CN102592673A

CN102592673A - Programming method for memorizer device

Info

Publication number: CN102592673A
Application number: CN2011100215283A
Authority: CN
Inventors: 蔡富凯; 刘建宏
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2011-01-13
Filing date: 2011-01-13
Publication date: 2012-07-18

Abstract

The invention discloses a programming method for a memorizer device. The memorizer device comprises a plurality of stations, wherein each station is provided with a plurality of programming states, and each programming state is provided with a corresponding program confirm (PV) level. The method comprises the following steps: a first sequential program shot is exerted to utilize a peak bias voltage corresponding to each programmed programming state to program a most rapid station of the memorizer device; the bias voltage is reduced, and a second sequential program shot is exerted to program the most rapid station of the memorizer device to reach N program shots; and the bias voltage when the number of the program shots are larger than N is added to program the slow-speed station of the memorizer device.

Description

A kind of programmed method of storage arrangement

Technical field

Embodiments of the invention relate to multilevel-cell formula (multi-level cell; MLC) programming of storage arrangement; And particularly, control about the program speed of MLC storage arrangement and to reading window in order to increase relevant for a kind of programmed method of storage arrangement.

Background technology

Known flash memory cell possibly be on the floating grid of DOPOS doped polycrystalline silicon for example with Charge Storage.Interior accumulate lotus changes the threshold voltage (Vt) of storage unit.In " reading " operation, be with reading the grid that voltage is applied to storage unit, and the storage unit programming state of corresponding indication (for example, conduction current) the expression storage unit of conducting whether.For example, possibly be designated as the digital value of " 1 " in the storage unit of " reading " operating period conduction current, and " reading " operating period not the storage unit of conduction current possibly be designated as the digital value of " 0 ".Can electric charge be added into floating grid, and electric charge is moved apart floating grid, in order to programming and eraseable memory unit (for example, in order to storage unit numerical value is changed over " 0 " from " 1 ").

The storer of another kind of pattern uses a kind of charge-trapping structure, but not is used in the conductive gate material in the floating grid device.The charge-trapping structure can have one or more unit (cell), and each unit comprises an electric charge capture layer and a non-conductive layer.When the structure of this kind pattern is programmed, possibly in electric charge capture layer, capture an electric charge, can not move through non-conductive layer can make it.Electric charge maybe be through electric charge capture layer be kept, till eraseable memory unit, under the situation that need not apply a kind of continuous electric power source, to keep data mode.These charge-trapping unit can be operating as double surface unit (two-sided cells).In other words, because electric charge does not move through non-conductive electric charge capture layer, so can the electric charge part be controlled at different charge-trapping locations.Therefore, (multi-bit cell, MBC), it can increase and can be stored in the data volume in the storage arrangement and need not waste more spaces possibly to make up so-called multi-bit cell.

Originally MBC can have a kind of erase status Vt and distributes, and each of storer possibly then be programmed to a kind of programming state of target.The Vt of target programmed state distributes and can have a kind of relevant programming affirmation (PV) level (for example, lower boundary).For the Vt closely with program bit distributes; Can be lower than the PV level with setting for, and can carry out the programming operation of two steps that comprise a coarse programming operation (rough program operation) and fine program operation (fineprogram operation) about the level of PV in advance of target programmed state.Yet programming generally only focuses on the position of lower boundary, and need not be careful the coboundary, and the coboundary possibly influence faster position.Therefore, possibly expect to develop a kind of in order to increasing the program that reads window about the program speed of MLC storage arrangement and control, with so that the negative effect of program distribution is minimized.

Summary of the invention

Therefore, embodiments of the invention are provided, but the providing of a kind of method in order to the storage arrangement of programming (for example, the MLC storage arrangement) of its activation, and this storage arrangement can be careful the position of coboundary.Therefore, for example, when increasing program speed, possibly control and read window margin (read windowmargins).In certain embodiments, maybe be through the bias voltage that is applied during the programming that is increased at a slow speed the position, to reduce the possibility of the excessive programming of position the most fast, still increase programming speed and the programming more quickly position at a slow speed of position at a slow speed simultaneously.

Implement in the example a kind of programmed method of storage arrangement to be provided one.Storage arrangement can comprise a plurality of position, and each position has a plurality of programming states, has a corresponding programming in each programming state wherein and confirms (program verify, PV) level.The method can comprise that the programming percussion (program shot) that applies one first order has the position the most fast of coming programming memory devices corresponding to a peaked bias voltage of each programming state that is programmed in order to utilization; Reduce bias voltage and pull the trigger N programming percussion of quick position arrival, and increase supplies to pull the trigger the at a slow speed position of the bias voltage of usefulness with programming memory devices greater than the programming of N with programming memory devices with the programming that applies one second order.

It will be understood by those skilled in the art that above-mentioned general remark and following detailed description are only to have illustrative purpose, and intention does not limit category of the present invention.

For there is better understanding above-mentioned and other aspect of the present invention, hereinafter is special lifts embodiment, and cooperates appended graphicly, elaborates as follows:

Description of drawings

Fig. 1 shows the general structure according to the charge capturing memory of the memory array of an enforcement example of the present invention;

Fig. 2 shows the Vt window according to each storage side of the charge capturing memory of Fig. 1 of an enforcement example of the present invention;

Coarse programming phases, and then two step program of the example in fine program stage are at first adopted in Fig. 3 demonstration;

Fig. 4 shows the demonstration programmed order according to the position of being careful high border of an enforcement example of the present invention;

Fig. 5 shows the programming operation Vd bias voltage (or BL bias voltage) of each side is pulled the trigger with programming pulse about each programming state among Fig. 2 according to an enforcement example of the present invention;

Fig. 6 show according to of the present invention one implement example about each programming state that Fig. 2 showed demonstration programme process flow diagram to each side; And

Fig. 7 for implement example according to the present invention one with increase the relevant operational flowchart of a demonstration methods that reads window about the program speed of MLC storage arrangement and control.

[main element symbol description]

10: charge capturing storage unit

12: substrate

14,16: the zone

18,22: the oxide layer zone

20: electric charge capture layer

24: grid

26: a left side stores side

28: the right side that stores

100,110,150,160,170: distribute

120:Vt distributes

200,202,204,206,208,210,212,214,216,300,305,310,330: operation steps

Embodiment

Explain more fully that referring now to accompanying drawing some embodiment of the present invention in down, wherein shows some embodiment of the present invention but not all enforceable aspects.Really, various embodiment of the present invention possibly specialized with many different forms, and should not be construed as limited to the embodiment that proposes in this; On the contrary, providing of these embodiment is to make this instructions will satisfy suitable legal requirements.For example, possibly make reference data to the direction and the orientation of vertical, level for example, diagonal line, the right side, a left side, forward and backward, side or the like in this; Yet those skilled in the art it should be noted that any direction and direction reference benchmark are example, and any specific direction or orientation can be depending on certain objects, and/or the orientation of certain objects, utilize it can make outgoing direction or direction reference benchmark.

It is a kind of in order to increasing the program that reads window about the program speed of MLC storage arrangement and control that some embodiment of the present invention can provide, with so that the negative effect of program distribution is minimized.Fig. 1 shows an a kind of example of charge capturing storage unit 10.Symmetrical regions and source (for example, the S/D zone 14 and 16) as shown in Figure 1, that charge capturing storage unit 10 can comprise a grid 24 and be communicated with semiconductor passage or substrate 12.Substrate 12 possibly pass through insulation course (for example, being respectively oxide layer zone 18 and 22) with grid 24 and separate with an electric charge capture layer 20.In this example configuration, the left side of electric charge capture layer 20 stores side 26 and possibly be programmed, and the right side of electric charge capture layer 20 storage side 28 possibly be programmed.

The left side that shown stores side 26 and right one of them that stores side 28 and possibly be programmed to one of four states (that is, state 00,01,10 and 11), with the data of store two bits.Because a key character that is accumulated as the multidigit programming of electric charge (more accurate charge arrangement being arranged in electric charge capture layer 20) is so possibly correctly reach higher figure place and status number.Generally can be for example through applying a current potential to grid 24 certain bits of programming, wherein one of them (for example, zone 16) in S/

D zone

14 and 16 in order to as a drain electrode, and another (for example, regional 14) in S/

D zone

14 and 16 are in order to as one source pole.The accumulation that is positioned at the electric charge of particular side changes a left side and stores side 26 or the right threshold voltage (threshold voltage) that stores side 28.For example, for reading numerical values 01 (being called level 1 again), between the leftmost point that the current potential that is applied possibly distribute at the rightmost point and the level 2 of level 1 distribution.Zone or window that current potential possibly must be deferred to the numerical value of these benchmark are called as " reading window ".

Fig. 2 shows the Vt window according to each storage side of an enforcement example.As be shown among Fig. 2, in each side one of four states (01,00,10 and 11) is arranged.In addition, each state has the distribution that comprises a lower boundary (PV) and a coboundary (or high border) (PV ').About reliable read operation, read and confirm that voltage (RD1, RD2, RD3) can be adjusted by dynamic with lower boundary based on the coboundary about the distribution of numerical value 01,00,10 and 11.

Fig. 3 shows at first adopt coarse programming phases demonstration two step program in fine program stage and then.As shown in Figure 3, in coarse programming phases, a plurality of position is programmed to a PV level in advance, and it is to be lower than some skew of PV level.During coarse programming phases; After some programming percussions; The position of storer is to be programmed to have Vt to distribute, and in wherein some has at least the same high Vt level of the level of PV in advance with target programmed state, and other has and is lower than the Vt level of PV level in advance.This storer can write down the position of passing through, and unsanctioned those positions possibly further be programmed through using the fine program stage.

In stage, possibly apply trickleer bias voltage to confirm all positions through the PV level at fine program, Vt distributes so that keep quite closely.In Fig. 3, the Vt that 100 expressions that distribute are not programmed state distributes, and 110 Vt that are illustrated in after the coarse programming phases that distribute distribute, and 120 Vt that are illustrated in after the fine program stage that distribute distribute.As shown in Figure 3, after coarse programming phases, the position possibly be programmed and influence high border the most fast, till passing through the PV level.These can influence program distribution owing to they also just are being programmed in the position the most fast.Therefore, according to this example, the position on high border very is not careful, and tight distribution is almost completely by the fine program stage.

Fig. 4 shows the demonstration programmed order according to the position of being careful high border of an enforcement example.As shown in Figure 4, after coarse programming and fine program, high border (PV ') be identical.In this, the Vt that 150 expressions that distribute are not programmed state distributes, and 160 Vt that are illustrated in after the coarse programming phases that distribute distribute, and 170 Vt that are illustrated in after the fine program stage that distribute distribute.It 160 is that Vt with respect to Fig. 3 distributes 120 and tightr that the Vt of Fig. 4 distributes.

During coarse programming phases, owing to pass through those positions of PV ' level, the position possibly just in time be programmed in one or two percussion the most fast.During the fine program stage, possibly carry out programming with respect to the position of having only the storer that does not pass through the PV level.Though high border can be careful, during the fine program stage, high border still possibly be affected and program speed maybe be slower slightly.Change if produce high border, then possibly be difficult to control and read window.Therefore, read the affirmation level, implement example and can reach the increase of reading ratio reliably that supplies the MLC storer to use through dynamic adjustment.

Fig. 5 shows about the programming operation Vd bias voltage (or BL bias voltage) and programming pulse percussion of each programming state among Fig. 2 (for example, 10,00 and 01) to each side.As can in Fig. 5, see capable of using being applied in position and the Vd bias voltage that increases in succession and be programmed the most fast in one or two percussion, to pass through PV '.When programming other when position faster, the Vd bias voltage can reduce and can keep suitable level, up to N programming pull the trigger be performed till, can be programmed speed in this N and control.Simultaneously, the Vd bias voltage can be maintained at quite low level, in order to these probability of position faster that reduce the high border of influence.About the programming of position at a slow speed, possibly increase the programming Vd bias voltage that applied so that gather way.Yet, as shown in Figure 5, can't surpass the highest numerical value of the Vd that is applied during the programming in position the most fast at the highest numerical value of the Vd that applied during the programming of position at a slow speed.Through adopting the program that Fig. 5 showed, possibly be reduced to previous programming confirm operation failure the faster possibility of position of excessive programming, and possibly increase program speed.

Fig. 6 shows about the demonstration programme process flow diagram of each programming state that Fig. 2 showed (for example 10,00 and 01) to each side.As shown in Figure 6, all positions at first possibly be examined to check whether they pass through PV in operation steps 200, to use is adopted a programming in advance to confirm that inspection is to determine whether to have the position that need be programmed.If all positions are passed through, then need not carry out programming further.Yet if some position is not passed through, this program possibly continue to the operation steps 202 that possibly carry out coarse programming.In operation steps 202 times, possibly increase by a coarse programming pulse to adopt a coarse Vd program distribution figure (BL bias voltage), till a position that has through PV ', and programming percussion number is to be subject to one or two percussion.So closing the inspection of not passing through PV ' at least one position possibly reach in 204 times quilts of operation steps.The position that in this program bit group, is programmed (or a plurality of position) is the quickest position.The selection of a kind of coarse Vd or Vg program distribution figure maybe be to attempt guaranteeing that at least one position of passing through is reached near the mode of PV ' level very much.

Pass through PV ' afterwards a position,, possibly increase by the first meticulous Vd programming pulse, and possibly keep down the BL bias voltage in operation steps 206 times, up to the number of programming pulse percussion till operation steps arrives numerical value of N 208 times.Program speed can be controlled by the selection of the numerical value of N pulse percussion.During this section, other quick position of possibly programming.Programming other fast after the position, possibly programme more at a slow speed through the numerical value that increases by one second fine program pulse and improve or increase Vd (BL bias voltage) in operation steps 210.In operation steps 212, possibly make again and guarantee of the inspection of at least one position through PV.If at least one position is programmed in operation steps 212; The programming of position at a slow speed that then increases via the second fine program pulse possibly continue in operation steps 214, and it is to check in operation steps 216 through in order to confirm that all positions are through till the PV up to one through keeping the BL bias voltage.Simultaneously, if at least one position is not programmed in operation steps 212, then possibly increase the BL bias voltage, it is through being to be programmed and through till the PV via the circulation again of operation steps 210 up to one.

What therefore, some enforcement example may command confession flash memory devices was used reads window margin and increases program speed.The position possibly be programmed through using one or two programming percussion the most fast; Till PV ' is passed through in a position; Then, possibly reduce and keep the BL bias voltage and programme other quick simultaneously, till N programming percussion (N is selected with control programming speed).Make position faster facilitate the possibility on high border through reducing the BL bias voltage, possibly reducing.Then, position programming maybe be through increasing the BL bias voltage at a slow speed, but maximum BL bias voltage is maintained be used for programming under the BL bias voltage of position the most fast and reach.Therefore, possibly reduce the faster possibility of position of excessive programming, and possibly increase program speed.

Fig. 7 for according to one that implement example with increase the relevant operational flowchart of a demonstration methods that reads window about the program speed of MLC storage arrangement and control.The combination that it will be understood by those skilled in the art that each square and the square in the process flow diagram of process flow diagram can be through various mechanism (for example under an operator control or via hardware, firmware, and/or comprising the software of one or more computer program instructions) and is implemented.For example, possibly specialize through the execution (having or do not have contribution) of computer program instructions in these illustrated one or more programs from operating personnel.In this, the computer program instructions of said procedure being specialized, is possibly store and pass through processor and carry out through storer.As will understand; Any such computer program instructions possibly be loaded on computing machine or other programmable device (that is; Hardware) on producing a machine, so that the device of the function that the instruction of on computing machine or other programmable device, carrying out is stated in detail in making up in order to the flowchart square.These computer program instructions also can be stored in an embodied on computer readable electron storage storer; It can indicate a computing machine or other programmable device to produce function with an ad hoc fashion, produces the article of the manufacturing of the instruction means that comprise the function of being stated in detail in the realization flow figure square so that be stored in the instruction of computer-readable access to memory.Computer program instructions also can be loaded on computing machine or other programmable device; With so that series of operation on computing machine or other programmable device, carry out to produce computer-implemented program, so that the function operations that the instruction of on computing machine or other programmable device, carrying out is stated in detail in providing in order to the flowchart square.

Therefore, the square support of process flow diagram is in order to the combination of the device of carrying out specific function, in order to carrying out the combination of operation of specified functions, and in order to carry out the program instruction means of specific function.Those skilled in the art also will appreciate that the combination of one or more squares and the square in the process flow diagram of process flow diagram can pass through specific purposes hardware type computer system (it carries out specific function or operation, or the combination of specific purposes hardware and computer instruction) and realize.

As shown in Figure 7; According to can comprising in order to increase the method that reads window about the program speed of MLC storage arrangement and control of an example: in operation steps 300 times, the programming percussion that applies one first order is in order to having the position the most fast of coming programming memory devices corresponding to the peaked bias voltage of each programming state that is programmed; In operation steps 310 times, reduce bias voltage and reach N programming in order to the programming percussion that applies one second order with the quick position of programming memory devices and pull the trigger; And, increase for greater than the bias voltage of the programming percussion of N position at a slow speed with programming memory devices in operation steps 330 times.

In certain embodiments, aforesaid operations possibly be described below and revised or be exaggerated.In addition, in some cases, except those of above-mentioned discussion, possibly implement operation further, an example wherein is to be shown among Fig. 7 with dotted line.Some or all modification, amplification and/or operation bidirectional maybe with any order with combine in certain embodiments with each possible combination.For example, in some cases, the method can more be included in before the operation steps 310 that continues second order, whether confirms border (PV ') through top programming in 305 times inspections of operation steps to check a position.In certain embodiments, increase to comprise and make bias voltage increase by the first progression quantity and determine whether extra bits passes through PV about bias voltage greater than the programming percussion of N.Implement in the example one, increase can comprise as long as additional bit through PV, is just kept the first progression quantity for the bias voltage of pulling the trigger greater than the programming of N.In certain embodiments, increase to comprise and makes bias voltage increase by the second progression quantity, with in response to the extra bits through PV not about bias voltage greater than the programming percussion of N.Implement in the example one, increase can comprise about the bias voltage of pulling the trigger greater than the programming of N increases bias voltage, till having increased each progression numerical value, but bias voltage is maintained below the maximal value corresponding to each programming state that is programmed.The numerical value of N maybe based on one the expectation program speed and be selected.Storage arrangement possibly be multilevel-cell formula (MLC) storage arrangement or a charge capturing memory device.In some cases, the programming percussion that applies first order can comprise and applies one or two programming percussion.Implement in the example one, the programming percussion that applies first order can comprise and applies bias voltage, so that bias voltage increases, and makes each the programming percussion that in the programming percussion of first order, is applied arrive maximal value.In certain embodiments; The programming percussion that applies first order can comprise adopts a coarse programming operation; Reduce bias voltage and can comprise with the programming percussion that applies second order and adopt the operation of one first fine program, and increase to comprise and adopt the operation of one second fine program about bias voltage greater than the programming percussion of N.

Those skilled in the art are when knowing in modification and other embodiment of the embodiment that this proposed, still can have the benefit of the instruction that is provided in above-mentioned explanation and the correlative type.Therefore, it will be understood by those skilled in the art that the present invention is subject to the specific embodiment that is disclosed, and modified version and other embodiment also are included within the claim scope of enclosing.In addition; Though above-mentioned explanation and correlative type are explained illustrative embodiments in the context of some illustrations combination of element and/or function, those skilled in the art should be understood that the different combinations of element and/or function possibly be provided through alternate embodiment not deviating under the claim scope of enclosing.In this, for example, the element except that above-mentioned those that specify and/or the different combinations of function also are considered and possibly in some encloses the claim scope, are suggested.Though adopt specific term in this, they only for the purpose that limits be not used with a kind of common and descriptive sense for the purpose that limits.

In sum, though the present invention discloses as above with embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defined.

Claims

1. the programmed method of a storage arrangement, this storage arrangement comprise a plurality of positions, and each position has a plurality of programming states, and each programming state has a corresponding programming and confirms (PV) level, and this method comprises:

Apply the one or more programmings percussions (program shot) of one first order (first sequence), have corresponding to programme a plurality of positions (fastest bits) the most fast of this storage arrangement of a peaked bias voltage of each programming state that is programmed in order to utilization;

Reduce this bias voltage applying the one or more programmings percussion of one second order (second sequence), reach N programming with a plurality of quick position (fast bits) of this storage arrangement of programming and pull the trigger; And

Increase is about greater than this bias voltage of a plurality of programmings percussion of N a plurality of positions (slow bits) at a slow speed with this storage arrangement of programming.

2. method according to claim 1 is characterized in that, increases about this bias voltage greater than a plurality of programmings percussions of N to comprise: make this bias voltage increase by one first progression quantity and determine whether an extra bits passes through PV.

3. method according to claim 2 is characterized in that, this bias voltage that increases about pulling the trigger greater than those programmings of N comprises: as long as this additional bit is just kept this first progression quantity through PV.

4. method according to claim 2 is characterized in that, increases about these bias voltages greater than those programming percussions of N to comprise: make this bias voltage increase by one second progression quantity, with in response to the extra bits through PV not.

5. method according to claim 2; It is characterized in that; Increase comprises about these bias voltages greater than those programming percussions of N: make this bias voltage increase each progression numerical value, but make this bias voltage maintain corresponding to this of respectively this programming state that is programmed below maximal value.

6. method according to claim 1 is characterized in that, the numerical value of N is based on the program speed of an expectation and is chosen.

7. method according to claim 1 is characterized in that, this memory device is changed to multilevel-cell formula (multi-level cell, MLC) storage arrangement.

8. method according to claim 1 is characterized in that, this memory device is changed to a charge capturing memory device.

9. method according to claim 1 is characterized in that, the programming percussion that applies this first order comprises that only applying one or two programming pulls the trigger.

10. method according to claim 1 is characterized in that, the programming percussion that applies this first order comprises and apply this bias voltage so that this bias voltage increases, and make in the programming percussion of this first order, applied respectively should programming pull the trigger this maximal value of arrival.

11. method according to claim 1 is characterized in that, more is included in to continue inspection before this second order, whether confirms border (PV ') through top programming to check a position.

12. method according to claim 1 is characterized in that, the programming percussion that applies this first order comprises adopts a coarse programming operation (rough programming operation).

13. method according to claim 12 is characterized in that, reduces this bias voltage and comprises employing one first fine program operation (first fineprogramming operation) with the programming percussion that applies this second order.

14. method according to claim 13 is characterized in that, this bias voltage that increases about pulling the trigger greater than those programmings of N comprises employing one second fine program operation (second fineprogramming operation).