CN102592673A - Programming method of memory device - Google Patents

Abstract

A method of programming a memory device includes a plurality of bits, each bit having a plurality of program states, wherein each program state has a corresponding Program Verify (PV) level. The method comprises the following steps: applying a first sequence of program shots to program the fastest bit of the memory device with a bias voltage having a maximum value corresponding to each program state being programmed; reducing the bias voltage to apply a second sequence of program shots to program fast bits of the memory device for N program shots; and increasing the bias voltage for a programming shot greater than N to program the slow bit of the memory device.

Description

A programming method for a memory device

technical field

Embodiments of the present invention relate to programming of a multi-level cell (multi-level cell, MLC) memory device, and in particular to a programming method of a memory device, for increasing the programming speed of the MLC memory device and for Read window for control.

Background technique

Known flash memory cells store charge on a floating gate, which may be, for example, doped polysilicon. The stored charge changes the threshold voltage (Vt) of the memory cell. In a "read" operation, a read voltage is applied to the gate of the memory cell, and a corresponding indication of whether the memory cell is on (eg, conducting current) indicates the programmed state of the memory cell. For example, a memory cell that conducts current during a "read" operation may be assigned a digital value of "1," while a memory cell that does not conduct current during a "read" operation may be assigned a digital value of "0." numeric value. Charge can be added to and removed from the floating gate for programming and erasing the memory cell (eg, to change the value of the memory cell from "1" to "0").

Another type of memory uses a charge trapping structure rather than the conductive gate material used in floating gate devices. The charge trapping structure may have one or more cells, and each cell includes a charge trapping layer and a non-conductive layer. When this type of configuration is programmed, a charge may be trapped in the charge trapping layer so that it does not move through the nonconductive layer. Charge may be maintained through the charge trapping layer until the memory cell is erased to maintain the data state without the need to apply a continuous power source. These charge trapping cells can be operated as two-sided cells. In other words, because the charge does not move through the non-conductive charge trapping layer, the charge can be locally controlled at different charge trapping locations. Thus, it is possible to construct so-called multi-bit cells (MBCs), which can increase the amount of data that can be stored in a memory device without wasting more space.

Initially the MBC may have an erased state Vt distribution, and each bit of the memory may then be programmed to a target programmed state. The Vt distribution of the target program state may have an associated program verify (PV) level (eg, lower boundary). In order to have a tight Vt distribution of programming bits, the pre-PV level for the target programming state may be set lower than the PV level, and a rough program operation and a fine program operation ( fineprogram operation) two-step programming operation. However, programming generally only focuses on the location of the lower boundary, without paying attention to the upper boundary, which may affect faster bits. Therefore, it may be desirable to develop a process for increasing the programming speed and controlling the read window for MLC memory devices in order to minimize the negative impact on the programming distribution.

Contents of the invention

Accordingly, embodiments of the present invention are provided which enable the provision of a method for programming a memory device, such as an MLC memory device, which takes care of the position of the upper boundary. Thus, for example, it is possible to control read window margins when increasing programming speed. In some embodiments, it is possible to program slow bits more quickly by increasing the bias voltage applied during programming of slow bits to reduce the likelihood of overprogramming of fastest bits, while still increasing the speed at which slow bits are programmed. Speed bit.

In an exemplary embodiment, a programming method of a memory device is provided. The memory device may include a plurality of bits, each bit having a plurality of programming states, wherein each programming state has a corresponding program verify (PV) level. The method may include applying a first sequence of program shots to program the fastest bits of the memory device with a bias having a maximum value corresponding to each programmed state being programmed, reducing the bias to apply A second sequence of programming shots to program the fast bits of the memory device up to N programming shots, and increasing the bias for programming shots greater than N to program the slow bits of the memory device.

It should be understood by those skilled in the art that the foregoing general description and the following detailed description are for illustrative purposes only and are not intended to limit the scope of the present invention.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples, together with the attached drawings, are described in detail as follows:

Description of drawings

FIG. 1 shows the general structure of a charge trapping memory of a memory array according to an exemplary implementation of the present invention;

FIG. 2 shows Vt windows of each storage side of the charge trapping memory of FIG. 1 according to an exemplary implementation of the present invention;

Figure 3 shows the two-step programming of an example using a coarse programming phase first, followed by a fine programming phase;

FIG. 4 shows an exemplary programming sequence for paying attention to the location of high margins according to an exemplary implementation of the present invention;

FIG. 5 shows the programming operation Vd bias (or BL bias) and programming pulse firing for each side of each programming state in FIG. 2 according to an exemplary implementation of the present invention;

FIG. 6 shows an exemplary program flow diagram for each side of each programming state shown in FIG. 2 in accordance with an exemplary implementation of the present invention; and

7 is a flowchart of operations associated with an exemplary method of increasing programming speed and controlling read windows for MLC memory devices in accordance with an exemplary implementation of the present invention.

[Description of main component symbols]

10: Charge Trapping Memory Unit

12: Substrate

14, 16: Area

18, 22: oxide layer area

20: Charge trapping layer

24: grid

26: left storage side

28: Right storage side

100, 110, 150, 160, 170: Distribution

120: Vt distribution

200, 202, 204, 206, 208, 210, 212, 214, 216, 300, 305, 310, 330: Operation steps

Detailed ways

Certain embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some but not all possible aspects of the invention are shown. Indeed, various embodiments of the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; The instructions will satisfy applicable legal requirements. For example, references may be made herein to directions and orientations such as vertical, horizontal, diagonal, right, left, front, rear, sideways, etc.; however, those skilled in the art should note that any directional and orientation references Datums are examples only, and any particular direction or orientation may depend on a particular object, and/or the orientation of a particular object, with which a direction or orientation reference datum may be made.

Certain embodiments of the present invention may provide a procedure to increase the programming speed and control the read window on MLC memory devices to minimize the negative impact on the programming distribution. FIG. 1 shows an example of a charge trapping memory cell 10 . As shown in FIG. 1 , charge trapping memory cell 10 may include a gate 24 and symmetric source/drain regions (eg, S/D regions 14 and 16 ) in communication with a semiconductor channel or substrate 12 . Substrate 12 and gate 24 may be separated from a charge trapping layer 20 by insulating layers (eg, oxide regions 18 and 22, respectively). In this example configuration, the left storage side 26 of the charge trapping layer 20 may be programmed, and the right storage side 28 of the charge trapping layer 20 may be programmed.

The shown left storage side 26 and right storage side 28 may be programmed to one of four states (ie, states 00, 01, 10, and 11) to store two bits of data. Because charge accumulation is an important feature of multi-bit programming (more precise charge distribution in the charge trapping layer 20), it is possible to correctly achieve higher bit and state numbers. A particular bit can generally be programmed, such as by applying a potential to gate 24, wherein one of S/D regions 14 and 16 (e.g., region 16) serves as a drain, and the other of S/D regions 14 and 16 The other (eg, region 14) is used as a source. Accumulation of charge on a particular side changes the threshold voltage of either the left storage side 26 or the right storage side 28 . For example, to read the value 01 (aka level 1), the applied potential may be between the rightmost point of the level 1 distribution and the leftmost point of the level 2 distribution. The region or window in which the potential must conform to the values of these references is called the "read window".

FIG. 2 shows Vt windows for each storage side according to an example implementation. As shown in Figure 2, there are four states (01, 00, 10 and 11) on each side. In addition, each state has a distribution that includes a lower bound (PV) and an upper bound (or upper bound) (PV'). For reliable read operations, the read verify voltages ( RD1 , RD2 , RD3 ) can be dynamically adjusted based on the upper and lower bounds for the distribution of values 01 , 00 , 10 and 11 .

Figure 3 shows exemplary two-step programming with a coarse programming phase followed by a fine programming phase. As shown in FIG. 3, in the coarse programming phase, bits are programmed to a pre-PV level, which is some offset below the PV level. During the coarse programming phase, after some programming shots, the bits of the memory are programmed to have a Vt distribution in which some bits have a Vt level at least as high as the pre-PV level of the target programming state, while other bits have A Vt level lower than the pre-PV level. This memory can record the bits that passed, while those that failed could be programmed even further by using the fine programming stage.

In the fine programming phase, finer biases may be applied to determine all bit pass PV levels in order to maintain a fairly tight Vt distribution. In FIG. 3, distribution 100 represents the Vt distribution for the unprogrammed state, distribution 110 represents the Vt distribution after the coarse programming phase, and distribution 120 represents the Vt distribution after the fine programming phase. As shown in Figure 3, after the coarse programming phase, the fastest bits may be programmed and affect the high boundary until the PV level is passed. These fastest bits can also affect the programming distribution as they are being programmed. Therefore, according to this example, the location of the high margin is not very well noticed, and the tight distribution depends almost entirely on the fine programming stage.

FIG. 4 shows an exemplary programming sequence for paying attention to the location of high margins according to an example implementation. As shown in Figure 4, the high margin (PV') is the same after both coarse and fine programming. In this regard, distribution 150 represents the Vt distribution for the unprogrammed state, distribution 160 represents the Vt distribution after the coarse programming phase, and distribution 170 represents the Vt distribution after the fine programming phase. The Vt distribution 160 of FIG. 4 is tighter than the Vt distribution 120 of FIG. 3 .

During the coarse programming phase, the fastest bits may be programmed in exactly one or two shots due to those bits passing the PV' level. During the fine programming phase, programming may be performed with respect to only bits of memory that fail the PV level. Although the high margins are taken care of, during the fine programming phase the high margins may still be affected and the programming speed may be slightly slower. If high boundary changes are produced, it may be difficult to control the read window. Thus, by dynamically adjusting the read acknowledge level, exemplary implementations can achieve a reliable increase in read rates for MLC memory.

FIG. 5 shows the programming operation Vd bias (or BL bias) and programming pulse firing for each side in FIG. 2 for each programming state (eg, 10, 00, and 01). As can be seen in Figure 5, the fastest bits can be programmed to pass PV' in one or two shots with successively increasing Vd biases applied. When programming other faster bits, the Vd bias can be reduced and maintained at a comparable level until N programming shots have been performed, at which point N can be controlled by the programming speed. At the same time, the Vd bias can be maintained at a relatively low level to reduce the probability of these faster bits affecting the high border. Regarding the programming of slow bits, it is possible to increase the applied programming Vd bias in order to increase the speed. However, as shown in FIG. 5, the highest value of Vd applied during the programming of the slow bits cannot exceed the highest value of Vd applied during the programming of the fastest bits. By employing the procedure shown in FIG. 5, it is possible to reduce the possibility of over-programming faster bits that fail previous program verify operations, and to increase the programming speed.

FIG. 6 shows an exemplary program flow diagram for each side for each of the programming states shown in FIG. 2 (eg, 10, 00, and 01). As shown in FIG. 6, all bits may first be checked to see if they pass PV in operation 200, thereby using a pre-program verification check to determine if there are bits that need to be programmed. If all bits pass, no further programming is required. However, if some bits do not pass, the process may continue to operation step 202 where coarse programming may be performed. At operation 202, a coarse programming pulse may be added to employ a coarse Vd programming profile (BL bias) until there is a bit through PV' and the number of programming shots is limited to one or two shots . A check as to whether at least one bit passes PV' may be done under operation 204. The bit (or bits) being programmed in this programming bit group is the fastest bit. A selection of coarse Vd or Vg programming profiles may be achieved in an attempt to ensure that at least one bit is passed very close to the PV' level.

After a bit passes PV', at operation 206, the first fine Vd programming pulse may be added, and the lower BL bias may be maintained until the number of programming pulse firings reaches the value N at operation 208. The programming speed can be controlled by the selection of the value of N pulse firing. During this time, other fast bits may be programmed. After programming other fast bits, slower bits may be programmed in operation 210 by adding a second fine programming pulse and raising or increasing the value of Vd (BL bias). In operation 212, a check may be made to ensure that at least one bit passes the PV. If at least one bit has been programmed at operation 212, slow bit programming via second fine program pulse increments may continue at operation 214 by maintaining the BL bias until a check is passed at operation 216 for Confirm that all bits pass PV so far. Meanwhile, if at least one bit is not programmed at operation 212, the BL bias may be increased by re-looping through operation 210 until a bit is programmed and passes PV.

Therefore, certain example implementations can control the read window margin for flash memory devices and increase programming speed. The fastest bits may be programmed using one or two programming shots until a bit passes PV', then the BL bias may be reduced and maintained while programming the other fast bits until N programming shots (N is chosen to be control programming speed). By reducing the BL bias, the likelihood of faster bits contributing to high margins may be reduced. Slow bit programming may then be achieved by increasing the BL bias while maintaining the maximum BL bias below the BL bias used to program the fastest bits. Thus, the likelihood of overprogramming faster bits may be reduced, and programming speed may be increased.

7 is a flowchart of operations associated with an exemplary method of increasing programming speed and controlling read windows for MLC memory devices, according to an exemplary implementation. Those skilled in the art will understand that each block of the flowchart and combinations of blocks in the flowchart can be implemented by various mechanisms (such as under the control of an operator or via hardware, firmware, and/or including one or software of a plurality of computer program instructions). For example, one or more of the procedures described herein may be embodied through the execution of computer program instructions (with or without human contribution). In this regard, computer program instructions embodying the above-mentioned program may be stored by a memory and executed by a processor. As will be appreciated, any such computer program instructions may be loaded onto a computer or other programmable device (i.e., hardware) to produce a machine such that the instructions executed on the computer or other programmable device are configured to Means for performing the functions detailed in the flowchart blocks. These computer program instructions can also be stored in a computer-readable electronic storage memory, which can instruct a computer or other programmable equipment to function in a specific way, so that the instructions stored in the computer-readable memory generate including implementation procedures An article of manufacture by means of instructions for the functions detailed in the figure block. Computer program instructions can also be loaded onto a computer or other programmable device to enable a series of operations to be executed on the computer or other programmable device to generate a computer-implemented program for execution on the computer or other programmable device. The instructions provide operations for performing the functions detailed in the flowchart blocks.

Accordingly, blocks of the flowchart support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and program instruction means for performing the specified functions. Those skilled in the art will also understand that one or more blocks of the flowchart illustrations, and combinations of blocks in the flowchart illustrations, can be implemented by special purpose hardware-based computer systems (which perform the specified functions or operations, or combinations of special purpose hardware and computer instructions) And realize.

As shown in FIG. 7 , according to an example, the method for increasing the programming speed and controlling the read window for an MLC memory device may include: under operation 300, applying a first sequence of programming shots to utilize programming the fastest bits of the memory device at a bias voltage of the maximum value of each programming state; at operation 310, lowering the bias voltage to apply a second sequence of programming shots to program the fastest bits of the memory device up to N programming firing; and at operation 330, increasing the bias voltage for the program firing greater than N to program the slow bits of the memory device.

In some embodiments, the operations described above may be modified or amplified as described below. Furthermore, in some cases further operations than those discussed above may be performed, an example of which is shown in dashed lines in FIG. 7 . Some or all of the modifications, amplifications, and/or additional operations may be combined in certain embodiments in any order and in every possible combination. For example, in some cases, the method may further include checking under operation 305 to see if a bit passes an upper program verify boundary (PV') before continuing with operation 310 of the second sequence. In some embodiments, increasing the bias voltage for program firings greater than N may include increasing the bias voltage by a first incremental amount and determining whether the additional bit passes through the PV. In an example implementation, increasing the bias for program firings greater than N may include maintaining the first incremental amount as long as additional bits pass through the PV. In some embodiments, increasing the bias voltage for programming fires greater than N may include increasing the bias voltage by a second incremental amount to account for the extra bits not passing through the PV. In an example implementation, increasing the bias for programming shots greater than N may include increasing the bias until each incremental value is increased, but maintaining the bias below a maximum value corresponding to each programmed state being programmed. . The value of N may be selected based on a desired programming speed. The memory device may be a multi-level cell (MLC) memory device or a charge trapping memory device. In some cases, applying the first sequence of programming shots can include applying one or two programming shots. In an example implementation, applying the first sequence of programming shots may include applying a bias voltage such that the bias voltage is increased such that each programming shot applied in the first sequence of programming shots reaches a maximum value. In some embodiments, applying a first sequence of programming shots may include employing a coarse programming operation, lowering the bias to apply a second sequence of programming shots may include employing a first fine programming operation, and increasing programming for greater than N Biasing for firing may include employing a second fine programming operation.

Modifications to the embodiments set forth herein, as well as other embodiments, will be appreciated by those skilled in the art while still having the benefit of the teachings provided in the foregoing description and associated drawings. Therefore, those skilled in the art will appreciate that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, although the above description and associated drawings illustrate exemplary embodiments in the context of certain exemplary combinations of elements and/or functions, those skilled in the art will appreciate that different combinations of elements and/or functions are possible without departing from the accompanying drawings. Alternative embodiments are provided below the scope of the claims. In this regard, for example, different combinations of elements and/or functions than those specified above are also contemplated as may be presented within the scope of some of the appended claims. Although specific terms are employed herein, they are used in a plain and descriptive sense for purposes of limitation only and not for limitation.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims (14)

1. the programmed method of a storage arrangement, this storage arrangement comprise a plurality of positions, and each position has a plurality of programming states, and each programming state has a corresponding programming and confirms (PV) level, and this method comprises:

Apply the one or more programmings percussions (program shot) of one first order (first sequence), have corresponding to programme a plurality of positions (fastest bits) the most fast of this storage arrangement of a peaked bias voltage of each programming state that is programmed in order to utilization;

Reduce this bias voltage applying the one or more programmings percussion of one second order (second sequence), reach N programming with a plurality of quick position (fast bits) of this storage arrangement of programming and pull the trigger; And

Increase is about greater than this bias voltage of a plurality of programmings percussion of N a plurality of positions (slow bits) at a slow speed with this storage arrangement of programming.

2. method according to claim 1 is characterized in that, increases about this bias voltage greater than a plurality of programmings percussions of N to comprise: make this bias voltage increase by one first progression quantity and determine whether an extra bits passes through PV.

3. method according to claim 2 is characterized in that, this bias voltage that increases about pulling the trigger greater than those programmings of N comprises: as long as this additional bit is just kept this first progression quantity through PV.

4. method according to claim 2 is characterized in that, increases about these bias voltages greater than those programming percussions of N to comprise: make this bias voltage increase by one second progression quantity, with in response to the extra bits through PV not.

5. method according to claim 2; It is characterized in that; Increase comprises about these bias voltages greater than those programming percussions of N: make this bias voltage increase each progression numerical value, but make this bias voltage maintain corresponding to this of respectively this programming state that is programmed below maximal value.

6. method according to claim 1 is characterized in that, the numerical value of N is based on the program speed of an expectation and is chosen.

7. method according to claim 1 is characterized in that, this memory device is changed to multilevel-cell formula (multi-level cell, MLC) storage arrangement.

8. method according to claim 1 is characterized in that, this memory device is changed to a charge capturing memory device.

9. method according to claim 1 is characterized in that, the programming percussion that applies this first order comprises that only applying one or two programming pulls the trigger.

10. method according to claim 1 is characterized in that, the programming percussion that applies this first order comprises and apply this bias voltage so that this bias voltage increases, and make in the programming percussion of this first order, applied respectively should programming pull the trigger this maximal value of arrival.

11. method according to claim 1 is characterized in that, more is included in to continue inspection before this second order, whether confirms border (PV ') through top programming to check a position.

12. method according to claim 1 is characterized in that, the programming percussion that applies this first order comprises adopts a coarse programming operation (rough programming operation).

13. method according to claim 12 is characterized in that, reduces this bias voltage and comprises employing one first fine program operation (first fineprogramming operation) with the programming percussion that applies this second order.

14. method according to claim 13 is characterized in that, this bias voltage that increases about pulling the trigger greater than those programmings of N comprises employing one second fine program operation (second fineprogramming operation).

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