201230045, Κ ?» ΓΧ 六、發明說明： 【發明所屬之技術領域】 本發明之實施例是有關於多層胞式（multi-level cell，MLC)記憶體裝置之編程，且特別是有關於一種用以 增加關於MLC記憶體裝置的編程速度與控制讀取視窗之方 法。 【先前技術】 習知之快閃記憶胞將電荷儲存在可能譬如是摻雜多 晶矽之浮動閘極上。内儲電荷改變記憶胞之臨界電壓 (Vt)。在「讀取」操作中，係將讀取電壓施加至記憶胞之 閘極，而記憶胞是否導通之相對應指示（例如，傳導電流） 表示記憶胞之編程狀態。舉例而言，在「讀取」操作期間 傳導電流之記憶胞可能被指定為「1」之數字值，而在「言買 取」操作期間並未傳導電流之記憶胞可能被指定為「0」 之數字值。可將電荷添加至浮動閘極，並將電荷移離浮動 閘極，用以編程並抹除記憶胞（例如，用以將記憶胞數值 從「1」改變成「0」）。 另一種型式之記憶體使用一種電荷捕捉構造，而非使 用於浮動閘極裝置中之導電閘材料。電荷捕捉構造可具有 一個或多個胞（cell)，每一胞包含一電荷捕捉層與一非導 電層。當此種型式之構造被編程時，可能在電荷捕捉層中 捕捉到一電荷，俾能使其不會移動通過非導電層。電荷可 能藉由電荷捕捉層而被維持，直到抹除記憶胞為止，藉以 在不需要施加一種連續的電力源的情況下維持資料狀 201230045 TW6585PA ， * 態。這些電荷捕捉胞可被操作為雙面胞（tw〇_sided cells)。換言之，因為電荷並未移動通過非導電電荷捕捉 層，所以可將電荷局部控制在不同的電荷捕捉地段。因 此，可能建構所謂的多位元胞（multi_bit cell，MBC)， 其可增加可被儲存於記憶體裝置中之資料量而不需要浪 費更多空間。 起初MBC可具有一種抹除狀態vt分佈，且記憶體之 每個位元可能接著被編程至一種目標的編程狀態。目標編 程狀態之Vt分佈可具有一種相關的編程確認（pv)位準（例 如，下邊界）。為了具有編程位元之緊密的vt分佈，可將 關於目標編程狀態之預先pV位準可能設定成低於pv位 準，並可執行包含一粗糙編程操作（r〇ugh program operation)與精細編程操作（f ine program operation) 之兩步驟之編程操作。然而，編程一般只聚焦在下邊界之 位置上，而不需要留意上邊界，而上邊界可能影響較快速 位兀。因此’可能期望發展一種用以增加關於MLC記憶體 裝置的編程速度與控制讀取視窗之程序，用以使對編程分 佈之負面影響最小化。 【發明内容】 因此，提供本發明之實施例，其可致能一種用以編程 一記憶體裝置（例如，MLC記憶體裝置）之方法之提供，此 記憶體裝置會留意上邊界之位置。因此，舉例而言，當增 加編程速度時’可能控制讀取視窗裕度（read wind〇w margins)。在某些實施例中，可能藉由增加在慢速位元之 201230045,201230045, Κ?» ΓΧ 6. Description of the Invention: [Technical Field] The present invention relates to programming of a multi-level cell (MLC) memory device, and particularly relates to a To increase the programming speed of the MLC memory device and the method of controlling the read window. [Prior Art] Conventional flash memory cells store charge on floating gates which may be, for example, doped polysilicon. The stored charge changes the threshold voltage (Vt) of the memory cell. In the "read" operation, the read voltage is applied to the gate of the memory cell, and the corresponding indication of whether the memory cell is turned on (for example, the conduction current) indicates the programmed state of the memory cell. For example, a memory cell that conducts current during a "read" operation may be assigned a digital value of "1", while a memory cell that does not conduct current during a "buy-and-buy" operation may be designated as "0". Digital value. Charge can be added to the floating gate and the charge removed from the floating gate to program and erase the memory cell (for example, to change the memory cell value from "1" to "0"). Another type of memory uses a charge trapping configuration rather than a conductive gate material for use in a floating gate device. The charge trapping structure can have one or more cells, each cell comprising a charge trapping layer and a non-conductive layer. When this type of configuration is programmed, it is possible to capture a charge in the charge trapping layer that will not move through the non-conductive layer. The charge may be maintained by the charge trapping layer until the memory cell is erased, thereby maintaining the data state 201230045 TW6585PA, * state without the need to apply a continuous power source. These charge trapping cells can be operated as tw〇_sided cells. In other words, because the charge does not move through the non-conductive charge trapping layer, the charge can be locally controlled in different charge trapping locations. Therefore, it is possible to construct a so-called multi-bit cell (MBC) which increases the amount of data that can be stored in the memory device without requiring more space. Initially the MBC may have an erase state vt distribution, and each bit of memory may then be programmed to a programmed state of the target. The Vt distribution of the target programming state may have an associated program acknowledgment (pv) level (e. g., lower boundary). In order to have a tight vt distribution of programming bits, the pre-pV level with respect to the target programming state may be set to be lower than the pv level, and may include a rough programming operation and a fine programming operation. (f ine program operation) Two-step programming operation. However, programming generally focuses only on the lower boundary, without the need to pay attention to the upper boundary, while the upper boundary may affect faster bits. Therefore, it may be desirable to develop a program to increase the programming speed of the MLC memory device and control the read window to minimize the negative impact on the programming distribution. SUMMARY OF THE INVENTION Accordingly, embodiments of the present invention are provided that enable the provision of a method for programming a memory device (e.g., an MLC memory device) that takes care of the location of the upper boundary. Thus, for example, when the programming speed is increased, it is possible to control the read wind 〇w margins. In some embodiments, it may be increased by 201230045 in the slow bit,
1 WOD53KA 編程期間所施加的偏壓，以減少最快速位元之過度編程之 可能性’同時仍然增加編私慢速位元之速度而更快速地編 程慢速位元。 在一實施示範例中，提供一種記憶體裝置之編程方 法。記憶體裝置可包含複數個位元，每個位元具有複數個 編程狀態’於其中每個編程狀態具有一對應的編程確認 (program verify ’ PV)位準。此方法可包括施加一第一順 序之編程擊發（program shot)用以利用具有對應於被編程 • 的各個編程狀態之一最大值之一偏壓來編程記憶體裝置 之隶快速位元’降低偏壓以施加一第二順序之編程擊發以 編程記憶體裝置之快速位元到達N個編程擊發，以及增加 供大於N之編程擊發用之偏壓以編程記憶體裝置之慢速位 元。 吾人應理解到上述的一般說明與下述的詳細說明係 僅具有例示的目的，且並未意圖限制本發明之範疇。 為了對本發明之上述及其他方面有更佳的瞭解，下文 •特舉實施例’並配合所附圖式，作詳細說明如下： 【實施方式】 現在將參考附圖更完全說明本發明之某些實施例於 下’其中顯不本發明之某些實施例而非所有可實施之態 樣的確’本發明之各種不同的實施例可能以許多不同的 形式被具體化，且不應被解釋為受限於於此所提出的實施 :田相反地’這些實施例之提供是能使這個揭露書將滿足 適用的法律需求。舉例而言，於此可能針 201230045 TW6585PA ， , 平、對角線、右、左、刖後、側面等等之方向與方位作 出參考基準；然而，吾人應注意到任何方向與方位參考其 準只是例子’且任何特定方向或方位可取決於特定物體， 及/或特定物體之方位，利用其可作出方向或方位參考基 準。 本發明之某些實施例可提供一種用以增加關於MLC 記憶體裝置的編程速度與控制讀取視窗之程序，用以使對 編程分佈之負面影響最小化。第1圖顯示一種電荷捕捉記 憶胞10之一例子。如第1圖所示，電荷捕捉記憶胞1〇可 包含一閘極24以及與一半導體通道或基板12連通之對稱 源極/汲極區域（例如，S/D區域14與16)。基板12與間 極24可能藉由絕緣層（例如’分別為氧化層區域18與22) 而與一電荷捕捉層20分離。於此例子組態中，電荷捕捉 層20之左儲存侧26可能被編程，而電荷捕捉層2〇之右 儲存侧28可能被編程。 所顯示的左儲存側26與右儲存側28可能被編程至四 個狀態（亦即，狀態〇〇、〇1、與u)之其中一個，藉以 儲存兩個位元之資料。因為電荷之累積係為多位元編^之 一項重要特徵（有更精確的電荷配置在電荷捕捉層2〇 中），所以可能正確達到較高的位元數與狀態數。一般可 譬如藉由施加一電位至閘極24而編程一特定位元，其中 S/D區域14與16之其中一個（例如，區域16)用以作為一 汲極，而S/D區域14與16之另一個（例如，區域14)用以 作為一源極。位於特定側之電荷之累積改變左儲存側26 或右儲存側28之臨界電壓（threshold v〇ltage)。舉例而 201230045, 1 言，為了讀取數值01(又稱為位準1)，所施加的電位可能 在位準1分佈之最右邊的點與位準2分佈之最左邊的點之 間。電位可能必須遵從這些基準之數值之區域或視窗係被 稱為「讀取視窗」。 第2圖顯示依據一實施示範例之每個儲存侧之視 窗。如顯示於第2圖中，於每一侧有四個狀態（〇1、、 10與11)。此外，每個狀態具有包含一下邊界（PV)與一上 邊界（或高邊界）（PV’）之分佈。關於可靠的讀取操作，讀 • 取確認電壓（RD1、RD2、RD3)可基於關於數值〇丨、〇〇、1() 與11之分佈之上邊界與下邊界而被動態調整。 第3圖顯示首先採用粗糙編程階段緊接著精細編程 階段之示範兩步驟編程。如第3圖所示，在粗趟編程階段 中’多個位元係被編程至一預先PV位準，其係低於^位 準某些偏移。在粗链編程階段期間’在一些編程擊發之 後，記憶體之位元係被編程以具有Vt分佈，於其中某此 位元具有至少與目標編程狀態之預先PV位準—樣高的Vt • 位準，而其他位元具有低於預先PV位準之Vt位準。此記 憶體可紀錄通過之位元，而未通過之那些位元可能藉由使 用精細編程階段而更進一步地被編程。 在精細編程階段中，可能施加更細微偏壓以確定戶斤有 位元通過PV.位準，以便維持相當緊密的Vt分佈。在第3 圖中，分佈100表示未被編程狀態之Vt分佈，分佈11Q 表示在粗糙編程階段之後之Vt分佈，而分佈120表示在 精細編程階段之後的Vt分佈。如第3圖所示，在粗輪編 程階段之後，最快速位元可能被編程並影響高邊界，直到 201230045 TW6585PA , , 通過PV位準為止。這些最快速位元由於它們正被編程亦 可影響編程分佈。因此，依據此例，高邊界之位置並未十 分被留意，而緊密分佈幾乎完全憑靠精細編程階段。 第4圖顯示依據一實施示範例之留意高邊界之位置 之示範編程順序。如第4圖所示，在粗糙編程與精細編程 兩者之後，高邊界（PV，）是相同的。在這點上，分佈150 表不未被編程狀態之Vt分佈，分佈16〇表示在粗糙編程 階段之後之Vt分佈’而分佈170表示在精細編程階段之 後的Vt分佈。第4圖之Vt分佈16〇係相對於第3圖之Vt 分佈120而更加緊密。 在粗糙編程階段期間，由於通過PV，位準之那些位 π，最快速位元可能在正好一個或兩個擊發中被編程。在 精細編程階段期間，可能相對於只有未通過”位準之記 憶體之位元執行編程。雖然高邊界會被留意，但在精細編 程階段期間，咼邊界仍然可能被影響且編程速度可能略微 較慢。如果產生向邊界改變，則可能難以控制讀取視窗。 因此，藉由動態調整讀取確認位準，實施示範例可達到供 MLC記憶體用之可靠的讀取比率的增加。 第5圖顯示關於第2圖中之每個編程狀態（例如，1〇、 00與01)對每一侧之編程操作Vd偏壓（或BL偏壓）與編程 脈衝擊發。如可在第5圖中看到的，最快速位元可利用被 施加而相繼增加的Vd偏壓而被編程以在一個或兩個擊發 中通過PV’。當編程其他較快速位元時，vd偏壓可減少並 可維持相當的位準’直到N個編程擊發已被執行為止，於 此N可被編程速度所控制。同時，w偏壓可維持於相當低 201230045,1 WOD53KA applies a bias voltage during programming to reduce the possibility of over-programming of the fastest bit' while still increasing the speed of the programmed slow bit and programming the slow bit faster. In an embodiment, a method of programming a memory device is provided. The memory device can include a plurality of bits, each bit having a plurality of programming states 'where each programming state has a corresponding program verify 'PV' level. The method can include applying a first sequence of program shots to program the fast bit of the memory device with a bias corresponding to one of a maximum of one of the programmed states being programmed. Pressing applies a second sequence of program firings to program the fast bits of the memory device to N programming firings, and increasing the bias for programming firings greater than N to program the slow bits of the memory device. It is to be understood that the following general description and the following detailed description are intended to be illustrative and not restrictive. In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments of the present invention will be described in the following: FIG. The various embodiments of the present invention may be embodied in many different forms and should not be construed as being limited by the present invention. Limited to the implementations presented herein: Conversely, the provision of these embodiments is such that the disclosure will satisfy applicable legal requirements. For example, this may refer to the direction and orientation of the 201230045 TW6585PA, flat, diagonal, right, left, rear, side, etc.; however, we should note that any direction and orientation reference is only The example 'and any particular direction or orientation may depend on the particular object, and/or the orientation of the particular object, with which direction or orientation reference can be made. Certain embodiments of the present invention may provide a procedure for increasing programming speed and control read windows with respect to MLC memory devices to minimize the negative impact on programming distribution. Figure 1 shows an example of a charge trapping memory cell 10. As shown in FIG. 1, the charge trapping memory cell 1 can include a gate 24 and a symmetrical source/drain region (e.g., S/D regions 14 and 16) in communication with a semiconductor channel or substrate 12. Substrate 12 and via 24 may be separated from a charge trapping layer 20 by an insulating layer (e.g., 'oxidation layer regions 18 and 22, respectively). In this example configuration, the left storage side 26 of the charge trap layer 20 may be programmed while the right storage side 28 of the charge trap layer 2 may be programmed. The displayed left storage side 26 and right storage side 28 may be programmed to one of four states (i.e., states 〇, 〇 1, and u) to store two bits of data. Since the accumulation of charge is an important feature of multi-bit programming (with a more accurate charge configuration in the charge trapping layer 2〇), it is possible to correctly achieve a higher number of bits and states. Typically, a particular bit can be programmed, for example, by applying a potential to the gate 24, wherein one of the S/D regions 14 and 16 (e.g., region 16) is used as a drain and the S/D region 14 is The other of 16 (e.g., region 14) is used as a source. The accumulation of charge on a particular side changes the threshold voltage (threshold v〇ltage) of the left storage side 26 or the right storage side 28. For example, 201230045, 1, in order to read the value 01 (also known as level 1), the applied potential may be between the rightmost point of the level 1 distribution and the leftmost point of the level 2 distribution. Areas or windows in which the potential may have to follow the values of these references are referred to as "read windows." Figure 2 shows a view of each storage side in accordance with an exemplary embodiment. As shown in Figure 2, there are four states (〇1, 10, and 11) on each side. In addition, each state has a distribution including a lower boundary (PV) and an upper boundary (or high boundary) (PV'). For reliable read operations, the read acknowledgment voltages (RD1, RD2, RD3) can be dynamically adjusted based on the upper and lower boundaries of the distribution of the values 〇丨, 〇〇, 1() and 11. Figure 3 shows an exemplary two-step programming that follows the coarse programming phase followed by the fine programming phase. As shown in Figure 3, in the rough programming phase, a plurality of bits are programmed to a pre-PV level, which is some offset below the ^ level. During the thick-chain programming phase, after some programming firings, the bits of the memory are programmed to have a Vt distribution, where one of the bits has a Vt of at least the pre-PV level of the target programming state. The other bits have a Vt level lower than the pre-PV level. This memory can record the bits passed, and those that fail cannot be further programmed by using the fine programming stage. In the fine programming phase, a finer bias may be applied to determine the position of the cell through the PV. level in order to maintain a fairly tight Vt distribution. In Figure 3, distribution 100 represents the Vt distribution of the unprogrammed state, distribution 11Q represents the Vt distribution after the coarse programming phase, and distribution 120 represents the Vt distribution after the fine programming phase. As shown in Figure 3, after the coarse wheel programming phase, the fastest bit may be programmed and affect the high boundary until 201230045 TW6585PA, through the PV level. These fastest bits can also affect the programming distribution as they are being programmed. Therefore, according to this example, the position of the high boundary is not noticed, and the tight distribution is almost entirely dependent on the fine programming stage. Figure 4 shows an exemplary programming sequence for the location of the high boundary in accordance with an embodiment. As shown in Figure 4, the high boundaries (PV,) are the same after both coarse programming and fine programming. In this regard, the distribution 150 represents the Vt distribution of the unprogrammed state, the distribution 16 〇 represents the Vt distribution after the rough programming phase and the distribution 170 represents the Vt distribution after the fine programming phase. The Vt distribution 16 of Fig. 4 is more closely related to the Vt distribution 120 of Fig. 3. During the coarse programming phase, the fastest bit may be programmed in exactly one or two firings due to the bits π through the PV. During the fine programming phase, programming may be performed relative to bits that only have memory that has not passed the "level." Although high boundaries are noticed, during the fine programming phase, the boundary may still be affected and the programming speed may be slightly lower. Slow. If a change to the boundary occurs, it may be difficult to control the read window. Therefore, by dynamically adjusting the read acknowledgment level, the implementation example can achieve an increase in the reliable read ratio for the MLC memory. Shows the programming operation Vd bias (or BL bias) and programming pulse firing for each side of each programming state (eg, 1〇, 00, and 01) in Figure 2. As seen in Figure 5 As a result, the fastest bit can be programmed to pass PV' in one or two firings with a Vd bias applied to it. The vd bias can be reduced and maintained when programming other faster bits. The equivalent level 'until N programming firings have been performed, where N can be controlled by the programming speed. At the same time, the w bias can be maintained at a relatively low 201230045,
TW6585PA 的位準，用以減少影響高邊界之這些較快速位元之概率。 關於慢速位元之編程，可能增加所施加的編程Vd偏壓以 便增加速度。然而，如第5圖所示，在慢速位元之編程期 間所施加的Vd之最高數值無法超過在最快速位元之編程 期間所施加的Vd之最高數值。藉由採用第5圖所顯示之 程序，可能降低於先前編程確認操作失敗的之過度編程的 較快速位元之可能性，且可能增加編程速度。 第6圖顯示關於第2圖所顯示之每個編程狀態（例如 • 10、00與01)對每一侧之示範程序流程圖。如第6圖所示， 所有位元首先可能被檢查以查看它們是否於操作步驟200 中通過PV，藉以採用一預先編程確認檢查以決定是否有需 要被編程之位元。如果所有位元通過，則不需要執行更進 一步的編程。然而，如果某些位元並未通過，則此程序可 能繼續進行至可能執行粗糙編程之操作步驟202。於操作 步驟202下，可能增加一粗糙編程脈衝以採用一粗糙Vd 編程分佈圖（BL偏壓），直到存在有通過PV ’之一個位元為 • 止，且編程擊發數目係受限於一個或兩個擊發。關於是至 少一位元否通過PV’之檢查可能於操作步驟204下被達 成。於此編程位元群組中被編程之位元（或多個位元）係為 最快速位元。一種粗糙Vd或Vg編程分佈圖之選擇可能以 試圖確保通過之至少一位元很靠近PV’位準的方式被達 成。 在一個位元通過PV’之後，於操作步驟206下，可能 增加第一精細Vd編程脈衝，且可能維持下BL偏壓，直到 編程脈衝擊發之數目於操作步驟208下到達數值N為止。The level of the TW6585PA is used to reduce the probability of these faster bits that affect high boundaries. Regarding the programming of the slow bit, it is possible to increase the applied programming Vd bias to increase the speed. However, as shown in Figure 5, the highest value of Vd applied during programming of the slow bit cannot exceed the highest value of Vd applied during programming of the fastest bit. By employing the procedure shown in Figure 5, it is possible to reduce the likelihood of over-programming faster bits that were previously programmed to confirm an operation failure, and may increase the programming speed. Figure 6 shows a flow chart of the exemplary program for each side of each programming state (e.g., 10, 00, and 01) shown in Figure 2. As shown in Figure 6, all of the bits may first be examined to see if they passed the PV in operation 200, thereby employing a pre-programmed check check to determine if there are any bits that need to be programmed. If all the bits pass, no further programming is required. However, if some of the bits have not passed, then the program may proceed to operation step 202 where rough programming may be performed. In operation 202, a rough programming pulse may be added to employ a coarse Vd programming profile (BL bias) until there is a pass through PV ', and the number of program firings is limited to one or Two shots. A check that at least one element is passed through PV' may be achieved in operation step 204. The bit (or bits) programmed in this programming bit group is the fastest bit. The choice of a coarse Vd or Vg programming profile may be achieved in an attempt to ensure that at least one bit passing through is close to the PV' level. After one bit passes PV', in operation 206, the first fine Vd programming pulse may be added, and the lower BL bias may be maintained until the number of programming pulse shots reaches the value N at operation step 208.
201230045 TW6585PA 編程速度^ 發之數值之卿所㈣。在這段 ^間叮P編程其他快速位元。在編程其他快速位元之 步驟21°藉由增加-第二精細編程脈衝並 ^5 d(BL偏壓）之數值來編程較慢速位元。於操 =1，可能再做出確保至少-位元_之檢查。 “心二」立70已於操作步驟212被編程，則經由第二精 細編程脈衝增加之慢祙/ 續，其係藉由維持程可能於操作步驟214繼 通過用以確認所有位元通過直^項檢查於操作步驟216 位兀並未則呆作步驟212 其係藉由經由操作步驟？1Λ 加BL偏壓’ 程並通過PV為止_之重新循環直到一位元係被編 取視窗因二施示範例可控制供快閃記憶裝置用之讀 :或=編程擊發而被編程，直到-個位元通:二 ，’二fw’可能減少並維持BL偏壓同時編程其他快t立 兀 個編程擊發（N係被選擇以控制編程速、、 藉r㈣偏壓，可能降低使較快速 备然後，慢速位元編程可能藉由增加乩偏壓，但 同夺使最大BL偏I維持在用來編程最快迷位元之乩偏壓 之下而達成’此’可能降低過度編程的較快速位元之可 能性’且可能增加編程速度。 第7圖係為依據一實施示範例之與增加關於ΜΙχ記憶 體裝置的編程速度與控制讀取視窗之一示範方法相關的 操作流程圖。吾人應理解流程圖之每個方塊以及流程圖中 201230045, 之方塊之組合可藉由各種不同的機制（例如在一操作員之 控制之下或經由硬體、韌體，及/或包含一個或多個電腦 程式指令之軟體）而實施。舉例而言，於此所說明的一個 或多個程序可能藉由電腦程式指令之執行（具有或不具有 來自操作人員的貢獻）而具體化。在這點上，將上述程序 之電腦程式指令具體化，係可能藉由記憶體而儲存並藉由 處理器而執行。如將明白的，任何這樣的電腦程式指令可 能被載入至電腦或其他可編程設備（亦即，硬體）之上以產 • 生一機器，以使在電腦或其他可編程設備上執行之指令建 構用以執行流程圖方塊中所詳載之功能之裝置。這些電腦 程式指令亦可被儲存於一電腦可讀取電子儲存記憶體，其 可指示一電腦或其他可編程設備以一特定方式產生功 能，以使儲存於電腦可讀取記憶體之指令產生包含實現流 程圖方塊中所詳載之功能之指令手段之製造之物品。電腦 程式指令亦可被載入至電腦或其他可編程設備之上，用以 使一系列的操作在電腦或其他可編程設備上執行以產生 • 電腦實施程序，以使在電腦或其他可編程設備上執行之指 令提供用以執行流程圖方塊中所詳載的功能之操作。 因此，流程圖之方塊支持用以執行特定功能之裝置之 組合，用以執行特定功能之操作之組合，以及用以執行特 定功能之程式指令裝置。吾人亦將理解到流程圖之一個或 多個方塊以及流程圖中之方塊之組合可藉由特殊目的硬 體式電腦系統（其執行特定功能或操作，或特殊目的硬體 與電腦指令之組合）而實現。 如第7圖所示，依據一個例子之用以增加關於MLC記 201230045 TW6585PA , , • . 憶體裝置之編程速度與控制讀取視窗之方法可包含：於操 作步驟300下，施加一第一順序之編程搫發以利用具有對 應於被編程之各個編程狀態之最大值之偏壓來編程記憶 體裝置之最快速位元；於操作步驟310下，降低偏壓用以 施加一第二順序之編程擊發以編程記憶體裝置之快速位 元達到N個編程擊發；以及於操作步驟33〇下，增加對於 大於N之編程擊發之偏壓以編程記憶體裝置之慢速位元。 在某些實施例中’上述操作可能如下所述被修正或被 放大。此外，在某些情況下，除了上述討論的那些以外，鲁 可能實施更進一步的操作’其之一例係以虛線顯;於第7 圖中。某些或所有的修改、放大及/或額外操作可能以任 何順序與以每個可能的組合而在某些實施例中結合。舉例 而言’在某些情況下’此方法可更包含在繼續第二順序之 操作步驟310之前，於操作步驟305下檢查以查看一個位 元是否通過一上部編程確認邊界（PV’）。在某些實施例中， 增加關於大於N之編程擊發之偏壓可包含使偏壓增加了第 一累進數量並決定額外位元是否通過PV。在一實施示範例鲁 中’增加對於大於N之編程擊發之偏壓可包含只要附加位 元通過PV ’就維持第一累進數量。在某些實施例中，增加 關於大於N之編程擊發之偏壓可包含使偏壓増加了第二累 進數量，以因應沒有通過PV之額外位元。在一實施示範 例中，增加關於大於N之編程擊發之偏壓可包含使偏壓增 加，直到增加了各個累進數值為止，但使偏壓維持在對應 於被編程之各個編程狀態之最大值以下。N之數值可能基 於一期望的編程速度而被選擇。記憶體裝置可能是一多層201230045 TW6585PA Programming speed ^ The value of the value of the Qing (four). During this period, 叮P programs other fast bits. In step 21 of programming other fast bits, the slower bit is programmed by increasing the value of the -second fine programming pulse and ^5 d (BL bias). In operation =1, it is possible to make a check to ensure at least - bit_. "Heart 2" 70 has been programmed in operation step 212, and is incremented by the second fine programming pulse, which may be passed through the maintenance step at operation step 214 to confirm that all bits pass through The item check is in operation step 216. If it is not in step 212, it is passed through the operation step. 1Λ Add BL bias 'process and re-circulate through PV until one-bit system is programmed to be controlled by the flash memory device for the reading of the flash memory device: or = programming firing, until - One bit pass: Second, 'two fw' may reduce and maintain the BL bias while programming other fast t-programming firings (N is selected to control the programming speed, r (four) bias, may be reduced to make faster preparation Then, slow bit programming may increase the 乩 bias, but the maximum BL bias I is maintained below the 乩 bias used to program the fastest pheromone to achieve 'this' may reduce over programming. The possibility of a fast bit 'and possibly increasing the programming speed. Figure 7 is an operational flow diagram relating to an exemplary method of increasing the programming speed of the memory device and controlling the read window in accordance with an exemplary embodiment. It should be understood that each block of the flowchart and the combination of blocks of 201230045, in the flowcharts, may be implemented by various mechanisms (for example, under the control of an operator or via hardware, firmware, and/or one or more Computer The software of the instructions is implemented. For example, one or more of the programs described herein may be embodied by the execution of computer program instructions (with or without contributions from an operator). In this regard, The computer program instructions of the above program may be stored by means of memory and executed by a processor. As will be understood, any such computer program instructions may be loaded into a computer or other programmable device (also That is, on top of the hardware to produce a machine for instructions executed on a computer or other programmable device to construct a device for performing the functions detailed in the flowchart block. Stored in a computer readable electronic storage memory that instructs a computer or other programmable device to generate functions in a particular manner such that instructions stored in the computer readable memory are generated as described in the implementation flow diagram block An article of manufacture that carries the functional instructions. Computer program instructions can also be loaded onto a computer or other programmable device to make a series of The operations are performed on a computer or other programmable device to generate a computer-implemented program to cause instructions executed on a computer or other programmable device to provide operations for performing the functions detailed in the flowchart block. The blocks support a combination of means for performing a particular function, a combination of operations for performing a particular function, and a program instruction device for performing a particular function. One or more blocks and flowcharts of the flowcharts will also be understood. The combination of the squares can be implemented by a special purpose hardware computer system (which performs a specific function or operation, or a combination of special purpose hardware and computer instructions). As shown in Figure 7, an example is used to increase Regarding the MLC 201230045 TW6585PA, , . . . the programming speed of the memory device and the method of controlling the read window may include: in operation 300, applying a first sequence of programming bursts to utilize the respective programming corresponding to being programmed The bias of the maximum value of the state to program the fastest bit of the memory device; in operation 310, the bias is lowered Pressing to apply a second sequential programming firing to program the fast bit of the memory device to N programming firings; and in operation 33, increasing the bias for programming firings greater than N to program the memory device Slow bit. In some embodiments, the above operations may be corrected or amplified as described below. In addition, in some cases, in addition to those discussed above, Lu may perform further operations, one of which is shown in dashed lines; in Figure 7. Some or all of the modifications, amplifications, and/or additional operations may be combined in any order and in every possible combination in some embodiments. For example, in some cases, the method may further include checking under operation 305 to see if a bit passes an upper programming confirmation boundary (PV') before proceeding to the second sequence of operation steps 310. In some embodiments, increasing the bias voltage for a programming firing greater than N may include increasing the bias voltage by a first progressive amount and determining whether the additional bit passes the PV. In an implementation example, increasing the bias for programming firings greater than N may include maintaining the first progressive amount as long as the additional bits pass through PV'. In some embodiments, increasing the bias voltage for a programming firing greater than N may include incrementing the biasing by a second progressive amount to account for the extra bits that have not passed through the PV. In an implementation example, increasing the bias voltage for a programming firing greater than N may include increasing the bias voltage until each progressive value is increased, but maintaining the bias voltage below a maximum value corresponding to each programmed state being programmed . The value of N may be selected based on a desired programming speed. The memory device may be a multi-layer
S 12 201230045, 胞式（MLC)記憶體裝置或一電荷捕捉記憶體裝置。在某些 情況下，施加第一順序之編程擊發可包含施加一個或兩個 編程擊發。在一實施示範例中，施加第一順序之編程擊發 可包含施加偏壓，以使偏壓增加，而使在第一順序之編程 擊發中所施加之每一個編程擊發到達最大值。在某些實施 例中，施加第=順序之編程擊發可包含採用一粗糙編程操 作，降低偏壓以施加第二順序之編程擊發可包含採用一第 一精細編程操作，以及增加關於大於N之編程擊發之偏壓 φ 可包含採用一第二精細編程操作。 熟習本項技藝者當知，於此所提出之實施例的修改與 其他實施例，仍可具有上述說明與相關圖式中所提供之教 導之益處。因此，相關技藝者應理解到本發明並非受限於 所揭露之具體實施例，且修改型式與其他實施例係亦包含 在以下申請專利範圍之範壽之内。此外，雖然上述說明與 相關圖式在元件及/或功能之某些例示組合之上下文中說 明例示實施例，但相關技藝者應該明白元件及/或功能之 • 不同的組合可能在不悖離以下申請專利範圍之範疇之下 藉由替代實施例而被提供。在這點上，舉例而言，除上述 所詳細說明的那些以外之元件及/或功能之不同的組合亦 被考慮可能在某些以下申請專利範圍中被提出。雖然於此 採用特定之用語，但它們只為了限制的目的與不為了限制 的目的而以一種普通且描述性意義被使用。 綜上所述，雖然本發明已以實施例揭露如上，然其並 非用以限定本發明。本發明所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作各種之更動 13 201230045S 12 201230045, Cellular (MLC) memory device or a charge trapping memory device. In some cases, applying a first sequence of programmed firings can include applying one or two programming shots. In an embodiment, applying the first sequence of program firings may include applying a bias to increase the bias voltage such that each programmed firing applied in the first sequential programming firing reaches a maximum value. In some embodiments, applying the = sequence of program firings can include employing a coarse programming operation, and reducing the bias voltage to apply the second sequence of programming firings can include employing a first fine programming operation and adding programming greater than N. The bias voltage φ of the firing may include a second fine programming operation. It will be apparent to those skilled in the art that the modifications and other embodiments of the embodiments presented herein may still have the benefit of the teachings provided in the above description and related drawings. Therefore, it is to be understood by those skilled in the art that the present invention is not limited to the specific embodiments disclosed, and the modifications and other embodiments are also included in the scope of the following claims. In addition, while the above description and the related drawings are illustrative of the embodiments in the context of some illustrative combinations of elements and/or functions, those skilled in the art will appreciate that the various combinations of elements and/or functions may not depart from the following The scope of the patent application is provided by an alternative embodiment. In this regard, for example, various combinations of elements and/or functions other than those specifically described above are also contemplated as may be presented in the scope of some of the following claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only for the purpose of limitation and not for the purpose of limitation. In summary, although the invention has been disclosed above by way of example, it is not intended to limit the invention. A person skilled in the art can make various changes without departing from the spirit and scope of the present invention. 13 201230045
1 W6585FA 附之申請專利範 與潤飾。因此，本發明之保護範圍當視後 圍所界定者為準。 【圖式簡單說明】 第1圖顯示録本發明之—實施示範例 列之電荷捕捉記憶體之一般結構； 〜陣 第2圖顯示依據本發明之眚絲+ # a丨 > 始 ^ 〈貫靶不靶例之第1圖之雷 何捕捉記憶體之每個儲存侧之η視窗； 屯 第3圖顯示首先採用粗键編程階段，緊接著精細編程 階段之例子之兩步驟編程； 第4圖顯示依據本發明之一實施示範例之留意高邊 界之位置之示範編程順序； 第5圖顯示依據本發明之一實施示範例之關於第2圖 中之每個編程狀態對每一側之編程操作Vd偏壓（或BL偏 壓）與編程脈衝擊發； 第6圖顯示依據本發明之一實施示範例之關於第2圖 所顯示之每個編程狀態對每一側之示範程序流程圖；以及 第7圖係為依據本發明一實施示範例之與增加關於 M L C記憶體裝置的編程速度與控制讀取視窗之一示範方法 相關的操作流程圖。 【主要元件符號說明】 10 :電荷捕捉記憶胞 12 :基板 14、16 :區域 201230045, 18、22 :氧化層區域 20 :電荷捕捉層 2 4 :閘極 26 :左儲存侧 28 :右儲存側 100、110、150、160、170 :分佈 120 : Vt分佈 200 、 202 、 204 、 206 、 208 、 210 、 212 、 214 、 216 、 • 300、305、310、330 :操作步驟1 W6585FA with patent application and retouching. Therefore, the scope of protection of the present invention is subject to the definitions defined in the following. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing the general structure of a charge trapping memory according to an exemplary embodiment of the present invention; FIG. 2 shows a twisted wire according to the present invention + # a丨> Figure 1 shows the η window of each storage side of the memory; 屯 Figure 3 shows the first step of programming with the thick key, followed by the two-step programming of the example of the fine programming stage; An exemplary programming sequence for indicating a position of a high boundary in accordance with an exemplary embodiment of the present invention is shown; FIG. 5 is a view showing a programming operation for each side of each of the programming states in FIG. 2 in accordance with an exemplary embodiment of the present invention Vd bias (or BL bias) and programming pulse firing; FIG. 6 is a flow chart showing an exemplary procedure for each side of each programming state shown in FIG. 2 in accordance with an exemplary embodiment of the present invention; 7 is an operational flow diagram associated with an exemplary method of increasing programming speed for an MLC memory device and controlling a read window in accordance with an exemplary embodiment of the present invention. [Description of main component symbols] 10: Charge trapping memory cell 12: Substrate 14, 16: Region 201230045, 18, 22: Oxide layer region 20: Charge trapping layer 2 4: Gate 26: Left storage side 28: Right storage side 100 , 110, 150, 160, 170: distribution 120: Vt distributions 200, 202, 204, 206, 208, 210, 212, 214, 216, • 300, 305, 310, 330: operational steps
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