CN102592661B - SRAM bit line leakage current compensation circuit - Google Patents
SRAM bit line leakage current compensation circuit Download PDFInfo
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- CN102592661B CN102592661B CN201210052508.7A CN201210052508A CN102592661B CN 102592661 B CN102592661 B CN 102592661B CN 201210052508 A CN201210052508 A CN 201210052508A CN 102592661 B CN102592661 B CN 102592661B
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- nmos pipe
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- 230000000694 effects Effects 0.000 description 7
- 230000002411 adverse Effects 0.000 description 6
- 230000003750 conditioning effect Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
The SRAM bit line leakage current compensation circuit is used as an auxiliary circuit of an SRAM circuit, and comprises two identical compensation circuits which jointly realize auxiliary compensation on an SRAM main circuit. Each compensation circuit is provided with two input/output ends, and one control signal CON is used for controlling the working mode of the bit line leakage current compensation circuit, each current compensation circuit comprises 5 PMOS tubes and 6 NMOS tubes, and the compensation circuit automatically enables a bit line signal at one end, which discharges slowly, in the main circuit to discharge more quickly and enables a bit line signal at one end, which discharges quickly, in the main circuit to discharge more quickly by detecting the change condition of the potential change rate on two bit lines in the main circuit in a normal working state, so that the influence of larger leakage current on an SRAM bit line on the main circuit is eliminated, and the correct identification of subsequent circuit signals is facilitated.
Description
Technical field
The present invention relates to a kind of SRAM bit line leakage current compensation circuit, belong to integrated circuit (IC) design technical field.
Background technology
In SRAM(static RAM of today) in application, increasing problem can constantly highlight along with the continuous progress of technology.One of them important problem is exactly that leakage current in SRAM can be along with constantly reducing of device threshold voltage exponential continuous increase.Although the existence of leakage current in SRAM circuit is inevitable, but excessive leakage current is but can not be uncared-for on the impact of SRAM, in the time there is larger bit line leakage current in SRAM circuit, thereby can cause two voltage differences between bit line reduce can cause correctly identification signal of subsequent conditioning circuit, particularly excessive bit line leakage current can produce very important impact to the normal read operations of SRAM, because the correct identification of its existence meeting severe jamming subsequent conditioning circuit SA to signal.Therefore, in the time there is larger bit line leakage current on the bit line of SRAM, just must take measures to eliminate the adverse effect of bit line leakage current to SRAM circuit, thus the stability of intensifier circuit.
For the problem that has larger leakage current on bit line, K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda has illustrated its bit line leakage current compensation circuit proposing in the article of the JSSC of 2001 a section " A Bitline Leakage Compensation Scheme for Low-Voltage SRAMs " by name, although the compensating circuit of this kind of structure can be realized the compensation object of bit line leakage current in theory, the adverse effect while there is larger leakage current in elimination circuit, SRAM circuit being caused, but due to its adopt be detect in advance leakage current then all compensation leakage compensated mode, so may exist SRAM performance to occur the problem declining in actual circuit is realized.
Summary of the invention
The object of the invention is by increasing auxiliary circuit, the SRAM circuit that has larger bit line leakage current to be compensated, thereby eliminate the adverse effect that in circuit, larger bit line leakage current produces circuit.
For achieving the above object, the technical solution adopted in the present invention is as follows:
A kind of SRAM bit line leakage current compensation circuit, is characterized in that, this circuit, as the auxiliary circuit of SRAM circuit, is provided with two identical compensating circuits and jointly realizes the auxiliary compensation to SRAM circuit (main circuit).Each compensating circuit comprises five PMOS pipe P1 ~ P5 and six NMOS pipe N1 ~ N6, the source of PMOS pipe P1 ~ P5 is connected and connects supply voltage VDD with body end separately respectively, the body end of NMOS pipe N1 ~ N6 all connects power supply ground VSS, the source of NMOS pipe N1, the source of NMOS pipe N2, the source of NMOS pipe N6 is connected with body end separately respectively, the drain terminal of PMOS pipe P1 connects the drain terminal of NMOS pipe N1, grid end and the drain terminal of the grid end of PMOS pipe P1 and PMOS pipe P2, the drain terminal of the drain terminal of PMOS pipe P3 and NMOS pipe N3 links together, grid end and the drain terminal of the grid end of PMOS pipe P3 and PMOS pipe P4, the drain terminal of the grid end of PMOS pipe P5 and NMOS pipe N4 links together, the grid end of the drain terminal of PMOS pipe P5 and NMOS pipe N1, the drain terminal of the grid end of NMOS pipe N2 and drain terminal and NMOS pipe N5 links together, the drain terminal of the source of NMOS pipe N5 and NMOS pipe N6, the source of the source of NMOS pipe N3 and NMOS pipe N4 links together, the grid end of NMOS pipe N6 is connected with external control signal, the grid end of NMOS pipe N4 in a compensating circuit and the drain terminal of NMOS pipe N1 are connected with two bit lines of SRAM circuit respectively after being connected with the drain terminal of the NMOS pipe N1 in another compensating circuit and the grid end of NMOS pipe N4 respectively.
Advantage of the present invention and showing effect: circuit of the present invention is as the auxiliary circuit of SRAM circuit, the bit line leakage current compensation circuit adopting has been abandoned that compensation mechanism of prior art completely, by detecting in normal operation the situation of change of the potential change rate on two bit lines in SRAM circuit, can automatically allow the slower one end bit line signal electric discharge of electric discharge in SRAM circuit slower, make one end bit line signal electric discharge faster of discharging in SRAM circuit faster, thereby eliminate the adverse effect of larger leakage current to main circuit on SRAM bit line, for the correct identification of subsequent conditioning circuit signal is offered help.
Brief description of the drawings
Fig. 1 is compensating circuit schematic diagram of the present invention (in two same circuits one);
Fig. 2 is the circuit model that has larger bit line leakage current for simulating SRAM;
Fig. 3 is for analyzing simplification circuit model of the present invention;
Circuit of the present invention is put into the way circuit schematic diagram after the circuit model of Fig. 2 by Fig. 4;
Fig. 5 is the signal simulation oscillogram that does not add bit line leakage current compensation circuit;
Fig. 6 is the signal simulation oscillogram of putting into bit line leakage current compensation circuit.
Embodiment
SRAM bit line leakage current compensation circuit of the present invention, as the auxiliary circuit of SRAM circuit, is provided with two identical compensating circuits and jointly realizes the auxiliary compensation to SRAM circuit (main circuit).Each compensating circuit (Fig. 1) comprises five PMOS pipe P1 ~ P5 and six NMOS pipe N1 ~ N6, the source of PMOS pipe P1 ~ P5 is connected and connects supply voltage VDD with body end separately respectively, the body end of NMOS pipe N1 ~ N6 all connects power supply ground VSS, the source of NMOS pipe N1, the source of NMOS pipe N2, the source of NMOS pipe N6 is connected with body end separately respectively, the drain terminal of PMOS pipe P1 connects the drain terminal of NMOS pipe N1, grid end and the drain terminal of the grid end of PMOS pipe P1 and PMOS pipe P2, the drain terminal of the drain terminal of PMOS pipe P3 and NMOS pipe N3 links together, grid end and the drain terminal of the grid end of PMOS pipe P3 and PMOS pipe P4, the drain terminal of the grid end of PMOS pipe P5 and NMOS pipe N4 links together, the grid end of the drain terminal of PMOS pipe P5 and NMOS pipe N1, the drain terminal of the grid end of NMOS pipe N2 and drain terminal and NMOS pipe N5 links together, the drain terminal of the source of NMOS pipe N5 and NMOS pipe N6, the source of the source of NMOS pipe N3 and NMOS pipe N4 links together, the grid end of NMOS pipe N6 is connected with external control signal CON, the Shu Ru ∕ output terminal that the drain terminal B of the grid end A of NMOS pipe N4 and NMOS pipe N1 is circuit.
Referring to Fig. 2, in circuit model of the present invention, there are two signal wire X and Y, represent respectively two bit lines of SRAM, capacitor C 1 and C2 are respectively used to simulate the load capacitance on X and Y, and are all set as 500pF.In circuit model, with a W=600nm, the NMOS pipe N1 of L=60nm simulates the working current of SRAM circuit, with a W=120nm, the NMOS pipe N2 of L=60nm simulates the bit line leakage current in SRAM circuit, can find out, in the time that circuit is started working, its working current is 5 times of bit line leakage current.CON is the control signal of circuit in addition, for the residing state of control circuit, when CON=" 0 ", the equal conducting of PMOS pipe P1 ~ P3 makes the current potential of two signal wires all in supply voltage VDD, now NMOS pipe N1 and N2 are also in cut-off state, so circuit is in precharging state, namely init state; And when CON=" 1 ", circuit enters duty, now NMOS pipe N1 and N2 conducting, PMOS pipe P1 ~ P3 cut-off, working current and bit line leakage current discharge to signal wire X and Y respectively.SA in figure is sense amplifier, for detection of and amplify two potential difference (PD) between signal wire.The supply voltage VDD of this circuit is set as 1.2V.
As Fig. 4, two Fig. 1 circuit are accessed after SRAM main circuit jointly, form the auxiliary circuit of SRAM main circuit, complete the compensation to SRAM main circuit.The grid end A(Y end of the NMOS pipe N4 of a circuit) with the drain terminal B(Y end of the NMOS pipe N1 of another circuit) be jointly connected a bit line Y(BLB of SRAM main circuit), the grid end A (X end) that the drain terminal B (X end) of the NMOS pipe N1 of a circuit manages N4 with the NMOS of another circuit is connected another root bit line X(BL of SRAM main circuit jointly).
Principle of work of the present invention is as follows:
As shown in Figure 1, the SRAM bit line leakage current compensation circuit proposing has adopted transistor P2 and the N2 that diode connects to manage and adopted current mirror technique, i.e. PMOS pipe P1 and PMOS pipe P2, and NMOS pipe N1 and NMOS pipe N2 form respectively current mirror.So, to analyze for convenient, this bit line leakage current compensation circuit can be reduced to circuit model as shown in Figure 3 further.Parameter alpha in figure and β represent the electric current magnification ratio of current mirror and equal respectively the ratio of PMOS in Fig. 1 pipe P1 and the wide length of P2 and the ratio of NMOS pipe N1 and the wide length of N2.Therefore, if PMOS pipe P1 mates respectively with N2 with P2, NMOS pipe N1, their breadth length ratio is identical, and the value of parameter alpha and β is just 1 so.And function ε (x) in figure represents in the time of x > 0, functional value is 1, and in the time of x < 0, functional value is 0.The characteristic of the one-way conduction of this circuit model based on diode and the principle of current mirror are simplified.That is to say, when the current i in figure
2be greater than i
1time, diode D1 conducting, the mirror image charging current that simultaneously has the electric current of the D1 that flows through is charged to input/output terminal B, on the contrary diode D1 will end, simultaneously mirror image charging current is also approximately 0; Similarly, when the current i in figure
3be greater than i
4time, diode D2 can conducting, the mirror image discharge current that simultaneously has the electric current of the D2 that flows through discharges to input/output terminal B, on the contrary diode D2 will end, mirror image discharge current is also approximately 0 simultaneously.
As shown in Figure 4, the circuit model of Fig. 2 is for representing the main circuit part of SRAM for the annexation of the circuit model of circuit of the present invention and Fig. 2.CON signal is outside input control signal, when CON=" 0 ", no matter SRAM main circuit all in init state, is now that A and the B signal wire current potential in X and Y-signal line or the bit line leakage current compensation circuit proposing in main circuit is supply voltage VDD with the bit line leakage current compensation circuit that proposes; And become after " 1 " as CON, circuit is started working.Similarly, working current is still set as 5 with the ratio of leakage current, and this is the ratio of the SR of two signal wires too.
And for proposed bit line leakage current compensation circuit, in the time that circuit is started working, if the SR of A is greater than the SR of B, A terminal potential will be more from original state VDD decline than B terminal potential so, so the electric current of flow through NMOS pipe N3 and N5 will be greater than the electric current of flow through PMOS pipe P3 and P5.This that is to say, i
2> i
1, i
4> i
3set up.This will cause diode D1 to open and D2 cut-off, as shown in Figure 3.Like this, B end will be by the current charges of coming from current mirror mirror image, and size is α (i
2-i
1), and mirror image charging current α (i
2-i
1) existence can make again the current potential of B end decline to obtain more slowly and to make conversely current i
2and i
4become larger.So the bit line leakage current compensation circuit proposing can make the slower end signal of electric discharge in main circuit discharge slower for main circuit provides positive feedback loop automatically.
On the contrary, if under original state, in the time that circuit is started working, the SR of A end signal is less than the SR of B end signal, and B terminal potential will be more from original state VDD decline than A terminal potential so, so have i
1> i
2, i
3> i
4set up.This will cause diode D2 to open and D1 cut-off, as shown in Figure 3.Like this, B end will be by the current discharge coming from current mirror mirror image, and size is β (i
3-i
4).And mirror image discharge current β (i
3-i
4) existence can make again the current potential of B end decline to obtain faster and make conversely current i
2and i
4become less.So this compensating circuit equally can be automatically makes in main circuit an electric discharge end signal electric discharge faster faster for main circuit provides positive feedback loop.
Like this, when SRAM main circuit is adopted after this compensating circuit, this bit line leakage current compensation circuit can be according to the situation of change of the potential change rate on two signal wires in main circuit, automatically allow the slower end signal electric discharge of electric discharge in main circuit slower, allow in main circuit an electric discharge end signal electric discharge faster faster, thereby the adverse effect of larger leakage current to SRAM circuit on elimination bit line, for the correct identification of subsequent conditioning circuit signal is offered help.
Figure 5 shows that the signal waveforms of the SRAM main circuit that does not add bit line leakage current compensation circuit, Figure 6 shows that the SRAM main circuit signal waveforms adding after bit line leakage current compensation circuit.As can be seen from Figure 5 the impact of larger bit line leakage current on circuit in SRAM, on bit line, thereby larger leakage current can cause the signal of the deficiency interfere with subsequent circuit that the potential difference (PD) of bit line sets up within the set time correctly to be identified, thereby the stability of SRAM circuit is constituted a threat to.After showing to adopt this bit line leakage current compensation circuit shown in Fig. 6, within the set time, can set up enough bit line potential difference (PD) to ensure the correct identification of subsequent conditioning circuit.Just because of this, thus just need to there is larger bit line leakage current on SRAM bit line time, need to compensate and eliminate the adverse effect of bit line leakage current to SRAM leakage current.
Claims (1)
1. a SRAM bit line leakage current compensation circuit, is characterized in that, this circuit, as the auxiliary circuit of SRAM circuit, is provided with two identical compensating circuits, and each compensating circuit comprises five PMOS pipe P1 ~ P5 and six NMOS pipe N1 ~ N6, the source of PMOS pipe P1 ~ P5 is connected and connects supply voltage VDD with body end separately respectively, the body end of NMOS pipe N1 ~ N6 all connects power supply ground VSS, the source of NMOS pipe N1, the source of NMOS pipe N2, the source of NMOS pipe N6 is connected with body end separately respectively, the drain terminal of PMOS pipe P1 connects the drain terminal of NMOS pipe N1, grid end and the drain terminal of the grid end of PMOS pipe P1 and PMOS pipe P2, the drain terminal of the drain terminal of PMOS pipe P3 and NMOS pipe N3 links together, grid end and the drain terminal of the grid end of PMOS pipe P3 and PMOS pipe P4, the drain terminal of the grid end of PMOS pipe P5 and NMOS pipe N4 links together, the grid end of the drain terminal of PMOS pipe P5 and NMOS pipe N1, the drain terminal of the grid end of NMOS pipe N2 and drain terminal and NMOS pipe N5 links together, the drain terminal of the source of NMOS pipe N5 and NMOS pipe N6, the source of the source of NMOS pipe N3 and NMOS pipe N4 links together, the grid end of NMOS pipe N6 is connected with external control signal, the grid end of NMOS pipe N4 in a compensating circuit and the drain terminal of NMOS pipe N1 are connected with two bit lines of SRAM circuit respectively after being connected with the drain terminal of the NMOS pipe N1 in another compensating circuit and the grid end of NMOS pipe N4 respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210052508.7A CN102592661B (en) | 2012-03-02 | 2012-03-02 | SRAM bit line leakage current compensation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210052508.7A CN102592661B (en) | 2012-03-02 | 2012-03-02 | SRAM bit line leakage current compensation circuit |
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| CN102592661B true CN102592661B (en) | 2014-08-27 |
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| CN111312303A (en) * | 2020-02-13 | 2020-06-19 | 深圳市紫光同创电子有限公司 | Method and device for compensating bit line leakage current of static random access memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101625891A (en) * | 2009-08-12 | 2010-01-13 | 东南大学 | Sub-threshold storing unit circuit with high density and high robustness |
| CN102176323A (en) * | 2010-12-31 | 2011-09-07 | 东南大学 | Storage unit circuit with adaptive leakage current cutoff mechanism |
| CN202549311U (en) * | 2012-03-02 | 2012-11-21 | 安徽大学 | SRAM bit line leakage current compensation circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101625891A (en) * | 2009-08-12 | 2010-01-13 | 东南大学 | Sub-threshold storing unit circuit with high density and high robustness |
| CN102176323A (en) * | 2010-12-31 | 2011-09-07 | 东南大学 | Storage unit circuit with adaptive leakage current cutoff mechanism |
| CN202549311U (en) * | 2012-03-02 | 2012-11-21 | 安徽大学 | SRAM bit line leakage current compensation circuit |
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