CN102592068B - The method and its system of malice circuit in fpga chip are detected using power consumption analysis - Google Patents
The method and its system of malice circuit in fpga chip are detected using power consumption analysis Download PDFInfo
- Publication number
- CN102592068B CN102592068B CN201110259418.0A CN201110259418A CN102592068B CN 102592068 B CN102592068 B CN 102592068B CN 201110259418 A CN201110259418 A CN 201110259418A CN 102592068 B CN102592068 B CN 102592068B
- Authority
- CN
- China
- Prior art keywords
- fpga chip
- power consumption
- tested
- wave data
- computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of system that malice circuit in fpga chip is detected using power consumption analysis, it includes：D.C. regulated power supply, to tested fpga chip and applies excitation fpga chip offer DC power supply；Current probe, measures the transient current of tested fpga chip power end；Oscillograph, under the triggering of the trigger signal of tested fpga chip generation, gathers the current signal that current probe measures；Apply excitation fpga chip, apply pumping signal to tested fpga chip, and the response signal of tested fpga chip is transmitted in computer, in case being verified compared with intended response；Computer, receives the incentives plus restraints that user writes, and produces test vector, and completes response check, oscillograph setting, Wave data collection, data analysis and processing work.The invention also discloses a kind of method that malice electric circuit inspection in fpga chip is carried out using said system.
Description
Technical field
The present invention relates to electric circuit inspection technology, more particularly to it is a kind of analyze in detection fpga chip the method for malice circuit and
Its system.
Background technology
In recent years, although the IC industry in China has obtained significant progress, many crucial, high-end, high-grade collection
Import is still relied primarily on into circuit (such as high-performance CPU, DSP, FPGA chips), these import integrated circuits are widely used in
The security sensitive such as national defense system, weaponry, government organs, finance, traffic, telecommunications field.Fpga chip therein is to weigh
What compounding was put, existing mainstream fpga chip is based on SRAM technology, its reality is determined by configuration data (bitstream)
The function of completion, this causes fpga chip in design, programmed configurations, the stage such as uses easily to be distorted by opponent so that
Great security risk is faced during using these chips：Opponent can distort bitstream configuration datas, so that past fpga chip
It is middle to add some extra malice circuits (these malice circuits are also referred to as " hardware Trojan horse ").Hardware Trojan horse may in the future certain
A moment is triggered or voluntarily triggered in some cases by opponent, upsets systemic-function so as to reach, makes what whole system failed
Purpose；And some hardware Trojan horses be triggered after encryption information, key etc. can be snugly leaked to opponent.Therefore, it is necessary to right
The detection method of malice circuit is studied in fpga chip.
The U.S. also carried at present from the malice circuit problem begun to focus in the configurable integrated circuit such as FPGA in 2007
The methods and techniques of some detection malice circuits are gone out.These methods and techniques are broadly divided into three major types：Based on failure analysis
Destructive physical detection methods, the electrical testing method based on ATPG (automatic test patterns generation), based on by-passing signal analyze
Nondestructive testing method.Detection method and the present invention wherein based on by-passing signal analysis is most close.So-called bypass letter
Number mainly include the signal such as caused heat, electromagnetic radiation, power consumption, time delay during chip operation, their feature and chip
The actual conditions of work are closely related, have closely contact.What Dakshi Agrawal of IBM et al. were delivered in 2007
《Trojan Detection using IC Fingerprinting》One text, proposes detect malice using power consumption analysis first
The method of circuit, this method with the invention belongs to same field.It it is also proposed similar method in addition with other researchers
And technology.
The existing achievement in research using power consumption analysis detection malice circuit is tested using simulation technology
Card (carries out analogue simulation to verify the validity of these achievements) by the software run on computers, goes back neither one reality
The hardware system on border can be used for the verification and confirmation of these achievements in research.The prior art also rests on the theory of malice electric circuit inspection
In research, emulation data analysis this aspect.If the fpga chip of a reality is given, due to lacking corresponding hardware detection
System, the prior art, which not can determine that, whether there is malice circuit in the fpga chip.
The content of the invention
In view of the shortcomings of the prior art, detected in fpga chip and disliked using power consumption analysis the object of the present invention is to provide one kind
The method and its system of meaning circuit, to being detected in tested fpga chip with the presence or absence of malice circuit (hardware Trojan horse), help
Suspicious fpga chip is rejected, so as to ensure the safety and reliability of the machine system using fpga chip.
To achieve these goals, the present invention is included using the system of malice circuit in power consumption analysis detection fpga chip：
D.C. regulated power supply, to tested fpga chip and applies excitation fpga chip offer DC power supply；Current probe, measurement are tested
The transient current of fpga chip power end；Oscillograph, under the triggering of the trigger signal of tested fpga chip generation, gathers electric current
The current signal that probe measurement arrives；Apply excitation fpga chip, give tested fpga chip to apply pumping signal, and by tested FPGA
The response signal of chip is transmitted in computer, in case being verified compared with intended response；Computer, receives what user write
Incentives plus restraints, produce test vector, and complete response check, oscillograph setting, Wave data collection, data analysis and processing work
Make.
Preferably, fpga chip is tested with applying the fpga chip of excitation to be located on same pcb board, and tested FPGA cores
Piece is installed to by way of IC sockets on the PCB.
Preferably, current probe is serially connected in the core power end of tested fpga chip and above-mentioned D.C. regulated power supply output terminal
Between.
Preferably, oscillograph is arranged to " single-trigger mode ", and the signal input part of oscillograph connects with the current probe
Connect, the triggering input terminal of oscillograph is connected with the trigger signal waveform output terminal of tested fpga chip, the data transfer of oscillograph
End is connected with computer respective input.
Preferably, apply excitation fpga chip output terminal be connected with the input terminal of tested fpga chip, and input terminal and
The corresponding output end of computer is connected.
Meanwhile a kind of method that malice circuit in fpga chip is detected using power consumption analysis of the invention includes following step
Suddenly：(101) incentives plus restraints that computer is provided according to user generate corresponding test vector；(102) power consumption Wave data is gathered；
(103) computer is handled and analyzed to the power consumption Wave data read from oscillograph, passes through relatively more tested FPGA cores
Whether the feature of the power consumption Wave data of piece and the feature with reference to fpga chip power consumption Wave data are consistent, to judge tested FPGA
It whether there is malice circuit in chip.
Preferably, in step (101), the incentives plus restraints are manually entered by user.
Preferably, in step (102), power consumption Wave data is comprised the steps of：(102a) computer passes through
Corresponding communication interface is configured oscillograph, sets it to be in " single triggering " pattern；(102b) computer passes through corresponding
Communication interface test vector be transferred to be responsible for apply excitation fpga chip；(102c) above-mentioned responsible FPGA for applying excitation
Chip produces corresponding pumping signal to drive tested fpga chip to work；(102d) is tested fpga chip and produces a triggering letter
Number, to trigger the current signal that measures of oscillograph collection current probe, the current signal multiplied by with supply voltage to obtain work(
Consume Wave data；(102e) computer check is tested the response signal of fpga chip return；(102f) computer is from oscillograph
Read its power consumption Wave data collected.
Preferably, in step (103), computer to the power consumption Wave data read from oscillograph carry out processing with
Analysis specifically includes：The input of (103a) data process＆analysis flow is the power consumption with reference to fpga chip and tested fpga chip
Wave data；(103b) eliminates measurement noise by being averaged to multiple power consumption waveforms；(103c) is calculated with reference to fpga chip
Grade Point Average power consumption profile Pmean；(103d) will all be subtracted with reference to all power consumption Wave datas of FPGA and tested fpga chip
Pmean；103e) projection subspace S is found using Eigenvalues Decomposition algorithm；(103f) is by with reference to FPGA and tested fpga chip
Power consumption Wave data is all projected on the S of subspace；(103g) compares the feature of above-mentioned two projection value.If feature is consistent, table
Malice circuit is not present in bright tested fpga chip, otherwise shows that there are malice circuit in tested fpga chip.
Compared with prior art：(1) present invention measures fpga chip power supply using high bandwidth, high-precision current probe
The transient current at end, realizes the high speed to the electric current, pinpoint accuracy measurement, with traditional voltage using sampling resistor both ends
Drop is compared to measure the method for electric current, current measurement precision higher of the invention.(2) using another fpga chip to tested
FPGA applies excitation so that tested FPGA can be worked normally, so as to measure to obtain the electric current under its normal operating conditions
Expenditure Levels, although integrated circuit ATE (automatic test equipment) can also complete this work, since ATE prices generally compare
Costly, therefore implementation of the present invention can greatly reduce the cost of detecting system.(3) inserted using integrated circuit
The mode of seat is installed to tested fpga chip in detecting system, so as to neatly realize the installation of tested fpga chip with unloading
Carry, avoid welding, also so that tested fpga chip may caused damage from welding process.(4) user is in computer
On write incentives plus restraints, the software on computer will automatically generate test vector according to these constraints, and by certain logical
These test vectors are sent to the fpga chip for being responsible for applying excitation by letter mode (such as RS-232 serial ports), are tested fpga chip
Under the excitation of pumping signal, some response signals can be returned to, these response signals can be sent in computer, by computer
In software verified, check whether it consistent with expected response signal.In the present invention, above-mentioned test vector generation and
Response check process is automated, and user need to only write incentives plus restraints, remaining work is all by the software in computer Lai complete
Into without user intervention.(5) present invention in waveform data collection be also automation, oscillograph drainage pattern and
The setting of relevant parameter, the Wave data collected are transmitted to computer these processes all by the software in computer from oscillograph
To control, intervene manually without user, reduce the workload of operating personnel.
The present invention is described in further detail below in conjunction with the accompanying drawings, but the present invention is not limited to these embodiments, it is any
Improvement or replacement on essence spirit of the present invention, still fall within scope claimed in claims of the present invention.
Brief description of the drawings
Fig. 1 is the detecting system composition schematic diagram of the present invention.
Fig. 2 is the tested fpga chip measurement of power loss result schematic diagram of the present invention.
Fig. 3 is the detection method flow chart of the present invention.
Fig. 4 is the flow chart of the power consumption wave data processing and analysis part in the detection method of the present invention.
Fig. 5 is " time bomb " malice circuit diagram.
Fig. 6 is the internal fpga chip to be measured there are malice circuit I and the power consumption Wave data with reference to fpga chip in son
The comparison diagram of projection value spatially.
Fig. 7 figures are that the internal fpga chip to be measured there are malice circuit I I exists with the power consumption Wave data with reference to fpga chip
The comparison diagram of projection value on subspace.
Embodiment
Referring to Fig. 1, the detecting system of the present invention is mainly by computer (including the software program run in computer), number
Word collection oscillograph, D.C. regulated power supply, current probe, application encourage fpga chip (also known as with reference to fpga chip) and are tested
The parts such as fpga chip (also known as fpga chip to be measured) form.D.C. regulated power supply gives tested fpga chip and applies excitation FPGA
Chip provides DC power supply.The transient current of the tested fpga chip power end of current probe measurement, which is multiplied by tested
The DC voltage of fpga chip, can obtain a power consumption profile measurement result (typical power consumption profile survey for tested fpga chip
The results are shown in Figure 2 for amount), in order to ensure the accuracy of measurement of power loss result, the bandwidth of current probe should in more than 200MHz, and
Should possess the measurement sensitivity of mA grades of electric currents；In addition, it is also noted that a fpga chip generally has three kinds of different types
Power end：The power end of internal logic power end, I O power supply end and on piece auxiliary logic, and the current probe in the present embodiment
It should be added on the internal logic power end of tested fpga chip, the current drain situation on remaining two kinds of power end is not concerned about.
Data acquisition oscillograph under the triggering of the trigger signal of tested fpga chip generation, believe by the electric current that collection current probe measures
Number, there is certain communication connection mode (such as gpib interface) between the oscillograph and computer, by these communication interfaces,
Software program in computer can set the drainage pattern of oscillograph, acquisition parameter；And the waveform number that oscillograph collects
According to also can by the communications interface transmission into computer, in case carry out next step data process＆analysis；This detecting system
In oscillograph, its bandwidth should be in more than 500MHz, more than sample rate 2GS/s.Apply excitation fpga chip to tested FPGA cores
Piece applies pumping signal, and the response signal of tested fpga chip is transmitted in computer, in case being compared with intended response
Compared with verification；There should be certain communication connection mode (such as RS-232 serial ports between the fpga chip and computer of application excitation
Deng).Tested fpga chip is located on same pcb board with applying the fpga chip of excitation, and tested fpga chip is inserted by IC
The mode (such as various BGA sockets) of seat is installed on the PCB；Tested fpga chip, which produces one, has obvious working status mark
The trigger signal that the enabling signal of will is sampled as oscillograph, by taking password encryption function as an example, if tested fpga chip is realized
One password encryption function, then it can generate a triggering with hopping edge at the time of each ciphering process starts
Signal.Computer is the control core of whole detecting system, it rely primarily on operation software program realize test vector generation,
The work such as response check, oscillograph setting, Wave data collection, data analysis and processing.
Referring to Fig. 3, using above-mentioned detecting system, the detection of malice circuit in fpga chip can be carried out, specific inspection
The flow of survey method is as follows：(1) user is manually entered incentives plus restraints, and the software program in computer is generated according to the constraint and tested
Vector；(2) power consumption Wave data gathers：A) oscillograph is set；B) test vector is applied to fpga chip；C) triggering oscillograph is adopted
The current signal that colleeting comb probe measurement arrives, current signal are multiplied by supply voltage and can obtain power consumption data；D) fpga chip is verified
The response signal of return；E) computer reads the power consumption Wave data that it is collected from oscillograph；(3) power consumption Wave data
Processing and analysis, the step for completed by the software program in computer, mainly pass through the power consumption of fpga chip more to be measured
Whether the feature of Wave data and the feature with reference to fpga chip power consumption Wave data are consistent, to judge to be in fpga chip to be measured
It is no that there are malice circuit.Need to compare fpga chip to be measured and the power consumption data with reference to fpga chip, can just detect to treat
Survey in FPGA and whether there is malice circuit.This with reference to fpga chip should model same with fpga chip to be measured, same to batch, Er Qieqi
Logic design process and program downloads process should be safely controllable, thus ensure with reference to be not inserted into inside fpga chip appoint
What malice circuit.
Referring to Fig. 4, power consumption wave data processing and the detailed process step analyzed are as follows：(1) data process＆analysis
The input of flow is the power consumption Wave data with reference to fpga chip and fpga chip to be measured；(2) by being taken to multiple power consumption waveforms
It is average, eliminate measurement noise；(3) the Grade Point Average power consumption profile P with reference to fpga chip is calculatedmean；(4) FPGA will be referred to and treated
All power consumption Wave datas for surveying fpga chip all subtract Pmean；(5) projection subspace S is found using Eigenvalues Decomposition algorithm；
(6) will all be projected on the S of subspace with reference to the power consumption Wave data of FPGA and fpga chip to be measured；(7) above-mentioned two throwing is compared
The feature of shadow value.If feature is consistent, shows that malice circuit is not present in fpga chip to be measured, otherwise show fpga chip to be measured
In there are malice circuit.
Following example produces an Xilinx company using detecting system provided by the invention and detection method
Fpga chip (Spartan-3E XC3S500E) carries out the example of malice electric circuit inspection.The fpga chip to be measured uses 90nm
CMOS technology manufactures, and scale is 500,000.In an experiment, we are patrolled by inside of the D.C. regulated power supply to fpga chip to be measured
Collect power end VCCINTThe DC voltage of 1.2V is provided, current probe selects the CT1 of Tektronix companies, and oscillograph is selected
Tektronix TDS3052B models.Communicated between oscillograph and computer by gpib interface, and apply excitation
Communicated between fpga chip and computer by RS-232 serial ports.The function that fpga chip to be measured is completed is one 64
Des encryption module.The malice circuit used in experiment is a coincidence counter (also known as " time bomb "), its circuit knot
Structure is as shown in Figure 5.The malice circuit sends out fpga chip internal logic after counter counts expire numerical value, by an XOR gate
Raw mistake.
In an experiment we used " time bomb " malice circuit of two different scales, difference lies in counting for they
The digit of device differs.Table 1 summarizes the situation of fpga chip internal logic resource to be measured shared by the two malice circuits.From this
Table understands that malice circuit I and malice circuit I I account for the 7.8% and 1.3% of 64 des encryption circuit gross areas respectively.
The situation of fpga chip internal logic resource to be measured shared by 1 two malice circuits of table
For above-mentioned actual conditions, using malice checking system for PCB provided by the invention and method to fpga chip to be measured
Malice electric circuit inspection is carried out, obtained experimental result is as shown in Figure 6 and Figure 7.In figure 6 and figure 7, we are to fpga chip to be measured
With measurement (every group of measurement 100 times, every time 10000 samplings of collection that 20 groups of power consumption datas have all respectively been carried out with reference to fpga chip
The data of point).Then using the power consumption wave data processing shown in Fig. 4 and analysis process at the power consumption data that collects
Reason.Finally we project on subspace (in figure 6 and figure 7, reference by FPGA to be measured and with reference to the power consumption data of fpga chip
The power consumption data projection value of fpga chip is labeled as " Golden ", the power consumption figure of the internal fpga chip to be measured there are malice circuit
Be respectively labeled as according to projection value " Trojan I " and " Trojan II "), and compare the feature of these projection values.In above-mentioned two
In figure, abscissa be subspace feature vector, ordinate is projection value, it can be seen that with reference to fpga chip projection value with
Becoming larger for feature vector, its average and variance all increasingly level off to 0, and the internal fpga chip there are malice circuit, its
Projection value becomes larger with feature vector, does not embody this feature, the i.e. feature of its projection value and reference fpga chip
The feature of projection value is inconsistent；And the scale of malice circuit is bigger, this feature inconsistency is more obvious.
Therefore, it is above-mentioned test result indicates that, using detecting system provided by the invention and method, can easily detect
(area is small to the 10 of reference circuit area for the malice circuit of micro scale in fpga chip-2Malice circuit again can be examined
Measure and), so as to help to reject suspicious fpga chip, ensure the safety and reliability of the machine system using fpga chip.
Claims (2)
- A kind of 1. method that malice circuit in fpga chip is detected using power consumption analysis, it is characterised in that it includes the following steps：(101) incentives plus restraints that computer is provided according to user generate corresponding test vector；(102) power consumption Wave data is gathered, power consumption Wave data is comprised the steps of：(102a) computer is configured oscillograph by corresponding communication interface, sets it to be in " single triggering " pattern；Test vector is transferred to the fpga chip for being responsible for applying excitation by (102b) computer by corresponding communication interface；(102c) above-mentioned responsible fpga chip for applying excitation produces corresponding pumping signal to drive tested fpga chip to work；(102d) is tested fpga chip and produces a trigger signal, to trigger the electric current letter that oscillograph collection current probe measures Number, the current signal multiplied by with supply voltage to obtain power consumption Wave data；(102e) computer check is tested the response signal of fpga chip return；(102f) computer reads its power consumption Wave data collected from oscillograph；(103) computer is handled and analyzed to the power consumption Wave data read from oscillograph, by relatively more tested Whether the feature of the power consumption Wave data of fpga chip and the feature with reference to fpga chip power consumption Wave data are consistent, to judge quilt Survey in fpga chip and whether there is malice circuit；Computer carries out the power consumption Wave data read from oscillograph processing and is specifically included with analysis：The input of (103a) data process＆analysis flow is the power consumption Wave data with reference to fpga chip and tested fpga chip；(103b) eliminates measurement noise by being averaged to multiple power consumption waveforms；(103c) calculates the Grade Point Average power consumption profile P with reference to fpga chipmean；(103d) will all subtract P with reference to all power consumption Wave datas of FPGA and tested fpga chipmean；(103e) finds projection subspace S using Eigenvalues Decomposition algorithm；(103f) will be all projected on the S of subspace with reference to the power consumption Wave data of FPGA and tested fpga chip；(103g) compares the feature of above-mentioned two projection value, if feature is consistent, shows that there is no malice in tested fpga chip Circuit, otherwise shows that there are malice circuit in tested fpga chip.
- 2. the method according to claim 1 that malice circuit in fpga chip is detected using power consumption analysis, it is characterised in that In step (101), the incentives plus restraints are manually entered by user.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110259418.0A CN102592068B (en) | 2011-09-05 | 2011-09-05 | The method and its system of malice circuit in fpga chip are detected using power consumption analysis |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110259418.0A CN102592068B (en) | 2011-09-05 | 2011-09-05 | The method and its system of malice circuit in fpga chip are detected using power consumption analysis |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102592068A CN102592068A (en) | 2012-07-18 |
| CN102592068B true CN102592068B (en) | 2018-04-27 |
Family
ID=46480698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110259418.0A Active CN102592068B (en) | 2011-09-05 | 2011-09-05 | The method and its system of malice circuit in fpga chip are detected using power consumption analysis |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102592068B (en) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102809725B (en) * | 2012-08-22 | 2015-04-15 | 武汉大学 | Sensitive element device for bypass signal of sensing circuit and detection method of sensitive element device |
| CN103777067B (en) * | 2012-10-19 | 2016-12-21 | 华为技术有限公司 | Chip power-consumption measuring circuit, chip and chip power-consumption measuring method |
| US8977902B2 (en) * | 2012-10-24 | 2015-03-10 | International Business Machines Corporation | Integrity checking including side channel monitoring |
| CN103197229B (en) * | 2013-04-02 | 2016-06-01 | 方波 | CDNA microarray test machine and testing method thereof |
| CN103884980B (en) * | 2014-03-13 | 2017-02-15 | 工业和信息化部电子第五研究所 | Hardware Trojan horse detection method and system based on supply current |
| CN103954904B (en) * | 2014-04-28 | 2016-08-24 | 工业和信息化部电子第五研究所 | hardware Trojan horse test system |
| CN104237768B (en) * | 2014-08-27 | 2017-02-15 | 工业和信息化部电子第五研究所 | Integrated circuit hardware Trojan horse detection method and system |
| CN104569700A (en) * | 2015-02-03 | 2015-04-29 | 上海观源信息科技有限公司 | Equipment power consumption acquiring device with various interfaces |
| CN104764992A (en) * | 2015-04-14 | 2015-07-08 | 江西科技学院 | Hardware Trojan detection method based on bypass analysis |
| CN105022860B (en) * | 2015-05-20 | 2018-05-04 | 工业和信息化部电子第五研究所 | PCB solder joint random vibration Prediction method for fatigue life and system |
| CN104951698B (en) * | 2015-06-24 | 2018-03-02 | 中国电子科技集团公司第五十八研究所 | The circuit safety design for Measurability method of inactive hardware Trojan horse and the detection method to hardware Trojan horse can be detected |
| CN105259491B (en) * | 2015-11-18 | 2018-07-20 | 上海兆芯集成电路有限公司 | Test device and test method with adaptive power adjustment |
| CN106126811A (en) * | 2016-06-22 | 2016-11-16 | 张升泽 | The power method for drafting of electronic chip and system |
| WO2017219279A1 (en) * | 2016-06-22 | 2017-12-28 | 张升泽 | Method and system for drawing power of electronic chip |
| CN106443423B (en) * | 2016-08-30 | 2019-10-11 | 中国电子科技集团公司第五十八研究所 | Two times of line fault test methods of fpga chip based on Virtex framework |
| CN106778263A (en) * | 2016-11-15 | 2017-05-31 | 天津大学 | Effectively improve the method that hardware Trojan horse activates probability |
| CN106841987B (en) * | 2017-01-25 | 2019-09-13 | 天津大学 | Hardware Trojan horse side channel detection method based on electromagnetism and electric current |
| CN106951746B (en) * | 2017-04-25 | 2020-01-21 | 厦门芯阳科技股份有限公司 | Method and system for preventing reverse cracking of temperature control program |
| US10685118B2 (en) | 2017-05-15 | 2020-06-16 | Ut-Battelle, Llc | System and method for monitoring power consumption to detect malware |
| DE102017219549A1 (en) * | 2017-11-03 | 2019-05-09 | Volkswagen Aktiengesellschaft | Method for condition monitoring of a production plant |
| CN108268776A (en) * | 2018-01-10 | 2018-07-10 | 中国人民解放军国防科技大学 | Hardware Trojan horse detection method combining infrared image and space projection conversion |
| CN108446555A (en) * | 2018-02-11 | 2018-08-24 | 复旦大学 | The method that hardware Trojan horse is monitored in real time and is detected |
| CN108629187B (en) * | 2018-05-03 | 2021-08-17 | 电子科技大学 | On-chip multiprocessor safety evaluation method |
| US11092648B2 (en) | 2019-04-15 | 2021-08-17 | Grammatech, Inc. | Systems and/or methods for anomaly detection and characterization in integrated circuits |
| US11074345B2 (en) | 2019-05-30 | 2021-07-27 | Ut-Battelle, Llc | Rootkit detection system |
| CN114236347A (en) * | 2021-11-30 | 2022-03-25 | 中国空间技术研究院 | Integrated circuit reserved instruction test circuit based on typical power consumption analysis |
-
2011
- 2011-09-05 CN CN201110259418.0A patent/CN102592068B/en active Active
Non-Patent Citations (3)
| Title |
|---|
| "硬件木马特征与检测技术";隋强等;《第十五届计算机工程与工艺年会暨第一届微处理器技术论坛论文集（A辑）》;20110812;第365页第3.2节 * |
| 《基于功率旁路泄露的硬件木马设计》;邹程等;《计算机工程》;20110630;第37卷(第11期);第135-137页 * |
| 《虚拟FPGA逻辑测试验证平台的设计》;王军;《万方学位论文》;20090821;正文第5-8页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102592068A (en) | 2012-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102592068B (en) | The method and its system of malice circuit in fpga chip are detected using power consumption analysis | |
| Guo et al. | A technique for fault diagnosis of defects in scan chains | |
| CN106066919B (en) | Statistical static timing analysis method applied to close/subthreshold value digital circuit | |
| Wei et al. | Provably complete hardware trojan detection using test point insertion | |
| CN104635144A (en) | Hardware trojan detection method independent of datum curve | |
| CN104569794A (en) | FPGA on-line tester based on boundary scan structure and testing method thereof | |
| CN107144779A (en) | PMU method of testings, device and system | |
| US7373619B2 (en) | Post-silicon test coverage verification | |
| US6970815B1 (en) | Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection system | |
| CN103926522A (en) | Hardware Trojan horse detecting and positioning method and system based on voltage | |
| Nelson et al. | Automatic classification of bridge defects | |
| CN112015604A (en) | Automatic reliability evaluation system and evaluation method based on Zynq FPGA | |
| CN106610462A (en) | Electronic system, system diagnostic circuit and operation method thereof | |
| CN109002714A (en) | Key node hardware Trojan horse detection method and device based on power consumption mean analysis | |
| CN110347595A (en) | A kind of FPGA internal resource is screened and localization method and system | |
| CN102608449B (en) | Electric stress limit evaluation method for gallium arsenide monolithic microwave power amplifier | |
| Jang et al. | Post-silicon timing validation method using path delay measurements | |
| CN103165405A (en) | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface | |
| CN106483950B (en) | Programmable logic device detection method and device | |
| CN102565664B (en) | Evaluation method for testing coverage rate | |
| CN105738795B (en) | A kind of overturning coverage rate detection method and device for chip checking after silicon | |
| CN108304659B (en) | A kind of Switching Power Supply testability analysis system and method based on LabVIEW platform | |
| Hung et al. | Linking the verification and validation of complex integrated circuits through shared coverage metrics | |
| Guo et al. | A new technique for scan chain failure diagnosis | |
| Grosso et al. | Software-Based Self-Test for Delay Faults |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: No. 78, Zhucun Avenue West, Zhucun street, Zengcheng District, Guangzhou, Guangdong 511300 Patentee after: CHINA ELECTRONIC PRODUCT RELIABILITY AND ENVIRONMENTAL TESTING Research Institute (THE FIFTH ELECTRONIC Research Institute OF MIIT)(CEPREI LABORATORY)) Address before: 510610 No. 110 Zhuang Road, Tianhe District, Guangdong, Guangzhou, Dongguan Patentee before: Fifth Electronics Research Institute of Ministry of Industry and Information Technology |
|
| CP03 | Change of name, title or address |