CN102591719A

CN102591719A - Interrupt expansion method based on 8051 CPU system

Info

Publication number: CN102591719A
Application number: CN2011100096049A
Authority: CN
Inventors: 薛重阳
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2011-01-17
Filing date: 2011-01-17
Publication date: 2012-07-18

Abstract

Disclosed is an interrupt expansion method based on an 8051 CPU (central processing unit) system. Using a combination of hardware expansion and traditional software queries, the method realizes the expansion treatment for 8051 CPU system with multiple interrupt sources. The method comprises firstly establishing an interrupt expansion processing module between a system program memory and the 8051 CPU; when 8051 CPU issues access to an interrupt address, using the interrupt expansion processing module to detect and intercept; returning the data according to an interrupt priority vector table and simulating long transfer instructions; and when 8051 CPU receives returned data, obtaining the long transfer jump address, executing the long transfer jump instructions to jump to a corresponding function and entering the interrupt processing. With the interrupt expansion method provided by the invention, processing speed of the multiple interrupt sources in 8051 CPU system can be effectively improved.

Description

A kind of interruption extended method based on the 8051CPU system

Technical field

The present invention relates to a kind of interrupt method, relate in particular to a kind of interruption extended method based on the 8051CPU system.

Background technology

8051CPU (8 single-chip CPU) as the system of classics, is applied to the every field of electron trade.Interrupt source in general situation of 8051CPU system comprises external interrupt 0, external interrupt 1, and timer interrupts 0, and timer interrupts 1 and interrupts with serial.Along with increasing of peripheral hardware, for the interruption of 8051 systems of one process bigger demand is arranged, and higher requirement is also arranged for interrupt response.Along with the continuous increase of interrupt source, a plurality of interrupt sources use the interruption inlet of a 8051CPU inevitable.

When the system break source is not enough, just need original interruption be expanded.The general employing of tradition interrupt source extension realization mode is connected to some interruptions in the interruption of 8051CPU together; An and externally integrated interrupt inquiry register; When interrupting taking place, realize this register of inquiry earlier by software; The corresponding interruption handled in selection more as required, and its execution efficient of the implementation method of this interrupt source expansion is lower.

Be the mode that solution is realized by software, the problem that the interrupt source expansion efficiency is lower, it is higher to design a kind of execution efficient, and can be technology contents to be solved by this invention by the interrupt source extended method of hardware and software realization.

Summary of the invention

The object of the invention provides a kind of interruption extended method based on the 8051CPU system, and the implementation that adopts the inquiry of hardware expanding and traditional software to combine can effectively improve the processing speed in multiple interrupt source in the 8051CPU system.

A kind of interruption extended method based on the 8051CPU system comprises following content:

(1) in the middle of system program storer and 8051CPU, sets up interruption extension process module;

(2) interrupt extension process module detection 8051CPU and whether begin to get into the interrupt routine processing;

When (3) 8051CPU sends certain interrupt address of visit, interrupt the extension process module and detect and tackle, also simulate the long jump instruction of shifting according to interrupt priority level vector table return data;

(4) after 8051CPU receives return data, obtain the long jump address that shifts, the executive chairman shifts jump instruction and jumps to corresponding function, gets into Interrupt Process;

(5) interrupt the extension process module and continue interception, and return corresponding address successively, carry out system break and handle according to interrupt address inlet vector table.

Interrupting the extension process module provides interrupt priority level control vector table, interrupts the entry address vector table and interrupts access detection three partial contents.The interrupt priority level vector is used to judge the preferential interrupt handling routine that gets into when multiple interrupt triggers simultaneously, and the user can be configured according to application.Interrupt address inlet vector table is used to provide the entry address of interrupt routine, and the user also can be configured according to demand.Interrupt access detection, be used to detect 8051CPU and when visit interrupt routine and offer and interrupt the extension process module and handle.

Description of drawings

Fig. 1 interruption extended method provided by the invention basic flow sheet

The interruption extension process electrical block diagram of Figure 28 051CPU system

Fig. 3 interrupts the inside realization synoptic diagram of extension process module

Long transfer instruction order code in the 8051CPU instruction set among Fig. 4 embodiment

Embodiment

Below in conjunction with each accompanying drawing, the content that the present invention proposes is carried out detailed description.

Fig. 1 has provided the interruption extended method basic flow sheet based on the 8051CPU system provided by the invention.It is example that case of external interrupts 0, interrupts the extension process module and is arranged between 8051CPU and the program storage, as shown in Figure 2.When central stopping pregnancy is given birth to, interrupt the extension process module and start working, detect 8051CPU and whether begin to get into the interrupt routine processing.At first produce interrupt trigger signal on the external interrupt 0,8051CPU gets into the Interrupt Process process, therefrom breaks read-in programme data on the port address.When the address of external interrupt 0 acquiescence enters the mouth is 0003, and then 8051CPU will visit 0003 this address and read interrupt handling routine.

When 8051CPU sends visit 0003 address, detect and tackle by interrupting the extension process module, return data 02 is also simulated the long jump instruction of shifting.8051CPU can continue the address that visit 0004,0005 address obtains redirect after having received 02 instruction, it is as shown in Figure 4 that length shifts jump instruction.Interrupt the extension process module and continue interception, and return corresponding address successively according to the interrupt address vector table.After 8051CPU obtains data, will the executive chairman shift jump instruction and jump to corresponding function, accomplish the different Interrupt Process of 8051CPU.Interrupting the extension process inside modules realizes as shown in Figure 3.

Claims

1. interruption extended method based on the 8051CPU system, its characteristic in step do,

2. a kind of interruption extended method based on the 8051CPU system as claimed in claim 1 is characterized in that said interruption extension process module provides the content of interrupt priority level control vector table, interruption entry address vector table and interruption access detection.

3. according to claim 1 or claim 2 a kind of interruption extended method based on the 8051CPU system is characterized in that said interrupt priority level vector is used to judge the preferential interrupt handling routine that gets into when multiple interrupt triggers simultaneously, and the user can be configured according to application.

4. according to claim 1 or claim 2 a kind of interruption extended method based on the 8051CPU system is characterized in that said interrupt address inlet vector table is used to provide the entry address of interrupt routine, and the user can be configured according to application.

5. according to claim 1 or claim 2 a kind of interruption extended method based on the 8051CPU system is characterized in that said interruption access detection is used to detect 8051CPU and when visits interrupt routine and offer and interrupt the extension process module and handle.