CN102577147A

CN102577147A - Transmission line transceiver for simultaneous bi-directional communication

Info

Publication number: CN102577147A
Application number: CN2009801615161A
Authority: CN
Inventors: 伯恩哈德·鲁斯
Original assignee: Inovys Corp
Current assignee: Advantest Corp
Priority date: 2009-10-20
Filing date: 2009-10-20
Publication date: 2012-07-11
Anticipated expiration: 2029-10-20
Also published as: KR101341205B1; TWI448097B; KR20120051072A; CN102577147B; TW201138337A; WO2011047695A1

Abstract

A line transceiver comprises a transmit driver, a current sensing element and a compensation circuit. The transmit driver is able to excite a transmit signal at a common transmit/receive node in dependence on a transmit data. The current sensing element provides a sense signal in dependence on a sense current. Further, the compensation circuit generates a compensation current in dependence on the transmit data, wherein the transmit driver and the compensation circuit are configured to comprise an opposite effect on the sense signal, so that a receive signal incident to the common transmit/receive node causes a larger change of the sense current than a transmit signal of the same signal strength excited by the transmit driver.

Description

The transmission line transceiver that is used for two-way communication simultaneously

Technical field

Relate to intercommunication system simultaneously according to embodiments of the invention, and relate to the method for carrying out the circuit transceiver of two-way communication simultaneously and carrying out two-way communication simultaneously through transmission line particularly through transmission line.

Background technology

When data when a direction from transmitted from transmitter to receiver is sent out, high-speed serial data is transmitted in greater than having its superperformance in 1G bps the scope.When realize at place, the two ends of data link transmitter and receiver both the time, can on both direction, transmit data through same physical circuit.Yet, because the electrical length (Td) of circuit itself, have the stand-by period of 2*Td between the data burst in different directions, this be because of the data that receive will be in this times prior by the transmission data corruption.

The method of a kind of being called " simultaneously two-way " is solved this problem by exploitation.

Figure 14 shows basic principle.The two ends of data link 1400 have driver (D1 and D2) and comparator (C1 and C2) both.Driver is represented as the switch that between two stationary singnals, switches, and wherein control signal is digital data stream DD1, DD2.The threshold value of comparator (input) is switched between two values, the control signal that wherein is used for switch also from DD1, DD2 via delay line DEL1, DEL2 and draw.As a result, when only the driver of same link side was just switching, the positive and negative input of comparator equated basically.Different ground, C1 can not see the activity from D1, and C2 can not see the activity from D2.

In most applications, the circuit on the both sides of link is identical, and this makes VTH1=VTH2 and VTL1=VTL2.

Other conventional example for example based on to the use of differential voltage amplifier from composite voltage signal, to deduct the voltage signal that sent or based on to the complementary version of signal transmitted and the use of active or passive summation.

The document that this problem is handled for example has: " Cecchi, Hanson, Preuss:A 2GB/SHigh Speed Link with Simultaneous Bi-directional IO; CICC 2001 ", " Yeung, Horowitz:A 2.4Gb/s Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation; IEEE Journal of S olid-State Circuits Vol.35, No.11, Nov.2000 " and " Casper; Martin, Jaussi, Kennedy; Mooney:An 8-Gb/sSimultaneous Bidirectional Link With On-Die Waveform Capture; Journal of Solid-State Circuits Vol.38, No.12, Dec.2003 ".

Summary of the invention

An object of the present invention is to provide the improvement notion that is used for carrying out two-way communication simultaneously through transmission line.

This purpose perhaps solves according to the method for claim 28 or 29 through the device according to claim 1 or 15.

One embodiment of the present of invention provide a kind of circuit transceiver that is used for carrying out through transmission line two-way communication simultaneously.This circuit transceiver comprises transmission driver, current sensing element and compensating circuit.Sending driver is configured to excite the transmission signal according to sending data at common transmission/receiving node place.Current sensing element is configured to according to current sensor sensing signal is provided.In addition, compensating circuit is configured to generate offset current according to sending data.Send driver and compensating circuit and be configured to comprise adverse effect current sensor; So that with compare by the transmission signal that sends the same signal intensity that driver excites, get into the more about-face that the reception signal of transmission/receiving node jointly will cause current sensor.

The another kind of circuit transceiver that is used for carrying out through transmission line two-way communication simultaneously is provided according to another embodiment of the present invention.This circuit transceiver comprises transmission driver and combiner.Send driver be configured to through will send jointly/receiving node is pulled to by sending the voltage that data confirm and inspires the transmission signal.In addition; Combiner is configured to first signal of the voltage at the common transmission/receiving node place of expression combined to obtain sensing signal with the secondary signal of the driver current of representing to be provided by the transmission driver; So that with compare by the transmission signal that sends the same signal intensity that driver inspires, get into the more about-face that the reception signal of transmission/receiving node jointly will cause sensing signal.

According to embodiments of the invention based on following central idea: the signal that sensing signal sends the driver current of driver based on current sensor or expression is generated; With sensing signal the dependence of the reception signal that gets into common transmission/receiving node is compared, it almost is independent of the signal that is sent out.This is to excite the transmission signal that the influence of sensing signal is realized through compensation institute at least in part.Therefore, can easily distinguish and send signal and receive signal, although they the two signal component possibly appear at common transmission/receiving node place simultaneously.In according to some embodiments of the present invention, utilize and send signal and the offset current that driver excited or represent the adverse effect of the electric current of driver current sensing signal.By this way, compare, can make the transmission signal keep lower for the change of sensing signal or current sensor with the sensing signal that causes by the reception signal that gets into or the change of current sensor.The sensitivity of using described notion can reduce hardware energy and/or can improve the circuit transceiver.

Description of drawings

To be described in detail with reference to the attached drawings subsequently according to embodiments of the invention, in the accompanying drawings:

Fig. 1 a, Fig. 1 b are the block diagrams that carries out the circuit transceiver of two-way communication simultaneously through transmission line;

Fig. 2 a, Fig. 2 b are the block diagrams that carries out the circuit transceiver of two-way communication simultaneously through transmission line;

Fig. 3 is the sketch map of the electronic circuit of expression circuit transceiver;

Fig. 4 is the sketch map of the electronic circuit of expression circuit transceiver;

Fig. 5 is the sketch map of the electronic circuit of expression circuit transceiver;

Fig. 6 is the sketch map of the electronic circuit of expression circuit transceiver;

Fig. 7 is the sketch map of the electronic circuit of expression circuit transceiver;

Fig. 8 is the block diagram that carries out the circuit transceiver of two-way communication simultaneously through transmission line;

Fig. 9 is the block diagram that carries out the circuit transceiver of two-way communication simultaneously through transmission line;

Figure 10 is the sketch map of the electronic circuit of expression circuit transceiver;

Figure 11 is the sketch map of the electronic circuit of expression circuit transceiver;

Figure 12 is the flow chart that is used for carrying out through transmission line the method for two-way communication simultaneously;

Figure 13 is the flow chart that is used for carrying out through transmission line the method for two-way communication simultaneously; And

Figure 14 is the sketch map of the electronic circuit of the expression known line transceiver that is used for two-way communication simultaneously.

Embodiment

Below, same numeral partly is used to have the object and the functional unit of identical or similar functions characteristic, and when embodiment is described in order to reduce redundancy, also will be applicable to other figure with respect to a width of cloth figure to its description.

Because the two ends of data link (transceiver at the place, two ends of transmission line) is made up of substantially the same circuit, so all following examples will only illustrate an end of link.The other end of link can be envisioned for identical set.Alternatively, the transceiver at the other end place of transmission line can be based on another notion of two-way communication simultaneously.

Fig. 1 a and Fig. 1 b show the block diagram that transmission line carries out the circuit transceiver 100,150 of two-way communication simultaneously that passes through according to the embodiment of the invention.Circuit transceiver 100,150 comprises transmission driver 110, current sensing element 120 and compensating circuit 130.Send driver 110 and can inspire the transmission signal at common transmission/receiving node 112 places according to sending data DD.Current sensing element 120 provides sensing signal SI according to current sensor IB.In addition, compensating circuit 130 generates offset current IC according to sending data DD.Send driver 110 and comprise adverse effect current sensor IB with compensating circuit 130; So that compare, get into the more about-face that the reception signal of transmission/receiving node 112 jointly will cause current sensor ID with the transmission signal that sends the same signal intensity that driver 110 inspires.In addition, show the transmission line TL that is not circuit transceiver 100,150 parts.

Comprise the adverse effect to current sensor IB owing to sending driver 110 with compensating circuit 130, therefore current sensor IB can almost keep constant when transmission driver 110 inspires the transmission signal.By contrast, the reception signal of entering is not compensated by compensating circuit 130 influence of current sensor IB.Therefore, receiving signal can easily be detected by current sensing element, and this is the more about-face that can cause current sensor IB because of the reception signal of comparing entering with the transmission signal of same signal intensity.By this way, can reduce hardware energy.In addition, be detected more easily because electric current changes than the voltage change, the sensitivity that therefore is used for the circuit transceiver of sensing reception signal can be improved.

Receive signal and the change ratio that sends the current sensor IB between the signal and to receive signal relevant with the same signal intensity of sending signal, so that be that the checking of the change ratio of current sensor provides definition status.Use for routine, the signal strength signal intensity of the reception signal of entering also maybe greater than or be lower than the signal strength signal intensity of sending signal.As long as receive signal to the influence of current sensor greater than the influence of sending signal, receive signal and just can be detected, and separate based on sensing signal SI quilt and transmission signaling zone.

Common transmission/receiving node or another representative node 112 places that signal with same signal intensity for example can be defined in transceiver comprise identical amplitude.For example, the amplitude of the transmission signal of transmission line TL one side can comprise the amplitude identical with the amplitude of the transmission signal of the transceiver of transmission line opposite side, similar amplitude or be arranged in the amplitude of the same area with it.

In the embodiment of Fig. 1 a, the transmission driver 110 of circuit transceiver 100, the compensating circuit 130 of circuit transceiver 100 and transmission line TL are connected to common transmission/receiving node 112.In addition, the current sensing element 120 of circuit transceiver 100 is connected to and sends driver 110.Inspire at common transmissions/receiving node 112 places when sending signal when sending driver 110, the voltage change at common transmission/receiving node 112 places, and like this, the electric current through transmission line TL also changes.When lacking offset current, cause through exciting of common transmission/receiving node 112, by the change of sending the electric current I B that driver 110 provides by offset current IC compensation or almost compensated.Therefore, current sensor IB keeps constant or almost constant.In other words, current sensor IB can be maintained at almost constant value, and this value also can equal 0.If signal is received through transmission line TL, then the voltage at transmission/receiving node 112 places and electric current I B also are changed jointly.Yet this electric current changes not by compensating circuit 130 compensation.Therefore, current sensor IB is according to receiving signal change.This change can be detected and corresponding sense signals SI can be provided by current sensing element 120.

Alternatively, current sensing element 120 provides current sensor IB, shown in the embodiment of Fig. 1 b.In this example; The compensating circuit 130 and the transmission line TL of the transmission driver 110 of circuit transceiver 150, the current sensing element 120 of circuit transceiver 100, circuit transceiver 150 are connected to common transmission/receiving node 112; Wherein current sensing element 120 is connected to this common transmission/receiving node with compensating circuit 130 through coupling element 102 (for example, resistor).Alternatively, current sensing element 120 is connected to dc voltage VDC.Again; The change of the electric current I B that when lacking offset current, causes through exciting of common transmission/receiving node 112, provided by current sensing element 120 is by the offset current IC of compensating circuit 130 compensation or almost compensated, so that current sensor IB is constant or almost constant.By contrast, the electric current that passes through transmission line that is caused by the reception signal that gets into changes not by compensating circuit 130 compensation, and therefore, current sensor IB significantly changes.

Fig. 2 a shows the more detailed example of the notion shown in Fig. 1 a.The structure of device 200 and the similar of Fig. 1 a shown device.In addition, device 200 comprises comparator C and series impedance RS (for example, resistors in series).Comparator C is connected to current sensing element 120 and series impedance RS is passing through between transmission receiving node 112 and the transmission line TL.Series impedance RS can equal the impedance Z of transmission line TL.

In this example, drive circuit D1 is made up of basic drive D 110 and current sense piece ISNS120.Voltage difference significantly not between the output of D 110 and D1 (node DS).D1 according to digital input stream at node DS place formation voltage dV.This signal at DS place is via series impedance RS, node P and the signal that sends through the transmission line TL with characteristic impedance Z.For example, RS equals Z.

IC is the offset current that is also generated in response to the same digital data stream of this of DD place by trsanscondutance amplifier TCA1 (compensating circuit 130).TCA1 can be assumed to be and show as the current source with fully high source impedance.

Under correct scaling, can realize that the output current of D1 (IB) is independent of or almost is independent of the signal that is sent out based on DD.For example, any change of IB can directly be converted into the relevant change of supply current.

ISNS (current sense piece or current sensor) for example generates the directly or indirectly signal SI relevant with IB.In one situation of back, SI for example can represent the supply current of driver D.

Any arrival signal all will appear at node P place and the formation voltage at the RS two ends; Therefore making IB produce electric current changes; This changes signal SI then and can compare with threshold signal Th at the comparator C place then, thereby produces numeric results signal RC (reception data).

In other words, comparator receives data RC based on relatively providing of sensing signal SI and at least one threshold voltage Th.

In addition, comparator can comprise filter in input place of sensing LSI.This filter can be used to cable loss compensator.Comparator also can be implemented as analog to digital converter (ADC).

For example can define offset current IC and sensing signal SI according to following formula:

IC＝-dV/(RS+Z)

SI＝f(IB)

Express with language, for example, sensing signal SI can be the function of current sensor IB.In addition, the offset current voltage change-dV that for example can equal common transmission/receiving node 112 places adds the impedance Z of transmission line divided by series impedance RS or divided by the series impedance of twice.

In addition, Fig. 2 b shows the more detailed example of notion shown in Fig. 1 b.The similar of device 250 is in the structure of Fig. 1 b shown device.In addition, device 250 comprises comparator C and series impedance RS.Comparator C be connected to current sensing element 120 and series impedance RS be disposed in common transmission/receiving node 112 and be connected to current sensing element 120 and the node of compensating circuit 130 between.In other words, current sensing element 120 is connected to common transmission/receiving node 112 with compensating circuit 130 through series impedance RS.

In this example, buffer circuits B1 is made up of basic buffer B and current sense piece ISNS.Between the output of B and the output of B1 (node DS), there is not significantly voltage difference.B1 generates the Low ESR dc voltage according to quiescent imput voltage VDC at node DS place.

TCA2 (sending driver 110) generates the current IS that gets into node P according to digital input stream.TCA2 is assumed to be and shows as the current source with fully high source impedance.The voltage signal that obtains is at the P place, form at the RS two ends, and is via node P and the signal that sends through the transmission line TL with characteristic impedance Z.For example, RS equals Z.

Under correct scaling, can realize that the output current (IB) of B1 is independent of the signal that is sent out based on DD.

ISNS generates the signal SI relevant with IB.For example, this supply current that can directly cross supervision B1 through output current or the turned of sensing B1 takes place, because the change of common B1 also shows as the change of supply current.Any arrival signal all will appear at node P place and form voltage at the RS two ends, therefore make IB produce electric current and change, and this changes signal SI then and can compare with threshold signal Th at the comparator C place then, thereby produce numeric results signal RC.

For example can define ratio and the sensing signal SI of driver current IS and offset current IC according to following equality:

IC/IS＝-Z/(RS+Z)

SI＝f(IB)

Express with language, for example, sensing signal SI can be the function of current sensor IB.In addition, the ratio of offset current IC and driver current IS adds the impedance Z of transmission line divided by series impedance RS like the impedance Z that can equal transmission line.In some cases, series impedance TS equal the impedance Z of transmission line and therefore offset current IC be approximately the half the of driver current IS.These two electric currents and its hope that the degree of closeness (reaching in 10%, 2% or 1%) of ratio has defined the overall performance of this circuit.

Fig. 3 shows the electronic circuit that carries out the circuit transceiver 300 of two-way communication simultaneously according to the expression of the embodiment of the invention through transmission line.The similar of the transceiver shown in the structure of transceiver 300 and Fig. 2 a.

In this example, send driver 110 and comprise transistor Q3 and signal adaptation device 314.Signal adaptation device 314 is connected to the base stage of transistor Q3 and receives transmission data DD in input place.Signal adaptation device 314 realize sending data-signal DD level shift and/or be amplified to transistor Q3 hope the working point.The collector electrode that the emitter of transistor Q3 is connected to common transmission/receiving node 112 and transistor Q3 is connected to current sensing element 120.Current sensor IB flows to current sensor element 120 from common transmission/receiving node 112 through transistor Q3.

Current sensing element 120 comprises sense resistor RC, and this sense resistor RC is connected to the collector electrode of quiescent voltage VDC+ and the transistor Q3 that sends driver 110.The current sensor IB of the sense resistor of flowing through RC forms pressure drop at sense resistor RC two ends.Sensing signal SI is provided at the node place between the collector electrode of sense resistor RC and transistor Q3.The pressure drop at sense resistor RC two ends changes according to the change of current sensor IB, so sensing signal SI also changes.

In this arranged, the transistor Q3 that sends driver 110 comprised high impedance lead-out terminal (for example, collector terminal) that is connected to sense resistor RC and the Low ESR input terminal (for example, emitter terminal) that is connected to common transmission/receiving node 112.Therefore; The little voltage that is caused at common transmissions/receiving node 112 places by the reception signal that gets into changes the huge change that will generate the current sensor IB that passes through sense resistor RC and the huge change of pressure drop, thereby and also generates the huge change of sensing signal SI.In addition, the voltage of base-emitter-voltage changes owing to the represented little emitter side impedance of transistor Q3 is retained as less (usually much smaller than 0.7V).

Compensating circuit 130 comprises two transistor Q1, Q2 and current source cell 332, and current source cell 332 comprises three current source IDC1, IDC2, the IDC3 that links to each other through two resistor R 1, R2, and these expression differential amplifiers are arranged.Sending data DD is provided for the base stage of the first transistor Q1 and sends the anti-phase/complement NDD of data or the base stage of the transistor seconds Q2 that quiescent voltage is provided for compensating circuit 130.The emitter that the collector electrode of the first transistor Q1 is connected to fixed potential (for example, ground connection) and the first transistor Q1 is connected to current source cell 332.In addition, the collector electrode of the transistor seconds Q2 emitter that is connected to common transmission/receiving node 112 and transistor seconds Q2 is connected to current source cell 332.

Alternatively, transmission data DD can be provided for transistor Q2 and anti-phase transmission data NDD or quiescent voltage and be provided for transistor Q1.For this alternative, be sent out the complement that data can be DD (through the transmission data DD of anti-phase) to transmission line.

The first current source IDC1 of current source cell 332 is connected to the emitter of the first transistor Q1 and first resistor R 1 through current source cell 332 is connected to the second current source IDC2.The 3rd current source IDC3 of current source cell 332 is connected to the emitter of transistor seconds Q2 and is connected to the second current source IDC2 of current source cell 332 through second resistor R 2 of current source cell 332.Utilize three different current sources for example can reduce the temperature dependency of circuit transceiver 300.Alternatively, current source cell 332 for example only comprises a current source, so that the complexity of current source cell 332 is lowered.

The transistor seconds Q2 of compensating circuit 130 is to common transmission/receiving node 112 electric current I C that affords redress, and compensate at least in part by this way by transistor Q3 the base stage place and the corresponding voltage of change that sends data DD change the change of the reference current IB that dV causes.

Optional comparator C can be compared sensing signal SI to obtain to receive data RC with at least one instantaneous constant (perhaps sending a plurality of at least different pieces of information values of data DD) threshold voltage VTHdc.

Circuit transceiver 300 is comprising the architecture of part symmetry at least aspect the differential amplifier layout of compensating circuit 130.At least the circuit of part symmetry can make the stray delay effect to offset at least in part.

In addition, illustrate the circuit 390 of transmission line TL far-end, as transmission line TL, circuit 390 is not the part of circuit transceiver 300.

For example, the D1 among Q3 and the RC presentation graphs 2a, wherein RC representes to generate from the source current relevant with IB the ISNS of signal SI.DD itself possibly show certain level shift and amplification before in the base stage that gets into transistor Q3 (wherein voltage change dV is generated).

NDD can be that complement signal or its of DD can be quiescent voltage.

DD/NDD, R1 and R2 and current source can be designed so that the electric current change in the way of going to RS and TL equals electric current change-IC, thereby make IB keep being independent of or almost being independent of digital data stream.

For example can define offset current IC according to following equality:

IC＝-dV/(RS+Z)

Voltage change-the dV that offset current for example can equal common transmission/receiving node 112 places adds the impedance Z of transmission line divided by series impedance RS or divided by the series impedance of twice.In other words; Transmission driver 110 can be designed with compensating circuit 130 or adjusted size is to make offset current equal the series impedance of the voltage change-dV at common transmission/receiving node 112 places divided by twice; Thereby make collector electrode-emitter-voltage of transistor Q3 can keep constant or substantially constant, although dV depends on data and changes.

Fig. 4 shows the electronic circuit that carries out the circuit transceiver 400 of two-way communication simultaneously according to the expression of the embodiment of the invention through transmission line.Circuit transceiver 400 is based on the notion shown in Fig. 2 b.

Send driver 110 and comprise transistor Q2, wherein send data DD, send the base stage that data NDD or quiescent voltage are provided for the transistor Q2 that sends driver 110 through anti-phase.The emitter of the transistor Q2 of transmission driver 110 is connected to the current source cell 332 of compensating circuit 130 and the collector electrode of transistor Q2 is connected to common transmission/receiving node 112.Depend on and send data DD that the transistor Q2 that sends driver 110 inspires the transmission signal at common transmission/receiving node 112 places.

Current sensing element 120 comprises transistor Q3 and sense resistor RC.The emitter of the transistor Q3 of current sensing element 120 is connected to common transmission/receiving node 112 through resistors in series RS, and the collector electrode of transistor Q3 is connected to sense resistor RC.Sense resistor RC is connected to dc voltage VDC+.In addition, constant voltage VDCH+ is provided for the base stage of the transistor Q3 of current sensing element 120.The node place of sensing signal SI between the transistor Q3 of sense resistor RC and current sensing element 120 is provided.In other words, current sensing element 120 uses the supply current IB of the transistor Q3 of current sensing element 120 that sensing signal SI is provided.Transistor as to the transmission driver of Fig. 3 is described, and the transistor Q3 of current sensing element 120 provides the Low ESR input and to sense resistor RC the high impedance input is provided to common transmission/receiving node 112.

Compensating circuit 130 comprises transistor Q1, current source cell 332 and excitation bucking circuit 434.The collector electrode of transistor Q1 is connected to excitation bucking circuit 434, and the emitter of transistor Q1 is connected to current source cell 332.In addition, depend on the kind (DD, NDD, quiescent voltage) of the signal that offers the transistor Q2 that sends driver 110, send data DD, send the base stage that data NDD or quiescent voltage are provided for transistor Q1 through anti-phase.

The transistor Q2 of the transistor Q1 of compensating circuit 130 and transmission driver 110 and current source cell 332 combine and comprise the differential amplifier layout.In addition; The excitation bucking circuit comprises the first resistor R SS and the second actuator RZ; The first resistor R SS be connected to compensating circuit 130 transistor Q1 collector electrode and be connected to emitter and the node between the resistors in series RS of the transistor Q2 of current sensing element 120, the second actuator RZ is connected to the collector electrode of transistor Q1 and is connected to ground.Excitation bucking circuit 434 forms the counterpart with resistor R S and transmission line TL symmetry.By this way, circuit transceiver 400 comprises part symmetrical structure at least, and this can be favourable for offsetting the stray delay effect.

The structure of current source cell 332 is identical with the structure of current source cell shown in Figure 3.Again, current source cell 332 is illustrated as the part of compensating circuit 130.Alternatively, current source cell 332 can be to be connected to compensating circuit 130 and the separate unit that sends driver 110.

For example, the buffer B1 of Q3 and RC presentation graphs 2b, wherein RC representes ISNS, it generates signal SI from the source current relevant with IB.By transistor Q1, Q2, resistor R 1, R2, RSS, RZ and current source IDC1, IDC2, the circuit that IDC3 forms representes to generate from differential input signal DD/NDD TCA1 and the TCA2 of IS and IC.RSS and RZ preferably are chosen as and equal RS and Z, so that IC is constant all the time with (IS*Z/ (RS+Z)) sum.For example, IDC2 or IDC1 and IDC3 are used as current source.

For example can define first resistor R SS of excitation bucking circuit 434 and the second resistor R Z of excitation bucking circuit 434 according to following equality:

RSS＝RS

RZ＝Z

Express with language and to be exactly, the first resistor R SS of excitation bucking circuit 434 equals resistors in series RS, and the second resistor R Z of excitation bucking circuit 434 equals the impedance Z of transmission line.

Fig. 5 shows the alternative implementation according to notion shown in Fig. 2 b of the embodiment of the invention.Circuit transceiver 500 comprises and structure like the circuit transceiver-like shown in Figure 4.Compare with circuit transceiver shown in Figure 4, be separated into two transistor Q1a and Q1b has replaced excitation bucking circuit 434 through transistor Q1 with compensating circuit 130.The collector electrode of the first transistor Q1a of compensating circuit 130 is connected to ground, and the emitter of the first transistor Q1a is connected to current source cell 332.The collector electrode of the transistor seconds Q1b of compensating circuit 130 is connected to the emitter of transistor Q3 and the node between the resistors in series RS, and the emitter of transistor seconds Q1b is connected to current source cell 332.In addition, send data DD, send the base stage of transistor seconds Q1b that data NDD or quiescent voltage are provided for base stage and the compensating circuit 130 of transistor Q1a through anti-phase.

From transistor Q1a and Q1b, compensating circuit 130 can comprise current diverter, and wherein, desirable offset current is confirmed by the ratio of transistor Q1a and Q1b.

In this example, the generation of IC realizes that through transistor Q1 being separated into two transistor Q1a and Q1b wherein these two transistors are designed so that the ratio of collector current is always constant with (IS*Z/ (RS+Z)) sum by IC.

The ratio of the electric current that for example can define the transistor seconds Q1b through compensating circuit 130 according to following equality and the electric current of the first transistor Q1a through compensating circuit 130:

I(Q1b)/I(Q1a)＝Z/RS

Fig. 6 shows the slight deformation of circuit transceiver shown in Figure 5.In this example, the compensating circuit 130 of circuit transceiver 600 comprises delay resistor RM.Postpone resistor RM at the collector electrode of the transistor Q1b of compensating circuit 130 and between like lower node, this node is between the emitter and resistors in series RS of the transistor Q3 of current sensing element 120.

Resistor R M can be chosen as and make the current IS that causes because of parasitic capacitance C1P, C2P at collector electrode place of transistor Q2 and transistor Q1b and the delay of IC be complementary.

The ratio and the resistor R M of the electric current that for example can define the transistor seconds Q1b through compensating circuit 130 according to following equality and the electric current of the first transistor Q1a through compensating circuit 130:

I(Q1b)/I(Q1a)＝Z/RS

RM＝RS*Z/(RS+Z)*C2p/C1p

Alternatively, Fig. 7 shows another implementation from the principle of Fig. 2 b.Circuit transceiver 700 comprises the transmission of fully differential signal.For this, the resistor R C of current sensing element 120 is separated into resistor R Cn and RCp, and transistor Q3 is separated into grounded-base transistor Q3n and Q3p.Current sensing element 120 provides positive and negative sensing signal Sip, Sin to comparator C.Comparator C is based on relatively providing of sensing signal Sip and sensing signal Sin received data RC.In this example, send driver 110 following two transistors: its collector electrode is connected to the transistor Q1a of negative common transmission/receiving node 112n and the transistor Q2a that its collector electrode is connected to common transmission/receiving node 112p.In this example, circuit transceiver 700 comprises two common transmission/receiving node 112n, 112p, a negative part that is connected to transmission line TLn, and another is connected to the positive part of transmission line TLp.In addition; Compensating circuit 130 comprises two transistors; The collector electrode of a transistor Q1b is connected to the emitter of transistor Q3p through just postponing resistor RMp, and the collector electrode of another transistor Q2b postpones the emitter that resistor RMn is connected to transistor Q3n through negative.Transmission driver 110 shown in Figure 7 and transistorized all emitters of compensating circuit 130 all are connected to current source cell 332.

Parasitic capacitance shown in Figure 6 is omitted in Fig. 7, can combine these electric capacity to do same thing although postpone resistor RM.

The negative part of circuit transceiver 700 and positive part comprise resistors in series RSn, RSp between the emitter of the transistor Q3n of current sensing element 120, Q3p and corresponding common transmission/receiving node 112n, 112p.

In this example, current IS, IC, IB, signal SI, T-circuit TL, transistor Q3 and resistor R S, RC, RM by positive part (ISp, ICb, IBp, TLp, Q3p, RSp, RCp, RMp) and negative part (ISN, ICn, IBn, TLn, Q3n, RSn, RCn RMn) forms.

For example can define the ratio of the electric current of the ratio, offset current ICn of resistor R Sn, RSp and RS and offset current ICp and the electric current of transistor Q1a through sending driver 110 and the transistor Q2a through sending driver 110 according to following equality:

RSn＝RSp＝RS

ICp/ISn＝Z/(RS+Z)

ICn/ISp＝Z/(RS+Z)

Fig. 8 shows the block diagram that transmission line carries out the circuit transceiver 800 of two-way communication simultaneously that passes through according to the embodiment of the invention.Transceiver 800 comprises transmission driver 810 and combiner 820.Send driver 810, combiner 820 and transmission line TL and be connected to common transmission/receiving node 812.Transmission line TL is not the part of transceiver 800.

Send driver 810 can through will send jointly/receiving node 812 is pulled to by sending the voltage that data DD confirms and inspires the transmission signal.In addition; Combiner 820 will represent that first signal 814 of the voltage at transmission/receiving node 812 places is combined to obtain sensing signal Cmp with the secondary signal 816 of the driver current IB that representes to be provided by transmission driver 810 jointly; So that compare, get into the more about-face that the reception signal of transmission/receiving node 812 jointly will cause sensing signal Cmp with the transmission signal that sends the same signal intensity that driver 810 inspired.

Transmission effect of signals by transmission driver 810 inspires can be by secondary signal 816 compensation or the almost compensation of expression driver current IB.

For example, compare, can comprise adverse effect sensing signal Cmp by the change of the voltage that sends common transmission/receiving node 812 places that driver 810 causes with the change of the secondary signal that causes by the change of sending the driver current IB that driver 810 provides.In other words; Can compensate through the influence of secondary signal 816 that the drive current IB of driver 810 is sent in expression or almost the voltage at common transmissions/receiving node 812 places of compensation change influence to sensing signal Cmp so that sensing signal Cmp maintenance is constant or almost constant.

Fig. 9 shows and carries out the block diagram of the circuit transceiver 900 of two-way communication simultaneously according to the embodiment of the invention through transmission line based on principle shown in Figure 8.The similar of the structure of transceiver 900 and transceiver shown in Figure 8.In addition, also illustrate the comparator C that is connected to combiner 820 and be disposed in the resistors in series RS between common transmission/receiving node 812 and the transmission line TL.Sending driver 810 comes drawing to send jointly/voltage at receiving node 812 places and corresponding driver current IB is provided according to sending data DD.Combiner 820 for example can generate the secondary signal 816 that is inversely proportional to driver current IB via compensating circuit 924.In addition, combiner 820 can comprise the adder 922 that is configured to generate sensing signal Cmp.

Combiner 820 can provide this sensing signal Cmp to comparator C.Comparator C can for example be compared sensing signal Cmp to obtain to receive data RC with at least one constant threshold voltage Th.

Compensating circuit 924 can be to send the part of driver 810 or the part of combiner 820, and is indicated like the dotted line among Fig. 9.Alternatively, compensating circuit 924 can be a hardware cell independently.

In this example, the sensing of electric current I B or IS is carried out to making SI have and being sent out signal antipole property.Then, SI can eliminate the signal that is sent out from comparator signal Cmp basically with the simple addition (active or passive) that is sent out signal DS.

Figure 10 shows according to the expression of the embodiment of the invention electronic circuit based on the circuit transceiver 1000 of principle shown in Figure 9.In this example, send driver 810 and comprise a pair of complementary output transistor Q1, Q2.The emitter of these two transistor Q1, Q2 is connected to common transmission/receiving node 812.Combiner 820 comprises the voltage divider that utilizes two resistor R 1, R2 to form.First resistor R 1 is connected to the common transmission/receiving node 812 and second resistor R 2.Second resistor R 2 is connected to first resistor R 1 and ground.The extraction point (tab) of combiner 820 between first resistor R 1 and second resistor R 2 locates to be provided for the sensing signal Cmp of comparator C.Comprise two complementary portions owing to send driver 810, so compensating circuit also comprises two complementary portion 924a, 924b.The first of compensating circuit 924a comprises the first current source IC1 and first current diverter that has transistor Q3.Current source IC1 is connected to the collector electrode of the transistor Q1 that sends driver 810 and is connected to the transistorized emitter of current diverter.First current diverter comprises the first transistor Q3 and another transistor, and the collector electrode of the first transistor Q3 is connected to the extraction point of the voltage divider of combiner 820, and another transistorized collector electrode is connected to ground.The transistorized base stage of first current diverter is setovered by the bias voltage VB1 that is used to regulate transistorized working point.The ratio of current diverter is m/n.

Be similar to the first of compensating circuit 924a, the second portion of compensating circuit 924b comprises the second current source IC2 and second current diverter that has transistor Q4.The second current source IC2 is connected to the collector electrode of the transistor Q2 that sends driver 810 and is connected to the transistorized emitter of second current diverter.This current diverter comprises two transistors, and extraction point and another transistorized collector electrode that the collector electrode of a transistor Q4 is connected to the voltage divider of combiner 820 are connected to ground.The transistor of this current diverter is setovered by the bias voltage VB2 of the transistorized working point that is used to regulate this current diverter.

The transistor Q1 of transmission driver 810, the base stage of Q2 can be driven by two equal signals based on the transmission data, and the only separated game clock of these two equal signals is shown the dc voltage (direct voltage) of two diode drops.

Comprise two complementary portions owing to send driver 810 with compensating

circuit

924a, 924b, so driver current IB1, IB2 and

secondary signal

816a, 816b also comprise two parts.Two parts of

secondary signal

816a, 816b directly are provided for the extraction point of the voltage divider of combiner 820.Alternatively, the extraction point that two of

secondary signal

816a, 816b parts can be combined and this composite signal is provided for voltage divider then.

For example, inspire the transmission signal if send driver 810 at common transmission/receiving node 812 places, then the voltage at transmission/receiving node place is pulled to higher or lower voltage jointly.For example, if the voltage at common transmissions/receiving node 812 places is increased, then the driver current IB1 of the transistor Q1 through transmission driver 810 is also increased.Otherwise the driver current IB2 of the transistor Q2 through sending driver 810 is reduced.Therefore, the first current sensor SC1 is lowered and the second current sensor SC2 is raised, so that the first current sensor SC1 and the second current sensor SC2 comprise the anti-phase behavior of being compared with driver current.Two current sensor SC1, SC2 are separated by current diverter; So that the first of secondary signal 816 is provided by the transistor Q3 of first current diverter with regard to the first offset current CC1; And the second portion of secondary signal 816b is provided by the transistor Q4 of second current diverter with regard to the second offset current CC2; Wherein, The part that the first of secondary signal 816a provides the ratio by the transistor of current diverter among the current sensor SC1 of reduction to confirm, and the second portion of the secondary signal 816b part that provides the ratio among the current sensor SC2 of increase to confirm by second current diverter.Because the first current sensor SC1 reduces and the second current sensor SC2 increases, therefore with the first of secondary signal 816a and the combined extraction point that will offer the offset current that obtains the voltage divider of combiner 820 of second portion of secondary signal 816b.To compare this offset current that obtains with first signal 814 and comprise adverse effect sensing signal Cmp, it will send jointly/and the voltage of the increase at receiving node 812 places offers the extraction point of this voltage divider through first resistor R 1 of the voltage divider of combiner 820.

In other words, offset current has compensated or has almost compensated the influence of the voltage of common transmission/receiving node 812 places increase to sensing signal Cmp.With send driver 810 inspire send signal during jointly the big voltage at transmissions/receiving node 812 places change and compare, if the reception signal that gets into is received, then only change slightly of the voltage at transmission/receiving node 812 places jointly.Yet driver current IB1, IB2 significantly change, and for the reception signal that gets into the Low ESR input are provided at common transmission/receiving node 812 places because send driver 810.Therefore, the behavior of first and second parts of driver current IB1, IB2, current sensor SC1, SC2 and

secondary signal

816a, 816b is similar to the behavior of describing when driver 810 excites the transmission signal of sending.Therefore, secondary signal 816 causes that at sensing signal Cmp place voltage changes.In other words, the about-face of the reception signal of entering and

secondary signal

816a, 816b combines the slight change that only causes first signal 814, so that the voltage pole the earth of sensing signal Cmp changes.

In this example, Q1 and Q2 are the common complementary output transistors of voltage driver.Its base stage is shown that by separated game clock only two equal signals of the dc voltage of two diode drops drive.The emitter of these transistorized collector electrodes and transistor Q3, Q4 is connected to current source IC1 and IC2.These transistors are also as current diverter work, and wherein the m/ of spill current (m+n) is routed to summing junction Cmp.Because this has the reverse voltage effect of driven signal DS (transmission signal), therefore, resistor R 1 drive signal at Cmp place is offset or is almost offset in the passive addition meeting of DS when suitably being selected via R1.Also change the driver output current and appear at the Cmp place and be not cancelled from any arrival signal of TL.This arrival signal from P to Cmp has the voltage gain of for example being confirmed by resistor R 2.

For example can define first resistor R 1 and second resistor R 2 of voltage divider of gain, the combiner 820 of receiver through following equality:

RcvGain＝RG＝Cmp/Pin

R1＝2*RS*n/m

RS＝2*RS*(1+n/m)*RG*(2-RG)

Change size that receiver gain RcvGain, RG can be defined as the sensing signal Cmp that is caused by the reception signal that gets into and the corresponding ratio of importing the voltage change size that (P) (for example input pin of ATE) locate.

Figure 11 shows the circuit transceiver 1100 of two-way communication is simultaneously carried out in expression according to the present invention through transmission line electronic circuit.The similar of circuit transceiver 1100 is in the structure of circuit transceiver shown in Figure 10.Only the current diverter of compensating circuit is implemented in sending driver 810, and the resistor R 2 of the voltage divider of combiner 820 is connected to the buffer of variable dc voltage VT B is provided.Therefore, send driver 810 and comprise a pair of complementary current shunt.Transistorized all emitters of current diverter all are connected to common transmission/receiving node 812.The collector electrode of a transistor Q1 of first current diverter is connected to the first current source IC1 of the first of compensating circuit 924a.In addition, the collector electrode of second current diverter transistor Q2 is connected to the second current source IC2 of the second portion of compensating circuit 924b.

Circuit transceiver 1100 is based on coming work with the same principle of describing to Figure 10.Because slightly different structure; The first current sensor SC1 of circuit transceiver 1100 and the first offset current CC1 equate (base current of ignoring transistor Q3), and the second current sensor SC2 and the second offset current CC2 equal (base current of ignoring transistor Q4).

In other words, transistor Q1 and Q2 are used as current diverter, and wherein the m/ of spill current (m+n) is routed to summing junction Cmp via simple cascade Q3, Q4.In addition, R2 is connected to the buffer that variable dc voltage is provided.This can be useful for optimizing entire circuit.

For example can define first resistor R 1 and second resistor R 2 of the voltage divider of gain Rev, combiner 820 according to following equality:

RcvGain＝RG＝Cmp/Pin

R1＝2*RS*n/m

RS＝2*RS*(1+n/m)*RG*(2-RG)

Figure 12 shows the flow chart that is used for carrying out through transmission line the method 1200 of two-way communication simultaneously according to the embodiment of the invention.Method 1200 comprises according to current sensor provides 1210 sensing signals, and generates 1220 offset currents according to sending data.To comprise adverse effect at transmission signal and the offset current that common transmission/receiving node place excites according to sending data to current sensor; So that compare with the transmission signal of same signal intensity, the reception signal that gets into this common transmission/receiving node will cause the more about-face of current sensor.

Figure 13 shows the flow chart that is used for carrying out through transmission line the method 1300 of two-way communication simultaneously according to the embodiment of the invention.Method 1300 comprises first signal of the voltage at the common transmissions/receiving node place of expression and expression by the secondary signal combined 1310 of sending the driver current that driver provides with the acquisition sensing signal; So that compare with the transmission signal of the same signal intensity that excites by the transmission driver; The reception signal that gets into this common transmission/receiving node will cause the more about-face of current sensor; Wherein, send signal be through will send jointly/receiving node is pulled to by sending the voltage that data confirm and is excited.

Relate to the method for bi-directional data link simultaneously according to some embodiments of the present invention.

In other words, some embodiment relate to electronics two-way signaling transmission circuit, and the supply current that wherein sends driver is used to generate the signal that will compare.This for example also can realize through differential signal.In addition, can add filter, for example be used for cable loss compensator in input place of comparator.According on the other hand, the symmetric circuit that for example is used to offset the stray delay effect can be used.In certain embodiments, trsanscondutance amplifier (TCA) current switch and/or the cascade that can be implemented as on linear amplifier or the collector electrode can be used to the electric current shunting.Alternatively, multiplier can be used as current diverter, for example is used for regulating or the calibrating resistor mismatch.

For example, the inner information of supply current of proposed invention utilization transmission driver is carried out separating signal transmitted and received signal.

Though above-mentioned all embodiment use bipolar transistor, obviously, bipolar transistor can be replaced by field-effect transistor.The transistor that can also replace in addition, the circuit transceiver with complementary transistor.For example, PNP transistor or field-effect transistor can be used to replace NPN transistor.In other words, the PNP transistor can be replaced by NPN transistor, and vice versa, and same, p type field effect transistor can be replaced by n type field effect transistor, and vice versa.

Relate to automatic testing equipment (ATE) according to some embodiments of the present invention, this automatic testing equipment comprises above-mentioned circuit transceiver.For example, the ATE pin electronic can realize with the method.

With the current sensor that relates to by relevant term " by compensate ", " almost by compensation ", " constant ", " almost constant ", " counteractings ", " almost offsetting ", " being independent of " and " almost being independent of " of change of sending current sensor that signal causes or sensing signal and cause by the reception signal of entering or the comparison of sensing signal.In other words, the change that is caused by the transmission signal is compared and can be left in the basket with the change that is caused by the reception signal that gets into.

Though in the context of device, described aspect some, with clear, the description to corresponding method is also represented in these aspects, wherein piece or equipment are corresponding to the characteristic of method step or method step.Similarly, the each side of in the context of method step, describing is also represented the description to the corresponding blocks of corresponding intrument or project or characteristic.

Claims

1. circuit transceiver (100 that is used for carrying out two-way communication simultaneously through transmission line; 150; 200; 250; 300; 400; 500; 600; 700), said circuit transceiver (100) comprising:

Send driver (110), be configured to locate to excite the transmission signal at common transmission/receiving node (112) according to sending data (DD);

Current sensing element (120), being configured to provides sensing signal (SI) according to current sensor (IB); And

Compensating circuit (130); Be configured to generate offset current (IC) according to said transmission data (DD); Wherein, Said transmission driver (110) and said compensating circuit (130) are configured to comprise the adverse effect to said current sensor (IB), so that compare with the transmission signal of the same signal intensity that is excited by said transmission driver (110), will cause the more about-face of said current sensor (IB) at the reception signal of said common transmission/receiving node (112) generation.

2. said circuit transceiver (300; 400; 500; 600; 700); Wherein, said current sensing element (120) comprises sense resistor (RC), and this sense resistor (RC) changes then causes that the voltage of said sensing signal (SI) changes if be configured to said current sensor (IB); Wherein, said current sensor (IB) the said sense resistor (RC) of flowing through.

3. circuit transceiver (300 according to claim 2; 400; 500; 600; 700); Wherein, Said current sensing element (120) or said transmission driver (110) comprise transistor (Q3), and said transistor (Q3) has high impedance terminal that is connected to said sense resistor (RC) and the Low ESR terminal that is connected to said common transmission/receiving node (112).

4. according to one in the claim 1 to 3 described circuit transceiver (200; 250), wherein, said compensating circuit (130) comprises the trsanscondutance amplifier (TCA1) that is configured to generate said offset current (IC).

5. according to one in the claim 1 to 4 described circuit transceiver (300), wherein, said compensating circuit (130) comprises the differential amplifier layout, and being configured to provides said offset current (IC) through the transistor that said differential amplifier is arranged.

6. according to one in the claim 1 to 4 described circuit transceiver (400; 500; 600; 700); Wherein, The combined differential amplifier that comprises of said compensating circuit (130) and said transmission driver (110) arranges, the transistor that this differential amplifier is arranged the transistor that comprises the said compensating circuit (130) that is configured to generate said offset current (IC) and is configured to locate to excite at said common transmission/receiving node (112) the said transmission driver (110) that sends signal.

7. according to one in the claim 1 to 6 described circuit transceiver (500; 600; 700), wherein, said compensating circuit (130) comprise the current diverter that is configured to provide said offset current (IC) (Q1a, Q1b).

8. according to one in the claim 1 to 7 described circuit transceiver (600; 700); Wherein, said compensating circuit (130) comprises and postpones resistor (RM), is configured to mate said offset current (IC) and will be in the delay between the transmission signal that said common transmission/receiving node (112) is located to excite; Wherein, said offset current (IC) the said delay resistor RM that flows through.

9. according to one in the claim 1 to 8 described circuit transceiver (700), wherein, said circuit transceiver is arranged to differential signal and handles.

10. according to one in the claim 1 to 9 described circuit transceiver (100; 200; 300); Comprise the series impedance (RS) between the transmission line that is positioned at said common transmission/receiving node (112) and will be connected to said circuit transceiver; Wherein, said offset current (IC) equals to be changed (dV) divided by impedance (Z) sum of said series impedance (RS) with said transmission line by the voltage of locating at said common transmission/receiving node (112) that the transmission signal that said transmission driver (110) is excited causes.

11. according to one in the claim 1 to 10 described circuit transceiver (150; 250; 400; 500; 600; 700); Wherein, The half the of the value of the value of said offset current (IC) and the driver current (IS) that is provided by said transmission driver (110) equate, and the difference of half of the value of the value of perhaps said offset current (IC) and the driver current (IS) that is provided by said transmission driver (110) is less than 10% of the value of the driver current (IS) that is provided by said transmission driver (110).

12., also comprise according to one in the claim 1 to 11 described circuit transceiver (300):

Be positioned at the resistors in series (RS) between said common transmission/receiving node (112) and the input terminal, be configured to be connected to transmission line TL; And

Comparator (C) is configured to receive data (RC) based on said sensing signal (SI) that is provided by said current sensing element (120) and relatively providing of threshold voltage (VTHdc),

Wherein, Said transmission driver (110) comprises transistor (Q3) and signal adaptation device (314); Wherein, The collector electrode that the emitter of the transistor (Q3) of said transmission driver (110) is connected to the transistor (Q3) of said common transmission/receiving node (112) and said transmission driver (110) is connected to said current sensing element (120); Wherein, said signal adaptation device (314) is configured to adaptive said transmission data (DD) and will offers the base stage of the transistor (Q3) of said transmission driver (110) through adaptive transmission data-signal (dV)

Wherein, Said current sensing element (120) comprises transistor (Q3) that is connected to said transmission driver (110) and the sense resistor (RC) that is connected to constant voltage (VDC+); Wherein, The node place that said current sensing element (120) is configured between the transistor (Q3) of said sense resistor (RC) and said transmission driver (110) provides said sensing signal (SI)

Wherein, Said compensating circuit (130) comprises the first transistor (Q1), transistor seconds (Q2) and current source cell (332); Wherein, The emitter of the grounded collector of the said the first transistor (Q1) of said compensating circuit (130) and the said the first transistor (Q1) of said compensating circuit (130) is connected to said current source cell (332); Wherein, The emitter that the collector electrode of the said transistor seconds (Q2) of said compensating circuit (130) is connected to the said transistor seconds (Q2) of said common transmission/receiving node (112) and said compensating circuit (130) is connected to said current source cell (332); The base stage of the base stage of the said the first transistor (Q1) that wherein, is provided for said compensating circuit (130) and the said transistor seconds (Q2) of said compensating circuit (130) based on the signal of said transmission data (DD), through the transmission data (NDD) or the stationary singnal of anti-phase.

13., also comprise according to one in the claim 1 to 11 described circuit transceiver (400):

Be positioned at the resistors in series (RS) between said common transmission/receiving node (112) and the said current sensing element (120); And

Wherein, Said transmission driver (110) comprises transistor (Q2); Wherein, The emitter that the collector electrode of the transistor (Q2) of said transmission driver (110) is connected to the transistor (Q2) of said common transmission/receiving node (112) and said transmission driver (110) is connected to said compensating circuit (130)

Wherein, Said current sensing element (120) comprises sense resistor (RC) and transistor (Q3); Wherein, said sense resistor (RC) is connected to the transistor (Q3) of said current sensing element (120) and is connected to constant voltage (VDC+), wherein; The emitter that the collector electrode of the transistor (Q3) of said current sensing element (120) is connected to said sense resistor (RC) and said transistor (Q3) is connected to said common transmission/receiving node (112) through said resistor (RS); Wherein, constant voltage (VDCH+) is provided for the base stage of the transistor (Q3) of said current sensing element (120)

Wherein, Said compensating circuit (130) comprises transistor (Q1), excitation bucking circuit (434) and current source cell (332); Wherein, The emitter that the collector electrode of the transistor (Q1) of said compensating circuit (130) is connected to the transistor (Q1) of said excitation bucking circuit (434) and said compensating circuit (130) is connected to said current source cell (332); Wherein, the base stage of the transistor (Q2) of said transmission data (DD), the transistor (Q1) that is provided for said compensating circuit (130) through the transmission data (NDD) or the stationary singnal of anti-phase and said transmission driver (110)

Wherein, Said excitation bucking circuit (434) comprises first resistor (RSS) and second resistor (RZ); Said first resistor (RSS) is connected to the transistor (Q1) of said compensating circuit (130) and is connected to the transistor (Q3) of said current sensing element (120) and the node between the said resistors in series (RS), and said second resistor (RZ) is connected to the node between first resistor (RSS) of the transistor (Q1) that is positioned at said compensating circuit (130) and said excitation bucking circuit (434) and is connected to ground.

14., also comprise according to one in the claim 1 to 11 described circuit transceiver (500):

Wherein, Said current sensing element (120) comprises sense resistor (RC) and transistor (Q3); Wherein, said sense resistor (RC) is connected to the transistor (Q3) of said current sensing element (120) and is connected to constant voltage (VDC+), wherein; The emitter that the collector electrode of the transistor (Q3) of said current sensing element (120) is connected to said sense resistor (RC) and transistor (Q3) is connected to said common transmission/receiving node (112) through said resistor (RS); Wherein, constant voltage (VDCH+) is provided for the base stage of the transistor (Q3) of said current sensing element (120)

Wherein, Said compensating circuit (130) comprises current source cell (332) and current diverter; This current diverter comprises the first transistor (Q1a) and transistor seconds (Q1b); Wherein, the collector electrode of the first transistor of said current diverter (Q1a) is connected to ground, and wherein; The emitter of the first transistor of said current diverter (Q1a) is connected to said current source cell (332); Wherein, the collector electrode of the transistor seconds of said current diverter (Q1b) be connected to the transistor (Q3) that is positioned at said current sensing element (120) and the node between the said resistors in series (RS) and, the emitter of the transistor seconds of said current diverter (Q1b) is connected to said current source cell (332); Wherein, said transmission data (DD), the first transistor (Q1a), the transistor seconds (Q1b) of said current diverter and the transistor (Q2) of said transmission driver (110) that are provided for said current diverter through the transmission data (NDD) or the stationary singnal of anti-phase.

15. circuit transceiver according to claim 14 (600); Comprise postponing resistor (RM), this delay resistor (RM) is connected to collector electrode and the transistor (Q2) of said current sensing element (120) and the node between the said resistors in series (RS) of the transistor seconds (Q1b) of said compensating circuit (130).

16. according to one in the claim 1 to 11 described circuit transceiver (700); Being arranged to differential signal handles; Wherein, Said transmission driver (110) is configured to locate to inspire the transmission signal according to sending data (DD) at negative common transmission/receiving node (112n) and positive common transmission/receiving node (112p); Wherein, Said current sensing element (120) is configured to negative sensing signal (Sin) is provided and according to positive current sensor (IBp) positive sensing signal (Sip) is provided according to negative current sensor (IBn); Wherein, said compensating circuit (130) is configured to generate negative offset current (ICn) and positive offset current (ICp) according to said transmission data (DD), wherein; Said transmission driver (110) and said compensating circuit (130) are configured to comprise the adverse effect to said negative current sensor (IBn) and said positive current sensor (IBp); So that compare with the transmission signal of the same signal intensity that is excited by said transmission driver (110), the reception signal of locating to take place at said negative common transmission/receiving node (112n) and said positive common transmission/receiving node (112p) will cause the more about-face of said negative current sensor (IBn) and said positive current sensor (IBp), and said circuit transceiver (700) also comprises:

First resistors in series (RSn) is connected to said negative common transmission/receiving node (112n) and is connected to said current sensing element (120);

Second resistors in series (RSp) is connected to said positive common transmission/receiving node (112p) and is connected to said current sensing element (120); And

Comparator (C) is configured to receive data (RC) based on said negative sensing signal (Sin) and relatively providing of said positive sensing signal (Sip),

Wherein, Said transmission driver (110) comprises the first transistor (Q1a) and transistor seconds (Q2a); Wherein, The emitter that the collector electrode of the first transistor (Q1a) of said transmission driver (110) is connected to the first transistor (Q1a) of said negative common transmission/receiving node (112n) and said transmission driver (110) is connected to said compensating circuit (130); Wherein, the collector electrode of the transistor seconds (Q2a) of said transmission driver (110) emitter that is connected to the transistor seconds (Q2a) of said positive common transmission/receiving node (112p) and said transmission driver (110) is connected to said compensating circuit (130)

Wherein, Said current sensing element (120) comprises the first transistor (Q3n), transistor seconds (Q3p), first sense resistor (RCn) and second sense resistor (RCp); Wherein, The emitter of the first transistor (Q3n) that the collector electrode of the first transistor (Q3n) of said current sensing element (120) is connected to first sense resistor (RCn) and the said current sensing element (120) of said current sensing element (120) is connected to said negative common transmission/receiving node (112n) through said first resistors in series (RSn); Wherein, First sense resistor (RCn) of said current sensing element (120) is connected to the first transistor (Q3n) of said current sensing element (120) and is connected to constant voltage (VDC+); Wherein, Second sense resistor (RCp) of emitter through said circuit transceiver (700) of transistor seconds (Q3p) that the collector electrode of the transistor seconds (Q3p) of said current sensing element (120) is connected to second sense resistor (RCp) and the said current sensing element (120) of said current sensing element (120) is connected to said positive common transmission/receiving node (112p); Wherein, Second sense resistor (RCp) of said current sensing element (120) be connected to said current sensing element (120) transistor seconds (Q3p) collector electrode and be connected to constant voltage (VDC+); Wherein, the node place of said negative sensing signal (Sin) between the first transistor (Q3n) of first sense resistor (RCn) of said current sensing element (120) and said current sensing element (120) is provided, wherein; The node place of said positive sensing signal (Sip) between the transistor seconds (Q3p) of second sense resistor (RCp) of said current sensing element (120) and said current sensing element (120) is provided

Wherein, Said compensating circuit (130) comprises that the first transistor (Q1b), transistor seconds (Q2b), first postpone resistor (RMp), second and postpone resistor (RMn) and current source cell (332); Wherein, The collector electrode of the first transistor (Q1b) of said compensating circuit (130) postpones resistor (RMp) through said first and is connected to the transistor seconds (Q3p) of said current sensing element (120) and the node between said second resistors in series (RSp); And the emitter of the first transistor (Q1b) of said compensating circuit (130) is connected to said current source cell (332); Wherein, The collector electrode of the transistor seconds (Q2b) of said compensating circuit (130) postpones resistor (RMn) through second of said compensating circuit (130) and is connected to the first transistor (Q3n) of said current sensing element (120) and the node between said first resistors in series (RSn), and the emitter of the transistor seconds (Q2b) of said compensating circuit (130) is connected to said current source cell (332).

17. circuit transceiver (800 that is used for carrying out two-way communication simultaneously through transmission line; 900; 1000; 1100), said circuit transceiver (800) comprising:

Send driver (810), be configured to through will send jointly/receiving node (812) is pulled to by sending the definite voltage of data (DD) and inspires the transmission signal; And

Combiner (820); First signal (814) that is configured to be illustrated in the voltage that said common transmission/receiving node (812) locates and expression are combined to obtain sensing signal (CMP) by the secondary signal (816) of the driver current (IB) that said transmission driver (810) provides; So that compare with the transmission signal of the same signal intensity that is inspired by said transmission driver (810), the reception signal of locating to take place at said common transmission/receiving node (812) will cause the more about-face of said sensing signal (CMP).

18. circuit transceiver (800 according to claim 17; 900; 1000; 1100); Wherein, Said combiner (820) is configured to make: the change that changes said driver current (IB) caused, that provided by said transmission driver (810) with the voltage located by said common transmission/receiving node (812) is compared, and the voltage of locating at said common transmission/receiving node (812) that is caused by said transmission driver (810) changes and comprises the adverse effect to said sensing signal (CMP).

19. according to claim 17 or 18 described circuit transceivers (1000; 1100); Wherein, Said combiner (820) comprises the voltage divider with the input that is connected to said common transmission/receiving node (812); Wherein, said voltage divider is configured at the extraction point place said first signal (814) and said secondary signal (816) made up, and wherein said voltage divider is configured at said extraction point place said sensing signal (CMP) is provided.

20. circuit transceiver (1000 according to claim 18; 1100), wherein, second input of said voltage divider is connected to the included voltage source of said combiner (820), and wherein, said voltage source is configured to said voltage divider variable DC voltage is provided.

21. according to one in the claim 17 to 20 described circuit transceiver (1000; 1100), wherein, said transmission driver (810) comprises the complementary voltage driver, and this complementary voltage driver comprises at least one pair of complementary transistor, and wherein, said common transmission/receiving node (812) is between this is to complementary transistor.

22. circuit transceiver (1000 according to claim 21; 1100); Wherein, Said secondary signal (816) comprises the first of offset current and the second portion of offset current; Wherein, the first of said offset current representes by this an electric current that transistor provides in the complementary transistor, and the second portion of said offset current is represented the electric current that another transistor in the complementary transistor provided by this.

23. according to one in the claim 17 to 22 described circuit transceiver (1000; 1100); Comprise the compensating circuit (924) that is connected to said transmission driver (110) and said combiner (820) and comprise the current source that is configured to provide the constant source electric current; If the electric current of said secondary signal (816) is increased so that said driver current is reduced, and if make that said driver current is increased then the electric current of said secondary signal (816) is reduced.

24. according to one in the claim 17 to 23 described circuit transceiver (1000), said circuit transceiver also comprises:

Resistors in series (RS) is connected to said common transmission/receiving node (812) and is connected to the transmission line that is connected to said circuit transceiver (1000); And

Comparator (C) is configured to receive data (RC) based on said sensing signal (CMP) and relatively providing of threshold voltage (Th), and wherein, said combiner (820) is configured to provide said sensing signal (CMP),

Wherein, said transmission driver (810) comprise a pair of complementary transistor (Q1, Q2); Wherein, the emitter of these two complementary transistors is connected to said common transmission/receiving node (812), wherein; This collector electrode to the first transistor in the complementary transistor (Q1) is connected to the first of compensating circuit (924a); Wherein, this collector electrode to the transistor seconds in the complementary transistor (Q2) is connected to the second portion of compensating circuit (924b), wherein; First drive signal is provided for the base stage of the first transistor (Q1) of said transmission driver (810) based on said transmission data; Wherein, be provided for the base stage of the transistor seconds (Q2) of said transmission driver (810) based on second drive signal of said transmission data, wherein; Be provided for the base stage of a plurality of the first transistors of said transmission driver (810) based on first drive signal of said transmission data; Wherein, be provided for the base stage of a plurality of transistor secondses of said transmission driver (810) based on second drive signal of said transmission data

Wherein, Said combiner (820) comprises the voltage divider that comprises first resistor (R1) and second resistor (R2); Wherein, first resistor of said voltage divider is connected to said common transmission/receiving node (812) and said second resistor, wherein; Second resistor (R2) of said voltage divider is connected to said first resistor (R1) and ground connection

Wherein, The first of said compensating circuit (924a) comprises first current source (IC1) and comprises the first transistor and first current diverter of transistor seconds (Q3); Wherein, Said first current source (IC1) be connected to said transmission driver (810) the first transistor (Q1) collector electrode and be connected to said first current diverter; Wherein, the emitter of the first transistor of said first current diverter is connected to the node between the first transistor (Q1) of said first current source (IC1) and said transmission driver (810), wherein; The collector electrode of the first transistor of said first current diverter is connected to ground; Wherein, the emitter of the transistor seconds of said first current diverter (Q3) is connected to the node between the first transistor (Q1) of said first current source (IC1) and said transmission driver (810), wherein; The collector electrode of the transistor seconds of said first current diverter (Q3) is connected to first resistor (R1) that is positioned at said voltage divider of said voltage divider and the extraction point between second resistor (R2)

Wherein, The second portion of said compensating circuit (924b) comprises second current source (IC2) and comprises the first transistor and second current diverter of transistor seconds (Q4); Wherein, Said second current source (IC2) be connected to said transmission driver (810) transistor seconds (Q2) collector electrode and be connected to said second current diverter, wherein, the emitter of the first transistor of said second current diverter is connected to the node between the transistor seconds (Q2) of said second current source (IC2) and said transmission driver (810); Wherein, The collector electrode of the first transistor of said second current diverter is connected to ground, and wherein, the emitter of the transistor seconds of said second current diverter (Q4) is connected to the node between the transistor seconds (Q2) of said second current source (IC2) and said transmission driver (810); Wherein, The collector electrode of the transistor seconds of said second current diverter (Q4) is connected to the said extraction point of said voltage divider, and wherein, first bias voltage (VB1) is provided for a plurality of transistorized base stage of said first current diverter; Wherein, second bias voltage (VB2) is provided for a plurality of transistorized base stage of said second current diverter.

25., also comprise according to one in the claim 17 to 23 described circuit transceiver (1100):

Resistors in series (RS) is connected to said common transmission/receiving node (812) and is connected to the transmission line that is connected to said circuit transceiver (1000);

Comparator (C) is configured to receive data (RC) based on said sensing signal (CMP) and relatively providing of threshold voltage (Th), and wherein, said combiner (820) is configured to provide said sensing signal (CMP); And

Buffer B is used for to said combiner (820) constant voltage VT being provided,

Wherein, said transmission driver (810) comprises a pair of complementary current shunt, wherein; This comprises the first transistor and transistor seconds (Q1) to first current diverter in the complementary current shunt, and wherein, this comprises the first transistor and transistor seconds (Q2) to second current diverter in the complementary current shunt; Wherein, this is connected to said common transmission/receiving node (812) to transistorized all emitters in the complementary current shunt, wherein; The collector electrode of the transistor seconds of said first current diverter (Q1) is connected to the first of compensating circuit (924a); Wherein, the collector electrode of the transistor seconds of said second current diverter (Q2) is connected to the second portion of compensating circuit (924b), wherein; Be provided for the transistorized base stage of said first current diverter based on first drive signal of said transmission data; Wherein, be provided for the transistorized base stage of said second current diverter based on second drive signal of said transmission data

Wherein, The first of said compensating circuit (924a) comprises first current source (IC1) and transistor (Q3); Wherein, said first current source (IC1) be connected to said transmission driver (810) first current diverter transistor seconds (Q1) collector electrode and be connected to the emitter of transistor (Q3) of the first of said compensating circuit (924a), wherein; The collector electrode of the transistor (Q3) of the first of said compensating circuit (924a) is connected to the said extraction point of the voltage divider of said combiner (820); Wherein, first bias voltage is provided for the base stage of transistor (Q3) of the first of said compensating circuit (924a)

Wherein, The second portion of said compensating circuit (924b) comprises second current source (IC2) and transistor (Q4); Wherein, Said second current source (IC2) be connected to said transmission driver (810) second current diverter transistor seconds (Q2) collector electrode and be connected to the emitter of transistor (Q4) of the second portion of said compensating circuit (924b), wherein, the collector electrode of the transistor (Q4) of the second portion of said compensating circuit (924b) is connected to the said extraction point of the voltage divider of said combiner (820); Wherein, second bias voltage is provided for the base stage of transistor (Q4) of the second portion of said compensating circuit (924b).

26. according to one in claim 1 to 9 or 17 to 20 described circuit transceiver, comprise comparator, this comparator is configured to receive data (RC) based on relatively providing of sensing signal and threshold signal.

27. circuit transceiver according to claim 26, wherein, said comparator comprises the filter of input place that is positioned at said sensing signal.

28. according to one in the claim 1 to 9,17 to 23 or 26 to 27 described circuit transceiver, wherein, said circuit transceiver comprises part symmetrical structure at least.

29. one kind comprises the automatic testing equipment according to a described circuit transceiver in the claim 1 to 28.

30. a method (1200) that is used for carrying out through transmission line two-way communication simultaneously, this method comprises:

According to current sensor (1210) sensing signal is provided; And

Generate (1220) offset current according to sending data; Wherein, Comprise adverse effect according to sending data at transmission signal and the said offset current that common transmission/receiving node place excites to said current sensor; So that compare with the transmission signal of the same signal intensity that is excited by the transmission driver, the reception signal that takes place at said common transmission/receiving node place will cause the more about-face of said current sensor.

31. a method (1300) that is used for carrying out through transmission line two-way communication simultaneously, this method comprises:

With first signal of the voltage at the common transmissions/receiving node place of expression and expression by the secondary signal combined (1210) of sending the driver current that driver provides with the acquisition sensing signal; So that compare with the transmission signal of the same signal intensity that inspires by said transmission driver; The reception signal that takes place at said common transmission/receiving node place will cause the more about-face of said sensing signal, and said transmission driver is configured to inspire said transmission signal through said common transmission/receiving node being pulled to by sending the definite voltage of data.