WO2011047695A1

WO2011047695A1 - Transmission line transceiver for simultaneous bi-directional communication

Info

Publication number: WO2011047695A1
Application number: PCT/EP2009/007519
Authority: WO
Inventors: Bernhard Roth
Original assignee: Verigy (Singapore) Pte. Ltd.
Priority date: 2009-10-20
Filing date: 2009-10-20
Publication date: 2011-04-28
Also published as: CN102577147A; KR20120051072A; TWI448097B; CN102577147B; TW201138337A; KR101341205B1

Abstract

A line transceiver comprises a transmit driver, a current sensing element and a compensation circuit. The transmit driver is able to excite a transmit signal at a common transmit/receive node in dependence on a transmit data. The current sensing element provides a sense signal in dependence on a sense current. Further, the compensation circuit generates a compensation current in dependence on the transmit data, wherein the transmit driver and the compensation circuit are configured to comprise an opposite effect on the sense signal, so that a receive signal incident to the common transmit/receive node causes a larger change of the sense current than a transmit signal of the same signal strength excited by the transmit driver.

Description

TRANSMISSION LINE TRANSCEIVER FOR SIMULTANEOUS BI-DIRECTIONAL

COM MUNICATION

Description

Embodiments according to the invention relate to simultaneous bi-directional communication systems and, particularly, to a line transceiver for simultaneous bidirectional communication through a transmission line and a method for simultaneous bi- directional communication through a transmission line.

Highspeed serial data transmissions in the >lGbit/s range have their best performance when data is sent in one direction, from a transmitter to a receiver. When both transmitter and receiver are implemented at both ends of the data link, it is possible to transfer data in both directions, over the same physical line. However, due to the electrical length of the line itself (Td) there is a waiting time of 2*Td between bursts of data in the different directions, because received data would be corrupted by sent data before that time.

An approach called 'simultaneous bidirectional' has been developed to solve the problem.

Fig. 14 shows a basic principle. Two ends of a data link 1400 have both a driver (Dl and D2) and a comparator (CI and C2). The driver is represented as a switch switching between two static signals where the controlling signal is a digital datastream DDI, DD2. The thresholds of the comparators (- inputs) are switched between two values, where the control signal for the switch is also derived from DDI, DD2, via delay lines DELI, DEL2. As an effect, the positive and negative input of the comparators are substantially equal when only the driver of the same link side is toggling. Differentially, CI does not see activity from Dl, and C2 does not see activity from D2. In most cases the circuits on both sides of the link are the same which leads to VTH1=VTH2 and VTL1=VTL2.

Further conventional examples are , for example, based on the usage of a differential voltage amplifier to subtract the transmitted voltage signal from the composite voltage signal or the usage of a complement version of the transmitted signal and active or passive summing. Documents dealing with this issue are, for example, "Cecchi, Hanson, Preuss: A 2GB/S High Speed Link with Simultaneous Bi-directional 10, CICC 2001", "Yeung, Horowitz: A 2.4Gb/s Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation, IEEE Journal of Solid-State Circuits Vol. 35, No. 11, Nov. 2000" and "Casper, Martin, Jaussi, Kennedy, Mooney: An 8-Gb/s Simultaneous Bidirectional Link With On-Die Waveform Capture, Journal of Solid-State Circuits Vol. 38, No. 12, Dec. 2003".

Summary of the Invention It is the object of the present invention to provide improved concepts for simultaneous bidirectional communication through a transmission line.

This object is solved by an apparatus according to claim 1 or 15 or a method according to claim 28 or 29.

An embodiment of the invention provides a line transceiver for simultaneous bi-directional communication through a transmission line. The line transceiver comprises a transmit driver, a current sensing element and a compensation circuit. The transmit driver is configured to excite a transmit signal at a common transmit/receive node in dependence on transmit data. The current sensing element is configured to provide a sense signal in dependence on a sense current. Further, the compensation circuit is configured to generate a compensation current in dependence on the transmit data. The transmit driver and the compensation circuit are configured to comprise an opposite effect on the sense current, so that a receive signal incident to the common transmit/receive node causes a larger change of the sense current than a transmit signal of the same signal strength excited by the transmit driver.

A further embodiment according to the invention provides another line transceiver for simultaneous bi-directional communication through a transmission line. The line transceiver comprises a transmit driver and a combiner. The transmit driver is configured to excite a transmit signal by pulling a common transmit/receive node to a voltage determined by transmit data. Further, the combiner is configured to combine a first signal representing a voltage at the common transmit/receive node and a second signal representing a driver current provided by the transmit driver, to obtain a sense signal such that a receive signal incident to the common transmit/receive node causes a larger change of the sense signal than a transmit signal of the same signal strength excited by the transmit driver. Embodiments according to the present invention are based on the central idea that a sense signal is generated based on a sense current or a signal representing a driver current of the transmit driver, which is almost independent on a signal to be transmitted in comparison to the dependency of the sense signal on a receive signal incident to the common transmit/receive node. This is realized by compensating at least partly an influence of an excited transmit signal to the sense signal. Therefore, it can be easily distinguished between a transmit signal and a receive signal, although signal components of both may be present at the common transmit/receive node at the same time. In some embodiments according to the invention, it is made use of an opposite effect of a signal excited by the transmit driver and a compensation current or a current representing a driver current on the sense signal. In this way, a change of the sense signal or a sense current is kept low for a transmit signal in comparison to a change of the sense signal or sense current caused by an incident receive signal. Using the described concept may reduce the hardware efforts and/or may increase the sensitivity of the line transceiver.

Brief Description of the Drawings

Embodiments according to the invention will be detailed subsequently referring to the appended drawings, in which:

Fig. la, lb is a block diagram of a line transceiver for simultaneous bi-directional communication through a transmission line;

Fig. 2a, 2b is a block diagram of a line transceiver for simultaneous bi-directional communication through a transmission line; is a schematic illustration of an electrical circuit representing a line transceiver;

Fig. 4 is a schematic illustration of an electrical circuit representing a line transceiver;

Fig. 5 is a schematic illustration of an electrical circuit representing a line transceiver;

Fig. 6 is a schematic illustration of an electrical circuit representing a line transceiver; is a schematic illustration of an electrical circuit representing a line transceiver;

Fig. 8 is a block diagram of a line transceiver for simultaneous bi-directional communication through a transmission line;

Fig. 9 is a block diagram of a line transceiver for simultaneous bi-directional communication through a transmission line; Fig. 10 is a schematic illustration of an electrical circuit representing a line transceiver;

Fig. 11 is a schematic illustration of an electrical circuit representing a line transceiver;

Fig. 12 is a flow chart of a method for simultaneous bi-directional communication through a transmission line;

Fig. 13 is a flow chart of a method for simultaneous bi-directional communication through a transmission line; and

Fig. 14 is a schematic illustration of an electrical circuit representing a known line transceiver for simultaneous bi-directional communication. Detailed Description of the Embodiments

In the following, the same reference numerals are partly used for objects and functional units having the same or similar functional properties and the description thereof with regard to a figure shall apply also to other figures in order to reduce redundancy in the description of the embodiments.

Since both ends of the data link (the transceivers at both ends of the transmission line) are made up of substantially equal circuits, all the following embodiments only show one end of the link. The other end of the link can be imagined as the same arrangement. Alternatively, the transceiver at the other end of the transmission line may be based on another concept for simultaneous bi-directional communication. Fig. la and lb show block diagrams of line transceivers 100, 150 for simultaneous bidirectional communication through a transmission line according to an embodiment of the invention. The line transceiver 100, 150 comprises a transmit driver 110, a current sensing element 120 and a compensation circuit 130. The transmit driver 110 can excite a transmit signal at a common transmit/receive node 1 12 in dependence on transmit data DD. The current sensing element 120 provides a sense signal SI in dependence on a sense current IB. Further, the compensation circuit 130 generates a compensation current IC in dependence on the transmit data DD. The transmit driver 1 10 and the compensation circuit 130 comprise an opposite effect on the sense current IB, so that a receive signal incident to the common transmit/receive node 112 causes a larger change of the sense current ID than a transmit signal of the same signal strength excited by the transmit driver 110. Further, a transmission line TL is shown, which is not part of the line transceiver 100, 150.

Since the transmit driver 110 and the compensation circuit 130 comprise an opposite effect on the sense current IB, the sense current IB may stay almost constant when the transmit driver 110 excites a transmit signal. In contrast, the influence of an incident receive signal to the sense current IB is not compensated by the compensation circuit 130. Therefore, the receive signal can be easily detected by the current sensing element, since the incident receive signal causes a larger change of the sense current IB than a transmit signal of the same signal strength. In this way, the hardware efforts may be reduced. Further, the sensitivity of the line transceiver for sensing a receive signal may be increased, since a current change may be easier detected than a voltage change.

The ratio of the change of the sense current IB between the receive signal and the transmit signal is related to a same signal strength of the receive signal and the transmit signal, in order to provide a defined state for verification of the ratio of the change of the sense current. For normal applications, the signal strength of an incident receive signal may also be larger or lower than the signal strength of a transmit signal. As long as the influence of the receive signal on the sense current is larger than the influence of a transmit signal, the receive signal may be detected, and distinguished from a transmit signal, based on the sense signal SI.

Signals with the same signal strength may be defined, for example, as comprising the same amplitude at the common transmit/receive node or another representative node 112 of a transceiver. For example, the amplitude of a transmit signal at one side of the transmission line TL may comprise the same amplitude, a similar amplitude or an amplitude in the same region as the amplitude of a transmit signal of a transceiver at the other side of the transmission line. In the embodiment of Fig. la, the transmit driver 1 10 of the line transceiver 100, the compensation circuit 130 of the line transceiver 100 and the transmission line TL are connected to the common transmit/receive node 1 12. Further, the current sensing element 120 of the line transceiver 100 is connected to the transmit driver 1 10. When the transmit driver 1 10 excites a transmit signal at the common transmit/receive node 1 12, the voltage at the common transmit/receive node 1 12, and in this way, also the current through the transmission line TL is changed. A change of the current IB provided by the transmit driver 1 10, which would be caused by the excitation of the common transmit/receive node 1 12 in the absence of the compensation current is compensated or nearly compensated by the compensation current IC. Therefore, the sense current IB stays constant or nearly constant. In other words, the sense current IB may be kept at a nearly constant value, which may be also equal to 0. If a signal is received through the transmission line TL, the voltage at the common transmit/receive node 1 12 and the current IB is also changed. However, this current change is not compensated by the compensation circuit 130. So, the sense current IB changes according to the receive signal. This change may be detected by the current sensing element 120 and the corresponding sense signal SI may be provided.

Alternatively, the current sensing element 120 provides the sense current IB, as shown in the embodiment of Fig. lb. In this example, the transmit driver 110 of the line transceiver 150 , the current sensing element 120 of the line transceiver 150, the compensation circuit 130 of the line transceiver 150 and the transmission line TL are connected to the common transmit/receive node 1 12, wherein the current sensing element 120 and the compensation circuit 130 are connected to the common transmit/receive node through a coupling element 102 (for example a resistor). Optional the current sensing element 120 is connected to a DC voltage VDC. Once again, a change of the current IB provided by the current sensing element 120, which would be caused by the excitation of the common transmit/receive node 112 in the absence of the compensation current is compensated or nearly compensated by the compensation current IC of the compensation circuit 130, so that the sense current IB is constant or nearly constant. In contrast, a current change through the transmission line caused by an incident receive signal is not compensated by the compensation circuit 130 and, therefore, the sense current IB is significantly changed.

Fig. 2a shows a more detailed example of the concept shown in Fig. la. The structure of the apparatus 200 is similar to the structure of the apparatus shown in Fig. la. Additionally, the apparatus 200 comprises a comparator C and a series impedance RS (e.g. a series resistor). The comparator C is connected to the current sensing element 120 and the series impedance RS is located between the common transmit receive node 112 and the transmission line TL. The series impedance RS may be equal to an impedance Z of the transmission line TL.

In this example, a Driver Circuit Dl consists of a basic driver D U O and a current sensing block ISNS 120. There is no substantial voltage difference between the output of D 1 10 and the output of D l (node DS). Dl generates, according to the digital input stream, a voltage dV at the node DS. This signal at DS is the transmitted signal via a series impedance RS, the node P and through a transmission line TL with characteristic impedance Z. For example, RS is equal to Z.

IC is the compensating current, generated by the trans-conductance-amplifier TCA1 (compensation circuit 130), also in response to the same digital data stream at DD. TCA1 may be assumed to behave like a current source with sufficiently high source impedance. With the correct scaling it can be achieved that the output current of Dl (IB) is independent or nearly independent of the transmitted signal based on DD. For example, any change in IB may directly translate to a related change of the supply current.

ISNS (current sensing block or current sensor) generates a signal SI which is, for example, either directly or indirectly related to IB. In the latter case SI may represent, for example, the supply current of driver D.

Any incoming signal appears at node P and builds up a voltage across RS and therefore creates a current change at IB which in turn changes the signal SI and then can be compared at the comparator C with a threshold signal Th, creating a digital result signal RC (receive data).

In other words, the comparator provides the receive data RC based on a comparison of the sense signal SI with at least one threshold voltage Th.

In addition, the comparator may comprise a filter at an input of the sensing LSI. The filter may be used for cable-loss compensation. The comparator may also be realized as an analog-digital converter (ADC). The compensation current IC and the sense signal SI may be defined, for example, according to the following equations: IC = -dV/(RS+Z)

SI = f(IB).

In words, for example, the sense signal SI may be a function of the sense current IB. Further, the compensation current may be, for example, equal to a voltage change -dV at the common transmit/receive node 112 divided by the series impedance RS plus the impedance Z of the transmission line or divided by two times the series impedance.

Further, Fig. 2b shows a more detailed example of the concept described in Figs. lb. The structure of the apparatus 250 is similar to the structure of the apparatus shown in Fig. lb. In addition, the apparatus 250 comprises a comparator C and a series impedance RS. The comparator C is connected to the current sensing element 120 and the series impedance RS is arranged between the common transmit/receive node 1 12 and a node connected to the current sensing element 120 and the compensation circuit 130. In other words, the current sensing element 120 and the compensation circuit 130 are connected to the common transmit/receive node 1 12 through the series impedance RS.

In this example, a Buffer Circuit Bl consists of a basic buffer B and a current sensing block ISNS. There is no substantial voltage difference between the output of B and the output of Bl (node DS). Bl generates a low impedance DC voltage at node DS, according to the static input voltage VDC.

TCA2 (transmit driver 110) generates, according to the digital input stream, a current IS into the node P. TCA2 is assumed to behave like a current source with sufficiently high source impedance. A resulting voltage signal builds up at P, across RS, and is the transmitted signal via the node P and through a transmission line TL with characteristic impedance Z. For example, RS is equal to Z.

IC is the compensating current, generated by the trans-conductance-amplifier TCA1 (compensation circuit 130), also in response to the same digital data stream at DD. TCA1 is assumed to behave like a current source with sufficiently high source impedance.

With the correct scaling it can be achieved that the output current of Bl (IB) is independent of the transmitted signal based on DD.

ISNS generates a signal SI which is related to IB. This can happen, for example, directly by sensing the output current of Bl or indirectly by monitoring a supply current of Bl, because usually a change in Bl shows up also as a change in the supply current. Any incoming signal appears at node P and builds up a voltage across RS and therefore creates a current change at IB which in turn changes the signal SI and then can be compared at the comparator C with a threshold signal Th, creating a digital result signal RC.

The ratio of the driver current IS and the compensation current IC as well as the sense signal SI may be defined, for example, according to the following equations:

IC/IS = -Z/(RS+Z)

SI = f(IB)

In words, for example, the sense signal SI may be a function of the sense current IB. Further, the ratio of the compensation current IC and the driver current IS may be, for example, equal to the impedance Z of the transmission line divided by the series impedance RS plus the impedance Z of the transmission line. In some cases, the series impedance RS is equal to the impedance Z of the transmission line and therefore the compensation current IC is approximately half of the driver current IS. How close these two current match their intended ratio (to within 10%, 2% or 1%) defines the overall performance of the circuit. Fig. 3 shows an electronic circuit representing a line transceiver 300 for simultaneous bidirectional communication through a transmission line according to an embodiment of the invention. The structure of the transceiver 300 is similar to the structure of the transceiver shown in Fig. 2a. In this example, the transmit driver 110 comprises a transistor Q3 and a signal-adapting means 314. The signal-adapting means 314 is connected to the base of the transistor Q3 and receives the transmit data DD at an input. The signal-adapting means 14 realizes a level-shifting and/or magnification of the transmit data signal DD to a desired operation point of the transistor Q3. The emitter of the transistor Q3 is connected to the common transmit/receive node 112 and the collector of the transistor Q3 is connected to the current sensing element 120. The sense current IB flows from the common transmit/receive node 112 through the transistor Q3 to the sense current element 120.

The current sensing element 120 comprises a sense resistor RC connected to a static voltage VDC+ and to the collector of the transistor Q3 of the transmit driver 110. The sense current IB flowing through the sense resistor RC causes a voltage drop across the sense resistor RC. The sense signal SI is provided at a node between the sense resistor RC and the collector of the transistor Q3. The voltage drop across the sense resistor RC varies according to a change of the sense current IB and, therefore, also the sense signal SI changes. In this arrangement, the transistor Q3 of the transmit driver 1 10 comprises a high impedance output terminal (e.g. collector terminal) connected to the sense resistor RC and a low impedance input terminal (e.g. emitter terminal) connected to the common transmit/receive node 1 12. Therefore, a small voltage change at the common transmit/receive node 1 12 caused by an incident receive signal generates a huge change of the sense current IB as well as a huge change in the voltage drop through the sense resistor RC and, in this way, also a huge change of the sense signal SI. In addition, voltage changes of a base-emitter-voltage are kept small (typically significantly smaller than 0,7V) due to the small emitter-sided impedance presented by transistor Q3. The compensation circuit 130 comprises of two transistors Ql, Q2 and a current source unit 332 comprising three current sources IDC1, IDC2, IDC3 connected through two resistors Rl, R2, representing a differential amplifier arrangement. The transmit data DD is provided to the base of the first transistor Ql and the inversion/the complement of the transmit data NDD or a static voltage is provided to the base of the second transistor Q2 of the compensation circuit 130. The collector of the first transistor Ql is connected a fixed potential (e.g. to ground) and the emitter of the first transistor Ql is connected to the current source unit 332. Further, the collector of the second transistor Q2 is connected to the common transmit/receive node 1 12 and the emitter of the second transistor Q2 is connected to the current source unit 332.

Alternatively, the transmit data DD may be provided to the transistor Q2 and the inverted transmit data NDD or a static voltage is provided to the transistor Ql . For this alternative, the transmitted data to the transmission line may be the complement of DD (the inverted transmit data DD).

The first current source IDC1 of the current source unit 332 is connected to the emitter of the first transistor Ql and to the second current source IDC2 through the first resistor Rl of the current source unit 332. The third current source IDC3 of the current source unit 332 is connected to the emitter of the second transistor Q2 and to the second current source IDC2 of the current source unit 332 through the second resistor R2 of the current source unit 332. Using three different current sources may reduce, for example, the temperature dependency of the line transceiver 300. Alternatively, the current source unit 332 comprises, for example, only one current source, so that the complexity of the current source unit 332 is reduced.

The second transistor Q2 of the compensation circuit 130 provides the compensation current IC to the common transmit/receive node 1 12 and compensates, in this way, at least partly a change of the reference current IB caused by a voltage change dV at the base of the transistor Q3 corresponding to a change of the transmit data DD.

The optional comparator C may compare the sense signal SI with at least one temporally constant (or at least a plurality of different data values of the transmit data DD) threshold voltage VTHdc to obtain the receive data RC.

The line transceiver 300 comprises at least partly a symmetric architecture in terms of the differential amplifier arrangement of the compensation circuit 130. An at least partly symmetric circuit may enable an at least partial cancellation of parasitic delay effects.

Further, a circuit 390 at the far end of the transmission line TL is illustrated, which is not part of the line transceiver 300, just like the transmission line TL. For example, Q3 and RC represent Dl in fig. 2a with RC representing ISNS which generates the signal SI from the power supply current which is related to IB. DD itself may exhibit some level-shifting and magnification before going to the base of transistor Q3 where a voltage change dV is generated. NDD may be the complement signal of DD or it may be a static voltage.

DD NDD and Rl and R2 and the current sources can be designed so that the current change to on the way to RS and TL is equal to the current change of -IC, keeping IB independent or nearly independent of the digital data stream.

The compensation current IC may be defined, for example, according to the following equation:

IC = -dV/(RS+Z)

The compensation current may be, for example, equal to a voltage change -dV at the common transmit/receive node 1 12 divided by the series impedance RS plus the impedance Z of the transmission line or divided by two times the series impedance. In other words, the transmit driver 1 10 and the compensation circuit 130 may be designed or dimensioned, so that the compensation current is equal to a voltage change -dV at the common transmit/receive node 1 12 divided two times the series impedance, so that the collector-emitter-voltage of transistor Q3 may stay constant or basically constant, although dV chances data-depending.

Fig. 4 shows an electrical circuit representing a line transceiver 400 for simultaneous bidirectional communication through a transmission line according to an embodiment of the invention. The line transceiver 400 is based on the concept shown in Fig. 2b.

The transmit driver 1 10 comprises a transistor Q2, wherein the transmit data DD, the inverted transmit data NDD or a static voltage is provided to the base of the transistor Q2 of the transmit driver 110. The emitter of the transistor Q2 of the transmit driver 1 10 is connected to a current source unit 332 of the compensation circuit 130 and the collector of the transistor Q2 is connected to the common transmit/receive node 1 12. Depending on the transmit data DD, the transistor Q2 of the transmit driver 1 10 excites a transmit signal at the common transmit/receive node 1 12. The current sensing element 120 comprises a transistor Q3 and a sense resistor RC. The emitter of the transistor Q3of the current sensing element 120 is connected to the common transmit/receive node 112 through the series resistor RS and the collector of the transistor Q3 is connected to the sense resistor RC. The sense resistor RC is connected to a DC voltage VDC+. Further, a constant voltage VDCH+ is provided to the base of the transistor Q3 of the current sensing element 120. The sense signal SI is provided at a node between the sense resistor RC and the transistor Q3 of the current sensing element 120. In other words, the current sensing element 120 uses the supply current IB of a transistor Q3 of the current sensing element 120 to provide the sense signal SI. As described for the transistor of the transmit driver in Fig. 3, the transistor Q3 of the current sensing element 120 provides a low impedance input to the common transmit/receive node 1 12 and a high impedance input to the sense resistor RC.

The compensation circuit 130 comprises a transistor Ql, the current source unit 332 and a stimulus cancellation circuit 434. The collector of the transistor Ql is connected to the stimulus cancellation circuit 434 and the emitter of the transistor Ql is connected to the current source unit 332. Further, the transmit data DD, the inverted transmit data NDD or a static voltage is provided to the base of the transistor Ql depending on the kind of signal (DD, NDD, static voltage) provided to the transistor Q2 of the transmit driver 110. Transistor Ql of the compensation circuit 130 and transistor Q2 of the transmit driver 1 10 in combination with the current source unit 332 comprise a differential amplifier arrangement. In addition, the stimulus cancellation circuit comprises a first resistor RSS connected to the collector of transistor Ql of the compensation circuit 130 and connected to a node between the emitter of transistor Q2 of the current sensing element 120 and the series resistor RS as well as a second resistor RZ connected to the collector of transistor Ql and connected to ground. The stimulus cancellation circuit 434 forms a symmetric counterpart to the resistor RS and the transmission line TL. In this way, the line transceiver 400 comprises an at least partly symmetric structure, which may be advantageous for a cancellation of parasitic delay effects.

The structure of the current source unit 332 is equal to the structure of the current source unit shown in Fig. 3. Again, the current source unit 332 is illustrated as a part of the compensation circuit 130. Alternatively, the current source unit 332 may be an independent unit connected to the compensation circuit 130 and the transmit driver 1 10.

For example, Q3 and RC represent the buffer Bl of Fig. 2b with RC representing ISNS, which generates the signal SI from the power supply current, which is related to IB. The circuit consisting of Transistors Q1,Q2, Resistors Rl, R2, RSS,RZ, and current sources IDC1,IDC2,IDC3, represents TCA1 and TCA2, generating IS and IC, from a differential input signal DD/NDD. RSS and RZ are preferably selected to be equal to RS and Z, so that the sum of IC and (IS*Z/(RS+Z)) is always constant. For example, either IDC2 or IDC1 and IDC3 are used as current sources. The first resistor RSS of the stimulus cancellation circuit 434 and the second resistor RZ of the stimulus cancellation circuit 434 may be defined, for example, according to the following equations:

RSS=RS

RZ=Z

In words, the first resistor RSS of the stimulus cancellation circuit 434 is equal to the series resistor RS and the second resistor RZ of the stimulus cancellation circuit 434 the impedance Z of the transmission line.

Fig. 5 shows an alternative implementation of the concept shown in Fig. 2b according to an embodiment of the invention. The line transceiver 500 comprises a similar structure as the line transceiver shown in Fig. 4. In comparison to the line transceiver shown in Fig. 4, the stimulus cancellation circuit 434 is replaced by splitting the transistor Ql of the compensation circuit 130 into two transistors Qla and Qlb. The collector of the first transistor Qla of the compensation circuit 130 is connected to ground and the emitter of the first transistor Qla is connected to the current source unit 332. The collector of the second transistor Qlb of the compensation circuit 130 is connected to a node between the emitter of transistor Q3 and the series resistor RS and the emitter of the second transistor Qlb is connected to the current source unit 332. Further, the transmit data DD, the inverted transmit data NDD or a static voltage is connected to the base of transistor Qla and to the base of the second transistor Qlb of the compensation circuit 130.

The compensation current 130 may comprise a current splitter in terms of the transistors Qla and Qlb, wherein the desired compensation current is determined by the ratio of the transistors Qla and Qlb. In this example, the generation of IC is done by splitting transistor Ql into two transistors Qla and Qlb, where these two are designed so that the ratio of collector currents is so that the sum of IC and (IS*Z/(RS+Z)) is always constant.

The ratio of the current through the second transistor Qlb of the compensation circuit 130 to the current through the first transistor Qla of the compensation circuit 130 may be defined, for example, according to the following equation:

I(Qlb) I(Qla) = Z/RS Fig. 6 shows a slight variation of the line transceiver shown in Fig. 5. In this example, the compensation circuit 130 of the line transceiver 600 comprises a delay resistor RM. The delay resistor RM is located between the collector of the transistor Qlb of the compensation circuit 130 and a node between the emitter of the transistor Q3 of the current sensing element 120 and the series resistor RS..

The resistor RM can be selected so that delays of the currents IS and IC caused by parasitic capacitance C1P, C2P at the collectors of transistor Q2 and transistor Qlb are matched.

The ratio of the current through the second transistor Qlb of the compensation circuit 130 and the current through the first transistor Qla of the compensation circuit 130 as well as the resistor RM may be defined, for example, according to the following equations: I(Qlb)/I(Qla) = Z RS

RM = RS*Z/(RS+Z)*C2p/Clp

Alternatively, Fig. 7 shows another implementation of the principle from Fig. 2b. The line transceiver 700 comprises a total differential signaling. For this, the resistor RC of the current sensing element 120 is split into resistors RCn and RCp and the transistor Q3 is split into the common base transistors Q3n and Q3p. The current sensing element 120 provides a positive and a negative sense signal Sip, Sin to the comparator C. The comparator C provides the receive data RC based on a comparison of the sense signal Sip and sense signal Sin. In this example, the transmit driver 1 10 comprises two transistors, one transistor Ql a with its collector connected to a negative common transmit/receive driver 1 12n and one transistor Q2a with its collector connected to a common transmit/receive node 1 12p. In this example, the line transceiver 700 comprises two common transmit/receive nodes 1 12n, 1 12p, one connected to the negative part of the transmission line TLn and the other connected to the positive part of the transmission line TLp. In addition, the compensation circuit 130 comprises two transistors, one transistor Qlb with its collector connected through a positive delay transistor RMp to the emitter of transistor Q3p and the other transistor Q2b with its collector connected through a negative delay resistor RMn connected to the emitter of the transistor Q3n. All emitters of the transistor of the transmit driver 110 and the compensation circuit 130 shown in Fig. 7 are connected to the current source unit 332.

The parasitic capacitances shown in Fig. 6 are omitted in Fig. 7, although the delay resistors RM may do the same thing in conjunction with these capacitances.

The negative part as well as the positive part of the line transceiver 700 comprises a series resistor RSn, RSp between the emitter of the transistor Q3n, Q3p of the current sensing element 120 and the corresponding common transmit/receive node 1 12n, 1 12b. In this example, the currents IS,IC,IB, signal SI, T-Line TL, transistor Q3 and resistors RS,RC,RM consist of a positive part (ISp,ICb,IBp,TLp,Q3p,RSp,RCp,RMp) and a negative part (ISN,ICn,IBn,TLn,Q3n,RSn,RCn,RMn).

The resistors RSn, RSp and RS as well as the ratio of the compensation current ICp and the current through the transistor Qla of the transmit driver 110 and the ratio of the compensation current ICn and the current through the transistor Q2a of the transmit driver 110 may be defined, for example, according to the following equations: RSn = RSp = RS

ICp/ISn - Z/(RS+Z)

ICn/ISp = Z/(RS+Z) Fig. 8 shows a block diagram of a line transceiver 800 for simultaneous bi-directional communication through a transmission line according to an embodiment of the invention. The transceiver 800 comprises a transmit driver 810 and a combiner 820. The transmit driver 810, the combiner 820 and a transmission line TL are connected to a common transmit/receive node 812. The transmission line TL is not part of the transceiver 800.

The transmit driver 810 can excite a transmit signal by pulling a common transmit/receive node 812 to a voltage determined by transmit data DD. Further, the combiner 820 combines a first signal 814 representing a voltage at the common transmit/receive node 812 and a second signal 816 representing a driver current IB provided by the transmit driver 810 to obtain a sense signal Cmp, such that a receive signal incident to the common transmit/receive node 812 causes a larger change of the sense signal Cmp than a transmit signal of the same signal strength excited by the transmit driver 810.

The influence of a transmit signal excited by the transmit driver 810 can be compensated or nearly compensated by the second signal 816 representing the driver current IB.

For example, a change of the voltage at the common transmit/receive node 812 caused by the transmit driver 810 may comprise an opposite effect on the sense signal Cmp than a change of the second signal caused by a change of the driver current IB provided by the transmit driver 810. In other words, the influence of the voltage change at the common transmit/receive node 812 to the sense signal Cmp may be compensated or nearly compensated by the influence of the second signal 816 representing the drive current IB of the transmit driver 810, so that the sense signal Cmp is kept constant or nearly constant. Fig. 9 shows a block diagram of a line transceiver 900 for simultaneous bi-directional communication through a transmission line based on the principle shown in Fig. 8 according to an embodiment of the invention. The structure of the transceiver 900 is similar to the structure of the transceiver shown in Fig. 8. In addition, a comparator C connected to the combiner 820 and a series resistor RS arranged between the common transmit/receive node 812 and the transmission line TL is illustrated. The transmit driver D 810 pulls the voltage at the common transmit/receive node 812 according to the transmit data DD and provides a corresponding driver current IB. The combiner 820 may generate the second signal 816 inverse proportional to the driver current IB, for example, via a compensation circuit 924. Further, the combiner 820 may comprise an adder 922 configured to generate the sense signal Cmp.

The combiner 820 may provide the sense signal Cmp to the comparator C. The comparator C may compare the sense signal Cmp, for example, with at least one constant threshold voltage Th to obtain the receive data RC.

The compensation circuit 924 may be part of the transmit driver 810 or part of the combiner 820 as indicated by the dashed lines in Fig. 9. Alternatively, the compensation circuit 924 may be an independent hardware unit.

In this example, the sensing of current IB or IS is done so that SI has the inverted polarity of the transmitted signal. Then a simple summing (active or passive) of SI and the transmitted signal DS may substantially eliminate the transmitted signal from the comparator signal Cmp.

Fig. 10 shows an electrical circuit representing a line transceiver 1000 based on the principle shown in Fig. 9 according to an embodiment of the invention. In this example, the transmit driver 810 comprises a pair of complementary output transistors Ql, Q2. The emitters of both transistors Ql, Q2 are connected to the common transmit/receive node 812. The combiner 820 comprises a voltage divider with two resistors Rl, R2. The first resistor Rl is connected to the common transmit/receive node 812 and to the second resistor R2. The second resistor R2 is connected to the first resistor Rl and to ground. The combiner 820 provides the sense signal Cmp for the comparator C at a tab between the first resistor Rl and the second resistor R2. Since the transmit driver 810 comprises two complementary parts, the compensation circuit also comprises two complementary parts 924a, 924b. The first part of the compensation circuit 924a comprises a first current source IC1 and a first current splitter with transistor Q3. The current source IC1 is connected to the collector of the transistor Ql of the transmit driver 810 and connected to the emitters of the transistors of the current splitter. The first current splitter comprises a first transistor Q3 with its collector connected to the tab of the voltage divider of the combiner 820 and another transistor with its collector connected to ground. The bases of the transistors of the first current splitter are biased by a bias voltage VBl for adjusting the operating point of the transistors. The ratio of the current splitter is m/n.

Similar to the first part of the compensation circuit 924a, the second part of the compensation circuit 924b comprises a second current source IC2 and a second current splitter with transistor Q4. The second current source IC2 is connected to the collector of the transistor Q2 of the transmit driver 810 and connected to the emitters of the transistors of the second current splitter. The current splitter comprises two transistors, one transistor Q4 with its collector connected to the tab of the voltage divider of the combiner 820 and another transistor with its collector connected to ground. The transistors of the current splitter are biased by a bias voltage VB2 for adjusting an operation point of the transistors of the current splitter.

The bases of the transistors Ql , Q2 of the transmit driver 810 may be driven by two identical signals based on the transmit data, just apart by a DC-voltage (direct current voltage) representing two diode drops.

Since the transmit driver 810 and the compensation circuit 924a, 924b comprise two complementary parts, the driver current IB1, IB2 and the second signal 816a, 816b comprise also two parts. The two parts of the second signal 816a, 816b are directly provided to the tab of the voltage divider of the combiner 820. Alternatively, the two parts of the second signal 816a, 816b may be combined and then the combined signal is provided to the tab of the voltage divider.

For example, if a transmit signal is excited at the common transmit/receive node 812 by the transmit driver 810, the voltage at the common transmit/receive node is pulled to a higher or a lower voltage. For example, if the voltage at the common transmit/receive node 812 is increased, the driver current IB1 through the transistor Ql of the transmit driver 810 is also increased. In contrast, the driver current IB2 through the transistor Q2 of the transmit driver 810 is reduced. Therefore, the first sense current SCI is decreased and the second sense current SC2 is increased, so that the first sense current SCI and the second sense current SC2 comprise an inverted behavior compared to the driver currents. Both sense currents SCI, SC2 are split by the current splitters, so that the first part of the second signal 816a in terms of the first compensation current CC1 is provided by transistor Q3 of the first current splitter and the second part of the second signal 816b in terms of the second compensation current CC2 is provided by the transistor Q4 of the second current splitter, wherein the first part of the second signal 816a provides a portion of the decreased sense current SCI determined by the ratio of the transistors of the current splitter and the second part of the second signal 816b provides a portion of the increased sense current SC2 determined by the ratio of the second current splitter. Since the first sense current SCI is decreased and the second sense current SC2 is increased, combining the first part of the second signal 816a and the second part of the second signal 816b provides a resulting compensation current to the tab of the voltage divider of the combiner 820. This resulting compensation current comprises an opposite effect on the sense signal Cmp than the first signal 814, which provides the increased voltage at the common transmit/receive node 812 through the first resistor Rl of the voltage divider to the tab of the voltage divider of the combiner 820. In other words, the compensation current compensates, or nearly compensates, the influence of the increased voltage at the common transmit/receive node 812 to the sense signal Cmp. In contrast to the large voltage changes at the common transmit/receive node 812 during exciting a transmit signal by the transmit driver 810, the voltage at the common transmit/receive node 812 changes only slightly if an incident receive signal is received. However, the driver currents IB 1 , IB2 are changed significantly, since the transmit driver 810 provides a low impedance input for an incident receive signal at the common transmit/receive node 812. Therefore, the behavior of the driver currents IB1 , IB2, the sense currents SCI , SC2 and the first and the second part of the second signal 816a, 816b is similar to the behavior described for exciting a transmit signal by the transmit driver 810. Accordingly, the second signal 816 causes a voltage change at the sense signal Cmp. In other words, an incident receive signal causes only a slight change of the first signal 814 in combination with a large change of the second signal 816a, 816b, so that the voltage of the sense signal Cmp is changed significantly. In this example, Ql and Q2 are the usual complementary output transistors of a voltage driver. Their bases are driven by two identical signals, just apart by a dc-voltage representing two diode drops. The collectors of these transistors are connected to current sources IC1 and IC2 and emitters of transistors Q3,Q4. Those transistors work also as current splitters where m/(m+n) of the delta current gets routed to a summing node Cmp. Since this has an inverted voltage effect of the normal drive signal DS (transmit signal), a passive adding of DS via Rl cancels or nearly cancels the drive signal at Cmp when the resistor Rl is selected properly. Any incoming signal from TL also changes the driver output current and also shows up at Cmp without being cancelled. There is a voltage gain for this incoming signal from P to Cmp, which is determined, for example, by the resistor R2.

The gain of the receiver, the first resistor Rl and the second resistor R2 of the voltage divider of the combiner 820 may be defined, for example, by the following equations:

RcvGain=RG=Cmp/Pin

Rl=2*RS*n/m

RS=2*RS*(l+n/m)*RG*(2-RG) The receiver gain RcvGain, RG may be defined as the ratio of the magnitude of a change of the sense signal Cmp caused by an incident receive signal to the magnitude of a change of a voltage at a corresponding input (P), for example an input pin of an ATE. Fig. 1 1 shows an electrical circuit representing a line transceiver 1 100 for simultaneous bidirectional communication through a transmission line according to an embodiment of the invention. The structure of the line transceiver 1 100 is similar to the structure of the line transceiver shown in Fig. 10. Only the current splitters of the compensation circuits are realized within the transmit driver 810 and the resistor R2 of the voltage divider of the combiner 820 is connected to a buffer B providing a variable DC voltage VT. Consequently, the transmit driver 810 comprises a complementary pair of current splitters. All emitters of the transistors of the current splitters are connected to the common transmit/receive node 812. The collector of one transistor Ql of the first current splitter is connected to the first current source IC1 of the first part of the compensation circuit 924a. Further, the collector of one transistor Q2 of the second current splitter is connected to the second current source IC2 of the second part of the compensation circuit 924b.

The line transceiver 1100 works based on the same principle described for Fig. 10. Due to the slightly different structure, the first sense current SCI and the first compensation current CC1 of the line transceiver 1100 are equal (neglecting the base current of transistor Q3) as well as the second sense current SC2 and the second compensation current CC2 (neglecting the base current of transistor Q4).

In other words, the transistors Ql and Q2 are used as current splitters where m/(m+n) of the delta current gets routed to a summing node Cmp via simple cascodes Q3,Q4. Also, R2 is connected to a buffer providing a variable DC voltage VT. This can be useful for optimizing the whole circuit.

The gain of Rev, the first resistor Rl and the second resistor R2 of the voltage divider of the combiner 820 may be defined, for example, according to the following equations:

RcvGain=RG=Cmp/Pin

Rl=2*RS*n/m

RS=2*RS*(l+n/m)*RG*(2-RG)

Fig. 12 shows a flow chart of a method 1200 for simultaneous bi-directional communication through a transmission line according to an embodiment of the invention. The method 1200 comprises providing 1210 a sense signal in dependence on a sense current and generating 1220 a compensation current in dependence on transmit data. The compensation current and the transmit signal to be excited at a common transmit/receive node in dependence on the transmit data comprise an opposite effect on the sense current, so that a receive signal incident to the common transmit/receive node causes a larger change of the sense current than a transmit signal of the same signal strength.

Fig. 13 shows a flow chart of a method 1300 for simultaneous bi-directional communication through a transmission line according to an embodiment of the invention. The method 1300 comprises combining 1310 a first signal representing a voltage at a common transmit/receive node and a second signal representing a driver current provided by a transmit driver to obtain a sense signal such that a receive signal incident to the common transmit/receive node causes a larger change of the sense signal than a transmit signal of the same signal strength excited by the transmit driver, wherein the transmit signal is excited by pulling the common transmit/receive node to a voltage determined by transmit data.

Some embodiments according to the invention relate to a method of simultaneous bidirectional data link. In other words, some embodiments relate to an electronic bi-directional signaling circuit where a supply current of the transmitting driver is used to generate the signal to be compared. The same may be done, for example, with differential signals. In addition, a filter may be added at the input of the comparator, for example, for cable-loss compensation. According to a further aspect, symmetric circuits, for example, for cancellation of parasitic delay effects may be used. In some embodiments, the trans- conductance amplifiers (TCA) may be realized as linear amplifiers or current switches and/or cascodes above collectors may be used for current-splitting. Alternatively, multipliers may be used as a current-splitter, for example, for adjustment or calibration of resistor-miss-matches.

For example, the proposed invention uses the information inside the supply current of a transmit driver to perform the separation of transmitted and received signals.

Although all embodiments described above use bi-polar transistors, it is obvious that the bi-polar transistors can be replaced by field-effect transistors. In addition, a replacement of the transistors of a line transceiver by the complementary transistors may be possible. For example, PNP transistors or field-effect transistors may be used instead of NPN transistors. In other words, PNP transistors may be replaced by NPN transistors and vice- versa as well as P-field-effect transistors may be replaced by N-field-effect transistors and vice-versa.

Some embodiments according to the invention relate to an automated test equipment (ATE) comprising a line transceiver described above. For example, the ATE pin- electronics may be realized with this approach.

The terms "compensated", "nearly compensated", "constant", "nearly constant", "cancels", "nearly cancels", "independent" and "nearly independent" in connection with changes of the sense current or the sense signal caused by a transmit signal are related to an comparison with a change of the sense current or the sense signal caused by an incident receive signal. In other words, changes caused by a transmit signal may be neglected in comparison with changes caused by an incident receive signal.

Although some aspects have been described in the context of an apparatus, it is clear that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus.

Claims

Line transceiver (100; 150; 200; 250; 300; 400; 500; 600; 700) for simultaneous bidirectional communication through a transmission line, the line transceiver (100) comprising: a transmit driver (110) configured to excite a transmit signal at a common transmit/receive node (112) in dependence on transmit data (DD); a current sensing element (120) configured to provide a sense signal (SI) in dependence on the sense current (IB); and a compensation circuit (130) configured to generate a compensation current (IC) in dependence on the transmit data (DD), wherein the transmit driver (110) and the compensation circuit (130) are configured to comprise an opposite effect on the sense current (IB), so that a receive signal incident to the common transmit/receive node (112) causes a larger change of the sense current (IB) than a transmit signal of the same signal strength excited by the transmit driver (110).

Line transceiver (300; 400; 500; 600; 700), wherein the current sensing element (120) comprises a sense resistor (RC) configured to cause a change of a voltage of the sense signal (SI) if the sense current (IB) changes, wherein the sense current (IB) flows through the sense resistor (RC).

Line transceiver (300; 400; 500; 600; 700) according to claim 2, wherein the current sensing element (120) or the transmit driver (110) comprises a transistor (Q3) with a high impedance terminal connected to the sense resistor (RC) and a low impedance terminal connected to the common transmit/receive node (112).

Line transceiver (200; 250) according to one of the claims 1 to 3, wherein the compensation circuit (130) comprises a trans-conductance amplifier (TCA1) configured to generate the compensation current (IC).

Line transceiver (300) according to one of the claims 1 to 4, wherein the compensation circuit (130) comprises a differential amplifier arrangement configured to provide the compensation current (IC) by a transistor of the differential amplifier arrangement.

Line transceiver (400; 500; 600; 700) according to one of the claims 1 to 4, wherein the compensation circuit (130) in combination with the transmit driver (1 10) comprises a differential amplifier arrangement comprising a transistor of the compensation circuit (130) configured to generate the compensation current (IC) and a transistor of the transmit driver (1 10) configured to excite a transmit signal at the common transmit/receive node (112).

Line transceiver (500; 600; 700) according to one of the claims 1 to 6, wherein the compensation circuit (130) comprises a current splitter (Qla, Qlb) configured to provide the compensation current (IC).

Line transceiver (600; 700) according to one of the claims 1 to 7, wherein the compensation circuit (130) comprises a delay resistor (RM) configured to match a delay between the compensation current (IC) and a transmit signal to be excited at the common transmit/receive node (1 12), wherein the compensation current (IC) flows through the delay resistor RM.

Line transceiver (700) according to one of the claims 1 to 8, wherein the line transceiver is configured for a differential signal processing.

Line transceiver (100; 200; 300) according to one of the claims 1 to 9, comprising a series impedance (RS) located between the common transmit/receive node (1 12) and a transmission line to be connected to the line transceiver, wherein the compensation current (IC) is equal to a voltage change (-dV) at the common transmit/receive node (1 12) caused by a transmit signal excited by the tranmit driver (1 10) divided by a sum of the series impedance (RS) and an impedance (Z) of the transmission line.

Line transceiver (150; 250; 400; 500; 600; 700) according to one of the claims 1 to 10, wherein a value of the compensation current (IC) and a half of a value of a driver current (IS) provided by the transmit driver (1 10) are equal or a difference of the value of the compensation current (IC) and the half of the value of the driver current (IS) provided by the transmit driver (1 10) is smaller than 10% of the value of the driver current (IS) provided by the transmit driver (110).

12. Line transceiver (300) according to one of the claims 1 to 1 1 , further comprising: a series resistor (RS) located between the common transmit/receive node (1 12) and an input terminal configured to be connected to a transmission line TL; and a comparator (C) configured to provide receive data (RC) based on a comparison of the sense signal (SI) provided by the current sensing element (120) with a threshold voltage (VTHdc), wherein the transmit driver (1 10) comprises a transistor (Q3) and a signal-adapting means (314), wherein an emitter of the transistor (Q3) of the transmit driver (1 10) is connected to the common transmit/receive node (1 12) and a collector of the transistor (Q3) of the transmit driver (1 10) is connected to the current sensing element (120), wherein the signal-adapting means (314) is configured to adapt the transmit data (DD) and to provide the adapted transmit data signal (dV) to the base of the transistor (Q3) of the transmit driver (1 10), wherein the current sensing element (120) comprises a sense resistor (RC) connected to the transistor (Q3) of the transmit driver (110) and connected to a constant voltage (VDC+), wherein the current sensing element (120) is configured to provide the sense signal (SI) at a node between the sense resistor (RC) and the transistor (Q3) of the transmit driver (110), wherein the compensation circuit (130) comprises a firsts transistor (Ql), a second transistor (Q2) and a current source unit (332), wherein a collector of the first transistor (Ql) of the compensation circuit (130) is connected to ground and an emitter of the first transistor (Ql) of the compensation circuit (130) is connected to the current source unit (332), wherein a collector of the second transistor (Q2) of the compensation circuit (130) is connected to the common transmit/receive node (1 12) and an emitter of the second transistor (Q2) of the compensation circuit (130) is connected to the current source unit (332), wherein a signal based on the transmit data (DD), an inverted transmit data (NDD) or a static signal is provided to the base of the first transistor (Ql) of the compensation circuit (130) and the base of the second transistor (Q2) of the compensation circuit (130).

13. Line transceiver (400) according to one of the claims 1 to 1 1 , further comprising: a series resistor (RS) located between the common transmit/receive node (1 12) and the current sensing element (120); and a comparator (C) configured to provide receive data (RC) based on a comparison of the sense signal (SI) provided by the current sensing element (120) with a threshold voltage (VTHdc), wherein the transmit driver (1 10) comprises a transistor (Q2), wherein a collector of the transistor (Q2) of the transmit driver (110) is connected to the common transmit/receive node (1 12) and an emitter of the transistor (Q2) of the transmit driver (1 10) is connected to the compensation circuit (130), wherein the current sensing element (120) comprises a sense resistor (RC) and a transistor (Q3), wherein the sense resistor (RC) is connected to the transistor (Q3) of the current sensing element (120) and connected to a constant voltage (VDC+), wherein a collector of the transistor (Q3) of the current sensing element (120) is connected to the sense resistor (RC) and an emitter of the transistor (Q3) is connected to the common transmit/receive node (112) through the resistor (RS), wherein a constant voltage (VDCH+) is provided to the base of the transistor (Q3) of the current sensing element (120), wherein the compensation circuit (130) comprises a transistor (Ql), a stimulus cancellation circuit (434) and a current source unit (332), wherein a collector of the transistor (Ql) of the compensation circuit (130) is connected to the stimulus cancellation circuit (434) and an emitter of the transistor (Ql) of the compensation circuit (130) is connected to the current source unit (332), wherein the transmit data (DD), an inverted transmit data (NDD) or a static signal is provided to the basis of the transistor (Ql) of the compensation circuit (130) and the transistor (Q2) of the transmit driver (1 10), wherein the stimulus cancellation circuit (434) comprises a first resistor (RSS) connected to the transistor (Ql) of the compensation circuit (130) and connected to a node between the transistor (Q3) of the current sensing element (120) and the series resistor (RS) and comprising a second resistor (RZ) connected to a node located between the transistor (Ql) of the compensation circuit (130) and the first resistor (RSS) of the stimulus cancellation circuit (434) and connected to ground. Line transceiver (500) according to one of the claims 1 to 11, further comprising: a series resistor (RS) located between the common transmit/receive node (112) and the current sensing element (120); and a comparator (C) configured to provide receive data (RC) based on a comparison of the sense signal (SI) provided by the current sensing element (120) with a threshold voltage (VTHdc), wherein the transmit driver (110) comprises a transistor (Q2), wherein a collector of the transistor (Q2) of the transmit driver (110) is connected to the common transmit/receive node (1 12) and an emitter of the transistor (Q2) of the transmit driver (110) is connected to the compensation circuit (130), wherein the current sensing element (120) comprises a sense resistor (RC) and a transistor (Q3), wherein the sense resistor (RC) is connected to the transistor (Q3) of the current sensing element (120) and connected to a constant voltage (VDC+), wherein a collector of the transistor (Q3) of the current sensing element (120) is connected to the sense resistor (RC) and an emitter of the transistor (Q3) is connected to the common transmit/receive node (112) through the resistor (RS), wherein a constant voltage (VDCH+) is provided to the base of the transistor (Q3) of the current sensing element (120), wherein the compensation circuit (130) comprises a current source unit (332) and a current splitter comprising a first transistor (Qla) and a second transistor (Qlb), wherein a collector of the first transistor (Qla) of the current splitter is connected to ground and wherein an emitter of the first transistor (Qla) of the current splitter is connected to the current source unit (332), wherein a collector of the second transistor (Qlb) of the current splitter is connected to a node located between the transistor (Q3) of the current sensing element (120) and the series resistor (RS) and an emitter of the second transistor (Qlb) of the current splitter is connected to the current source unit (332), wherein the transmit data (DD), an inverted transmit data (NDD) or a static signal is provided to the first transistor (Qla) of the current splitter, the second transistor (Qlb) of the current splitter and the transistor (Q2) of the transmit driver (110).

15. Line transceiver (600) according to claim 14, comprising a delay resistor (RM) connected to the collector of the second transistor (Qlb) of the compensation circuit (130) and the node between the transistor (Q2) of the current sensing element (120) and the series resistor (RS).

16. Line transceiver (700) according to one of the claims 1 to 1 1, configured for a differential signal processing, wherein the transmit driver (110) is configured to excite a transmit signal at a negative common transmit/receive node (1 12n) and at a positive common transmit/receive node (112p) in dependence on transmit data (DD), wherein the current sensing element (120) is configured to provide a negative sense signal (Sin) in dependence on a negative sense current (IBn) and a positive sense signal (Sip) in dependence on a positive sense current (IBp), wherein the compensation circuit (130) is configured to generate a negative compensation current (ICn) and a positive compensation current (ICp) in dependence on the transmit data (DD), wherein the transmit driver (110) and the compensation circuit (130) are configured to comprise an opposite effect on the negative sense current (IBn) and the positive sense current (IBp), so that a receive signal incident to the negative common transmit/receive node (112) and the positive transmit/receive node (112b) causes a larger change of the negative sense current (IBn) and the positive sense current (IBp) than a transmit signal of the same signal strength excited by the transmit driver (110), the line transceiver (700) further comprising: a first series resistor (RSn) connected to the negative common transmit/receive node (112n) and connected to the current sensing element (120); a second series resistor (RSp) connected to the positive common transmit/receive node (112b) and connected to the current sensing element (120); and a comparator (C) configured to provide receive data (RC) based on a comparison of the negative sense signal (Sin) with the positive sense signal (Sip), wherein the transmit driver (110) comprises a first transistor (Qla) and a second transistor (Q2a), wherein a collector of the first transistor (Qla) of the transmit driver (110) is connected to the negative common transmit/receive node (112n) and an emitter of the first transistor (Qla) of the transmit driver (110) is connected to the compensation circuit (130), wherein a collector of the second transistor (Q2a) of the transmit driver (110) is connected to the positive common transmit/receive node (1 12p) and an emitter of the second transistor (Q2a) of the transmit driver (1 10) is connected to the compensation circuit (130), wherein the current sensing element (120) comprises a first transistor (Q3n), a second transistor (Q3p), a first sense resistor (RCn) and a second sense resistor

(RCp), wherein a collector of the first transistor (Q3n) of the current sensing element (120) is connected to the first sense resistor (RCn) of the current sensing element (120) and an emitter of the first transistor (Q3n) of the current sensing element (120) is connected to the negative common transmit/receive node (1 12n) through the first series resistor (RSn), wherein the first sense resistor (RCn) of the current sensing element (120) is connected to the first transistor (Q3n) of the current sensing element (120) and connected to a constant voltage (VDC+), wherein a collector of the second transistor (Q3p) of the current sensing element (120) is connected to the second sense resistor (RCp) of the current sensing element (120) and an emitter of the second transistor (Q3p) of the current sensing element

(120) connected to the positive common transmit/receive node (112p) through the second sense resistor (RCp) of the line transceiver (700), wherein the second sense resistor (RCp) of the current sensing element (120) is connected to the collector of the second transistor (Q3p) of the current sensing element (120) and connected to the constant voltage (VDC+), wherein the negative sense signal (Sin) is provided at a node between the first sense resistor (RCn) of the current sensing element (120) and the first transistor (Q3n) of the current sensing element (120), wherein the positive sense signal (Sip) is provided at the node between the second sense resistor (RCp) of the current sensing element (120) and the second transistor (Q3p) of the current sensing element (120), wherein the compensation circuit (130) comprises a first transistor (Qlb), a second transistor (Q2b), a first delay resistor (RMp), a second delay resistor (RMn) and a current source unit (332), wherein a collector of the first transistor (Qlb) of the compensation circuit (130) is connected through the first delay resistor (RMp) to a node between the second transistor (Q3p) of the current sensing element (120) and the second series resistor (RSp) and an emitter of the first transistor (Qlb) of the compensation circuit (130) is connected to the current source unit (332), wherein a collector of the second transistor (Q2b) of the compensation circuit (130) is connected through the second delay resistor (RMn) of the compensation circuit

(130) to a node between the first transistor (Q3n) of the current sensing element (120) and the first series resistor (RSn) and an emitter of the second transistor (Q2b) of the compensation circuit (130) is connected to the current source unit (332).

Line transceiver (800; 900; 1000; 1 100) for simultaneous bi-directional communication through a transmission line, the line transceiver (800) comprising: a transmit driver (810) configured to excite a transmit signal by pulling a common transmit/receive node (812) to a voltage determined by transmit data (DD); and a combiner (820) configured to combine a first signal (814) representing a voltage at the common transmit/receive node (812) and a second signal (816) representing a driver current (IB) provided by the transmit driver (810) to obtain a sense signal (CMP) such that a receive signal incident to the common transmit/receive node (812) causes a larger change of the sense signal (CMP) than a transmit signal of the same signal strength excited by the transmit driver (810).

Line transceiver (800; 900; 1000; 1 100) according to claim 17, wherein the combiner (820) is configured, such that the change of the voltage at the common transmit/receive node (812) caused by the transmit driver (810) comprises an opposite effect on the sense signal (CMP) than a change of the driver current (IB) provided by the transmit driver (810) caused by the change of the voltage at the common transmit/receive node (812).

Line transceiver (1000; 1 100) according to claim 17 or 18, wherein the combiner (820) comprises a voltage divider with an input connected to the common transmit/receive node (812), wherein the voltage divider is configured to combine the first signal (814) and the second signal (816) at the tab, and wherein the voltage divider is configured to provide the sense signal (CMP) at the tab.

Line transceiver (1000; 1 100) according to claim 18, wherein a second input of the voltage divider is connected to a voltage source comprised by the combiner (820), wherein the voltage source is configured to provide a variable direct current voltage to the voltage divider.

Line transceiver (1000; 1 100) according to one of the claims 17 to 20, wherein the transmit driver (810) comprises a complementary voltage driver comprising at least one pair of complementary transistors, wherein the common transmit/receive node (812) is located between the complementary pair of transistors.

22. Line transceiver (1000; 1 100) according to claim 21, wherein the second signal (816) comprises a first portion of a compensation current and a second portion of a compensation current, wherein the first portion of the compensation current represents a current provided by one transistor of the pair of complementary transistors and the second portion of the compensation current represents a current provided by the other transistor of the pair of complementary transistors.

23. Line transceiver (1000; 1 100) according to one of the claims 17 to 22, comprising a compensation circuit (924) connected to the transmit driver (1 10) and to the combiner (820) and comprising a current source configured to provide a constant source current, so that a current of the second signal (816) is increased, if the driver current is decreased, and so that a current of the second signal (816) is decreased, if the driver current is increased.

24. Line transceiver (1000) according to one of the claims 17 to 23, the line transceiver further comprising: a series resistor (RS) connected to the common transmit/receive node (812) and connected to a transmission line to be connected to the line transceiver (1000); and a comparator (C) configured to provide receive data (RC) based on a comparison of the sense signal (CMP) with a threshold voltage (Th), wherein the combiner (820) is configured to provide the sense signal (CMP), wherein the transmit driver (810) comprises a complementary pair of transistors (Ql, Q2), wherein emitters of both complementary transistors are connected to the common transmit/receive node (812), wherein the collector of the first transistor (Ql) of the pair of complementary transistors is connected to a first part of a compensation circuit (924a), wherein a collector of the second transistor (Q2) of the complementary pair of transistors is connected to a second part of a compensation circuit (924b), wherein a first drive signal is provided to the base of the first transistor (Ql) of the transmit driver (810) based on the transmit data, wherein a second drive signal based on the transmit data is provided to the base of the second transistor (Q2) of the transmit driver (810), wherein a first drive signal based on the transmit data is provided to the basis of the first transistors of the transmit driver (810), wherein a second drive signal based on the transmit data is provided to the bases of the second transistors of the transmit driver (810), wherein the combiner (820) comprises a voltage divider comprising a first resistor (Rl) and a second resistor (R2), wherein the first resistor of the voltage divider is connected to the common transmit/receive node (812) and to the second resistor, wherein the second resistor (R2) of the voltage divider is connected to the first resistor (Rl) and to ground, wherein the first part of the compensation circuit (924a) comprises a first current source (IC1) and a first current splitter comprising a first transistor and a second transistor (Q3), wherein the first current source (IC1) is connected to the collector of the first transistor (Ql) of the transmit driver (810) and connected to the first current splitter, wherein an emitter of the first transistor of the first current splitter is connected to a node between the first current source (IC1) and the first transistor (Ql) of the transmit driver (810), wherein a collector of the first transistor of the first current splitter is connected to ground, wherein an emitter of the second transistor (Q3) of the first current splitter is connected to the node between the first current source (IC1) and the first transistor (Ql) of the transmit driver (810), wherein a collector of the second transistor (Q3) of the first current splitter is connected to a tab of the voltage divider located between the first resistor (Rl) and the second resistor (R2) of the voltage divider, wherein the second part of the compensation circuit (924b) comprises a second current source (IC2) and a second current splitter comprising a first transistor and a second transistor (Q4), wherein the second current source (IC2) is connected to the collector of the second transistor (Q2) of the transmit driver (810) and connected to the second current splitter, wherein an emitter of the first transistor of the second current splitter is connected to a node between the second current source (IC2) and the second transistor (Q2) of the transmit driver (810), wherein a collector of the first transistor of the second current splitter is connected to ground, wherein an emitter of the second transistor (Q4) of the second current splitter is connected to the node between the second current source (IC2) and the second transistor (Q2) of the transmit driver (810), wherein a collector of the second transistor (Q4) of the second current splitter is connected to the tab of the voltage divider, wherein a first bias voltage (VB1) is provided to the bases of the transistors of the first current splitter, wherein a second bias voltage (VB2) is provided to the bases of the transistors of the second current splitter.

Line transceiver (1 100) according to one of the claims 17 to 23, further comprising: a series resistor (RS) connected to the common transmit/receive node (812) and connected to a transmission line to be connected to the line transceiver (1000); a comparator (C) configured to provide receive data (RC) based on a comparison of the sense signal (CMP) with a threshold voltage (Th), wherein the combiner (820) is configured to provide the sense signal (CMP); and a buffer B providing a constant voltage VT to the combiner (820), wherein the transmit driver (810) comprises a complementary pair of current splitters, wherein the first current splitter of the pair of complementary current splitters comprises a first transistor and a second transistor (Ql), wherein the second current splitter of the pair of complementary current splitters comprises a first transistor and a second transistor (Q2), wherein all emitters of the transistors of the pair of complementary current splitters are connected to the common transmit/receive node (812), wherein a collector of the second transistor (Ql) of the first current splitter is connected to a first part of a compensation circuit (924a), wherein a collector of the second transistor (Q2) of the second current splitter is connected to a second part of a compensation circuit (924b), wherein a first drive signal based on the transmit data is provided to the bases of the transistors of the first current splitter, wherein a second drive signal based on the transmit data is provided to the bases of the transistors of the second current splitter, wherein the combiner (820) comprises a voltage divider comprising a first resistor

(Rl) and a second resistor (R2), wherein the first resistor of the voltage divider is connected to the common transmit/receive node (812) and to the second resistor, wherein the second resistor (R2) of the voltage divider is connected to the first resistor (Rl) and to ground, wherein the first part of the compensation circuit (924a) comprises a first current source (IC1) and a transistor (Q3), wherein the first current source (IC1) is connected to the collector of the second transistor (Ql) of the first current splitter of the transmit driver (810) and connected to an emitter of the transistor (Q3) of the first part of the compensation circuit (924a), wherein a collector of the transistor

(Q3) of the first part of the compensation circuit (924a) is connected to the tab of the voltage divider of the combiner (820), wherein a first bias voltage is provided to the base of the transistor (Q3) of the first part of the compensation circuit (924a), wherein the second part of the compensation circuit (924b) comprises a second current source (IC2) and a transistor (Q4), wherein the second current source (IC2) is connected to the collector of the second transistor (Q2) of the second current splitter of the transmit driver (810) and connected to an emitter of the transistor (Q4) of the second part of the compensation circuit (924b), wherein a collector of the transistor (Q4) of the second part of the compensation circuit (924b) is connected to the tab of the voltage divider of the combiner (820), wherein a second bias voltage (VB2) is provided to the base of the transistor (Q4) of the second part of the compensation circuit (924b).

Line transceiver according to one of the claims 1 to 9 or 17 to 23, comprising a comparator configured to provide a receive data (RC) based on a comparison of the sense signal with a threshold signal.

Line transceiver according to claim 26, wherein the comparator comprises a filter at an input of the sense signal.

Line transceiver according to one of the claims 1 to 9, 17 to 23 or 26 to 27, wherein the line transceiver comprises an at least partly symmetric structure.

Automated test equipment comprising a line transceiver according to one of the claims 1 to 28.

Method (1200) for simultaneous bi-directional communication through a transmission line, the method comprising: providing (1210) a sense signal in dependence on a sense current; and generating (1220) a compensation current in dependence on transmit data, wherein the compensation current and a transmit signal excited at a common transmit/receive node in dependence on transmit data comprise an opposite effect on the sense current, so that a receive signal incident to the common transmit/receive node causes a larger change of the sense current than a transmit signal of the same signal strength excited by the transmit driver.

Method (1300) for simultaneous bi-directional communication through a transmission line, the method comprising: combining (1210) a first signal representing a voltage at a common transmit/receive node and a second signal representing a driver current provided by a transmit driver configured to excite a transmit signal by pulling the common transmit/receive node to a voltage determined by transmit data to obtain a sense signal such that the receive signal incident to the common transmit/receive node causes a larger change of the sense signal than a transmit signal of the same signal strength excited by the transmit driver.