CN102568820A - Coplanar built-in capacitor and manufacture method thereof - Google Patents
Coplanar built-in capacitor and manufacture method thereof Download PDFInfo
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- CN102568820A CN102568820A CN2010106173186A CN201010617318A CN102568820A CN 102568820 A CN102568820 A CN 102568820A CN 2010106173186 A CN2010106173186 A CN 2010106173186A CN 201010617318 A CN201010617318 A CN 201010617318A CN 102568820 A CN102568820 A CN 102568820A
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Abstract
The invention provides a coplanar built-in capacitor and a manufacture method of the coplanar built-in capacitor and is applicable to the field of a printed circuit board. The capacitor comprises a lower layer capacitor electrode, an upper layer capacitor electrode and a dielectric layer, wherein the dielectric layer is positioned between the lower layer capacitor electrode and the upper layer capacitor electrode and is formed by dielectric materials through spray printing by adopting the inkjet printing technology. The embodiment of the invention has the advantages that the inkjet printing technology is adopted for realizing the spray printing on the dielectric layer, the thickness of the dielectric layer is reduced, and the uniformity of the dielectric layer is enhanced, so the unit capacitance density of the coplanar built-in capacitor is improved, and in addition, the capacitance tolerance value is reduced; a magnetron sputtering technology is adopted for sputtering conducting seed layers, the bonding force between the dielectric layer and the capacitor electrodes is enhanced, and the mutual diffusion between the dielectric layer and the capacitor electrodes is prevented, so the reliability of the coplanar built-in capacitor is improved, and the development requirements of electronic devices in miniaturization and multifunctional directions in future are met.
Description
Technical field
The invention belongs to the printed circuit board field, relate in particular to a kind of coplane formula built-in capacitance and manufacturing approach thereof.
Background technology
Along with developing rapidly of semiconductor integrated circuit industry, the Electronic Packaging specification requirement is encapsulated in passive devices such as electric capacity in the circuit board, to save the space, improves electric property.
Electric capacity as being built in the circuit board is divided into coplane formula and high density interconnect type built-in capacitance according to the technology difference.Coplane formula built-in capacitance has simply obtained using widely with its technology.But present coplane formula built-in capacitance adopts silk-screen or roller coating technology to make dielectric layer, is difficult to form large tracts of land and thin, uniform dielectric layer, can't satisfy the needs that following electronic device develops to miniaturization, multifunction direction.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of coplane formula built-in capacitance, and it is thicker and make uneven problem to be intended to solve existing coplane formula built-in capacitance dielectric layer.
The embodiment of the invention is achieved in that a kind of coplane formula built-in capacitance, and said electric capacity comprises:
Lower floor's capacitance electrode, upper strata capacitance electrode; And
Dielectric layer between said lower floor capacitance electrode and said upper strata capacitance electrode, said dielectric layer is formed by the dielectric material spray printing.
Another purpose of the embodiment of the invention is to provide a kind of embedded circuit board that comprises above-mentioned electric capacity.
Another purpose of the embodiment of the invention is to provide a kind of manufacturing approach of coplane formula built-in capacitance, and said method comprises the steps:
Preparation lower floor's capacitance electrode and upper strata capacitance electrode;
The dielectric material spray printing in said lower floor capacitance electrode surface and said upper strata capacitance electrode surface, is formed dielectric layer.
The embodiment of the invention adopts inkjet technology that the dielectric material spray printing is processed dielectric layer; Reduced the thickness of dielectric layer; Strengthened the uniformity of dielectric layer; Thereby improved the specific capacitance density of coplane formula built-in capacitance and reduced the capacitance tolerance value, thereby improved the reliability of coplane formula built-in capacitance, satisfied the needs that following electronic device develops to miniaturization, multifunction direction.
Description of drawings
The structure chart of the coplane formula built-in capacitance that Fig. 1 provides for one embodiment of the invention;
The structure chart of the another kind of coplane formula built-in capacitance that Fig. 2 provides for one embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention adopts inkjet technology spray printing dielectric layer, with the thickness that reduces dielectric layer, the uniformity that improves dielectric layer, adopts magnetron sputtering technique sputter conductive seed layer, to have strengthened the adhesion between dielectric layer and the electrode.
The structure of the buried capacitor that provides as first embodiment of the invention comprises:
Lower floor's capacitance electrode, upper strata capacitance electrode; And
Dielectric layer between said lower floor capacitance electrode and said upper strata capacitance electrode, said dielectric layer adopts the inkjet technology spray printing to form by dielectric material.
Below in conjunction with specific embodiment realization of the present invention is elaborated.
The structure of the coplane formula built-in capacitance that Fig. 1 provides for the embodiment of the invention for the ease of explanation, only shows the part relevant with the embodiment of the invention.
The surface of lower floor's capacitance electrode 11 has the uniform first sub-dielectric layer 21, and the surface of upper strata capacitance electrode 12 has the uniform second sub-dielectric layer 22.
In embodiments of the present invention, the thickness of dielectric layer 2 can be controlled spray printing by capacitance as required, and dielectric layer 2 is thin more, and the specific capacitance density of built-in capacitance is high more; Dielectric layer 2 more even capacitance tolerance values are more little.
As one embodiment of the invention; Can use Copper Foil as lower floor's capacitance electrode 11 and upper strata capacitance electrode 12; Can use the higher high dielectric ink of dielectric coefficient as dielectric material, the dielectric coefficient of dielectric material is high more, and it is high more that the ratio of coplane formula built-in capacitance buries the appearance value.
As one embodiment of the invention; Also has the first electronic conduction Seed Layer 31 between lower floor's capacitance electrode 11 and the dielectric layer 2; Also has the second electronic conduction Seed Layer 32 between upper strata capacitance electrode 12 and the dielectric layer 2; This first electronic conduction Seed Layer 31 and the second electronic conduction Seed Layer 32 adopt the magnetron sputtering technique sputter to form by the conduction target, referring to Fig. 2.
This first electronic conduction Seed Layer 31 and the second electronic conduction Seed Layer 32 can be used metallic nickel materials as transition zone; Lower floor's capacitance electrode 11, upper strata capacitance electrode 12 are combined closely with dielectric layer 2 respectively, and can stop diffusion mutually between dielectric layer 2 and lower floor's capacitance electrode 11, the upper strata capacitance electrode 12.
As one embodiment of the invention, this conductive seed layer adhesion is strong more, and the reliability of built-in capacitance is high more.
As one embodiment of the present invention, the first electronic conduction Seed Layer 31 and the second electronic conduction Seed Layer 32 can also use metallic copper or material with carbon element as the conduction target.
The coplane buried capacitor that the embodiment of the invention provides can be placed in the embedded circuit board of any kind of after cutting.
The manufacture method of the buried capacitor that the embodiment of the invention provides is following:
At first, preparation lower floor's capacitance electrode 11 and upper strata capacitance electrode 12;
Secondly, adopt the inkjet technology spray printing in lower floor's capacitance electrode 11 surfaces and upper strata capacitance electrode 12 surfaces dielectric material, solidify the back and form dielectric layer 2, its structure is as shown in Figure 1.
In embodiments of the present invention, can use Copper Foil to make upper strata capacitance electrode 12 and lower floor's capacitance electrode 11.
As one embodiment of the present of invention, dielectric layer 2 can through with the even spray printing of dielectric material in lower floor's capacitance electrode 11 surfaces, solidify the back and form the first sub-dielectric layer 21; With the even spray printing of dielectric material in the upper strata capacitance electrode 12 surfaces, solidify the back and form the second sub-dielectric layer 22; This first sub-dielectric layer 21 and 22 pairs of the second sub-dielectric layers are pressed formation, and its structure is as shown in Figure 1.
In embodiments of the present invention, can use high dielectric ink as dielectric material, the thickness of dielectric layer 2 can be controlled spray printing by capacitance as required, and dielectric layer 2 is thin more, and the specific capacitance density of built-in capacitance is high more; Dielectric layer 2 more even capacitance tolerance values are more little.
As a preferred embodiment of the present invention, dielectric layer 2 can form the first electronic conduction Seed Layer 31 through conducting electricity target material magnetic sputtering in lower floor's capacitance electrode 11 surfaces; To conduct electricity target material magnetic sputtering in the upper strata capacitance electrode 12 surfaces, form the second electronic conduction Seed Layer 32; The dielectric material spray printing in the first electronic conduction Seed Layer, 31 surfaces, is solidified the back and forms the first sub-dielectric layer 21; The dielectric material spray printing in the second electronic conduction Seed Layer, 32 surfaces, is solidified the back and forms the second sub-dielectric layer 22; This first sub-dielectric layer 21 and 22 pairs of the second sub-dielectric layers are pressed formation, and its structure is as shown in Figure 2.
As one embodiment of the invention; This first electronic conduction Seed Layer 31 and the second electronic conduction Seed Layer 32 can be used metallic nickel materials as transition zone; Lower floor's capacitance electrode 11, upper strata capacitance electrode 12 are combined closely with dielectric layer 2 respectively; And can stop diffusion mutually between dielectric layer 2 and lower floor's capacitance electrode 11, the upper strata capacitance electrode 12, this conductive seed layer adhesion is strong more, and the reliability of built-in capacitance is high more.
As one embodiment of the present invention, the first electronic conduction Seed Layer 31 and the second electronic conduction Seed Layer 32 can also use metallic copper or material with carbon element as the conduction target.
The embodiment of the invention adopts inkjet technology spray printing dielectric layer, has reduced the thickness of dielectric layer, has strengthened the uniformity of dielectric layer, thereby has improved the specific capacitance density of coplane formula built-in capacitance and reduced the capacitance tolerance value; Adopt magnetron sputtering technique sputter conductive seed layer; Strengthened the adhesion between dielectric layer and the capacitance electrode; Prevent counterdiffusion mutually between dielectric layer and the capacitance electrode; Thereby improved the reliability of coplane formula built-in capacitance, satisfied the needs that following electronic device develops to miniaturization, multifunction direction.
More than be merely preferred embodiment of the present invention,, all any modifications of within spirit of the present invention and principle, being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention not in order to restriction the present invention.
Claims (12)
1. coplane formula built-in capacitance is characterized in that said electric capacity comprises:
Lower floor's capacitance electrode, upper strata capacitance electrode; And
Dielectric layer between said lower floor capacitance electrode and said upper strata capacitance electrode, said dielectric layer is formed by the dielectric material spray printing.
2. electric capacity as claimed in claim 1 is characterized in that, said dielectric layer is formed pressure by first sub-dielectric layer that is positioned at said lower floor capacitance electrode surface and the second sub-dielectric layer that is positioned at capacitance electrode surface, said upper strata;
The said first sub-dielectric layer and the said second sub-dielectric layer form by the dielectric material spray printing.
3. electric capacity as claimed in claim 1 is characterized in that, also comprises the first electronic conduction Seed Layer between said lower floor capacitance electrode and the said dielectric layer, also comprises the second electronic conduction Seed Layer between said upper strata capacitance electrode and the said dielectric layer;
Said first electronic conduction Seed Layer and the said second electronic conduction Seed Layer form by the conduction target material magnetic sputtering.
4. electric capacity as claimed in claim 1 is characterized in that, said dielectric material is high dielectric ink.
5. electric capacity as claimed in claim 3 is characterized in that, said conduction target is a metallic nickel.
6. electric capacity as claimed in claim 3 is characterized in that, said conduction target is metallic copper or carbon.
7. an embedded circuit board is characterized in that, said circuit board comprises like each described electric capacity of claim 1 to 6.
8. the manufacturing approach of a coplane formula built-in capacitance is characterized in that, said method comprises the steps:
Preparation lower floor's capacitance electrode and upper strata capacitance electrode;
The dielectric material spray printing in said lower floor capacitance electrode surface and said upper strata capacitance electrode surface, is formed dielectric layer.
9. method as claimed in claim 8 is characterized in that, said dielectric layer forms through following step:
The dielectric material spray printing in said lower floor capacitance electrode surface, is formed the first sub-dielectric layer;
With the dielectric material spray printing in said upper strata capacitance electrode surface, form the second sub-dielectric layer;
The said first sub-dielectric layer and the said second sub-dielectric layer are formed said dielectric layer to pressing.
10. method as claimed in claim 8 is characterized in that, said dielectric layer forms through following step:
To conduct electricity target material magnetic sputtering in said lower floor capacitance electrode surface, form the first electronic conduction Seed Layer;
To conduct electricity target material magnetic sputtering in said upper strata capacitance electrode surface, form the second electronic conduction Seed Layer;
The dielectric material spray printing in said first electronic conduction Seed Layer surface, is formed the first sub-dielectric layer;
The dielectric material spray printing in said second electronic conduction Seed Layer surface, is formed the second sub-dielectric layer;
The said first sub-dielectric layer and the said second sub-dielectric layer are formed said dielectric layer to pressing.
11., it is characterized in that said dielectric material is high dielectric ink like each described method of claim 8 to 10.
12. method as claimed in claim 10 is characterized in that, said conduction target is a metallic nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2010106173186A CN102568820A (en) | 2010-12-31 | 2010-12-31 | Coplanar built-in capacitor and manufacture method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010106173186A CN102568820A (en) | 2010-12-31 | 2010-12-31 | Coplanar built-in capacitor and manufacture method thereof |
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| CN102568820A true CN102568820A (en) | 2012-07-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111044183A (en) * | 2019-12-24 | 2020-04-21 | 浙江清华柔性电子技术研究院 | Flexible pressure sensor and preparation method thereof |
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| CN1374666A (en) * | 2000-08-24 | 2002-10-16 | 奥克-三井有限公司 | Formation of embedded capacitor polar plate sing thin dielectric |
| CN1660579A (en) * | 2004-02-27 | 2005-08-31 | 佳能株式会社 | Dielectric element, piezoelectric element ink jetting head and recording device,and mfg.method |
| CN1829420A (en) * | 2005-03-02 | 2006-09-06 | 三星电机株式会社 | Printed circuit board with embedded capacitors therein and manufacturing process thereof |
| CN1968576A (en) * | 2005-11-17 | 2007-05-23 | 三星电机株式会社 | Fabricating method of printed circuit board having embedded component |
| CN101525511A (en) * | 2008-03-07 | 2009-09-09 | 财团法人工业技术研究院 | Curable cross-linked type ink composition and dielectric film |
| CN102543426A (en) * | 2010-12-29 | 2012-07-04 | 深南电路有限公司 | Built-in capacitor and manufacturing method thereof |
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2010
- 2010-12-31 CN CN2010106173186A patent/CN102568820A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1374666A (en) * | 2000-08-24 | 2002-10-16 | 奥克-三井有限公司 | Formation of embedded capacitor polar plate sing thin dielectric |
| CN1660579A (en) * | 2004-02-27 | 2005-08-31 | 佳能株式会社 | Dielectric element, piezoelectric element ink jetting head and recording device,and mfg.method |
| CN1829420A (en) * | 2005-03-02 | 2006-09-06 | 三星电机株式会社 | Printed circuit board with embedded capacitors therein and manufacturing process thereof |
| CN1968576A (en) * | 2005-11-17 | 2007-05-23 | 三星电机株式会社 | Fabricating method of printed circuit board having embedded component |
| CN101525511A (en) * | 2008-03-07 | 2009-09-09 | 财团法人工业技术研究院 | Curable cross-linked type ink composition and dielectric film |
| CN102543426A (en) * | 2010-12-29 | 2012-07-04 | 深南电路有限公司 | Built-in capacitor and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111044183A (en) * | 2019-12-24 | 2020-04-21 | 浙江清华柔性电子技术研究院 | Flexible pressure sensor and preparation method thereof |
| CN111044183B (en) * | 2019-12-24 | 2022-03-18 | 浙江清华柔性电子技术研究院 | Flexible pressure sensor and preparation method thereof |
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Application publication date: 20120711 |