CN102546611B - Interface implementation method integrating power monitoring bus protocol and serial communication protocol - Google Patents
Interface implementation method integrating power monitoring bus protocol and serial communication protocol Download PDFInfo
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Abstract
Disclosed is an interface implementation method integrating a power monitoring bus protocol and a serial communication protocol. The method includes: integrating the PM (power monitoring) bus protocol and the serial communication bus I2C protocol by means of a state machine; starting the working process of the method by the aid of a start signal on a bus; firstly judging whether a model is a PM bus model or a serial communication I2C model if the start signal exists; if the model is the PM bus model, further judging whether malfunction interrupt ARA (airborne radar attachment) exists or not and whether reading operations or writing operations are performed, and finally judging whether the reading operations or the writing operations are performed for one byte or two bytes, thereby performing one of a one-byte reading operation, a two-byte reading operation, a one-byte writing operation and a two-byte writing operation; and if the model is the serial communication I2C, further judging whether the reading operations or the writing operations are performed and finally finishing transmission by the aid of a stop signal of the bus.
Description
Technical field
The present invention relates to Power Supply Monitoring agreement PMBus interface and serial communication I2C interface, belong to the design of integrated circuit, be subordinate to electronic technology field.
Background technology
Power management bus (PMBus) communication protocol normalized definition an open standard digital power management agreement (comprising interface and order) being used between power conversion apparatus and management device.By PMBus, digital power can be configured, monitor and safeguard according to a set of standard commands, and in the time breaking down or move warning, designer can use PMBus instruction to set the running parameter of power supply, monitors its working condition and implement corrective action.And serial communication I2C agreement is a kind of two-wire system standard for serial communication, each slave has a specific address, and the transmission rate of I2C can reach 100kbit/s under mode standard, under quick mode, can reach 400kbit/s, under fast mode, can reach 3.4Mbit/s.
The communication specification of the data link layer of PMBus agreement is to come from I2C agreement, but PMBus seldom needs transfer of data and the transmission mode at a high speed of big data quantity, therefore the present invention is intended to design an interface circuit, this interface circuit can meet PMBus agreement and I2C agreement simultaneously, under PMBus pattern, can not need very fast speed and large data volume just can realize PMBus, and under I2C pattern, can realize fast the transfer of data with big data quantity.So just realize on the basis of single one physical address, can realize the monitoring of PMBus agreement and the transmission of the I2C protocol data of big data quantity simultaneously.
Summary of the invention
The invention provides integrating power supply controlling bus agreement and serial communication protocol interface realizing method, the method, in accordance with PMBus agreement and I2C communication protocol, has fully been optimized the integration of two interfaces, has used ten less states just to realize invention.
Technical scheme of the present invention is as follows:
An interface realizing method for integrating power supply controlling bus agreement and serial communication protocol, is characterized in that:
Flow process enters beginning, directly carries out afterwards the judgement of start signal, judges on Power Supply Monitoring bus PMBus whether have start signal, if there is no start signal, return to beginning, if there is start signal, enter mode decision, judgement is PMBus communication pattern, or I2C communication pattern.
If be judged as Power Supply Monitoring bus PMBus communication pattern, carry out fault interrupting ARA judgement, judge whether to exist fault interrupting ARA; If there is fault interrupting ARA, enter failure response ARA response, send slave addresses data to PMBus bus, and enter beginning after completing address transmission; If there is no ARA interrupts, enter Power Supply Monitoring bus PMBus operation read-write judgement, judge whether to carry out PMBus read operation, if PMBus read operation, further reading of 1 byte or 2 byte datas carried out in judgement, if the reading of 1 byte data, enter Power Supply Monitoring bus PMBus pattern, read 1 byte, after completing 1 byte and reading, enter beginning, if the reading of 2 byte datas, enter 2 bytes of Power Supply Monitoring bus PMBus mode reads, complete after 2 bytes read and enter beginning; If not Power Supply Monitoring bus PMBus read operation, writing of 1 byte or 2 byte datas carried out in judgement, if the writing of 1 byte data, enter Power Supply Monitoring bus PMBus pattern and write 1 byte, complete after 1 byte writes and enter beginning, if writing of 2 byte datas enters Power Supply Monitoring bus PMBus pattern and write 2 bytes, complete after 2 bytes write and enter beginning.
Not Power Supply Monitoring bus PMBus communication pattern if be judged as, enter the judgement of serial communication I2C read operation, if be judged as read operation, enter the operation of serial communication I2C mode reads and carry out reading of data, then under serial communication I2C pattern, carry out the judgement of bus read operation stop signal, judge and in bus, whether have stop signal, if there is stop signal, complete data and read, and enter beginning, if there is no stop signal, keeps carrying out reading of data; If be judged as write operation, enter I2C pattern write operation and carry out writing of data, under I2C pattern, carry out again the total line write transactions stop of PMBus signal, judge and in bus, whether have stop signal, if there is stop signal, data have write, and enter beginning, if there is no stop signal, keeps carrying out writing of data.
The invention of this compound PMBus agreement and I2C protocol interface implementation method, adopt Verilog HDL to write completely, by functional verification, and can pass through DC logic synthesis software synthesis, thereby the gate cell circuit of the standard of use is built, and the flexibility of design is very large, if need to design be adjusted, can suitably adjust as required at any time and revise, applicability be strong.
Advantage of the present invention and useful achievement:
1) the present invention is based on PMBus bus design, meet the standard of Power Supply Monitoring bus PMBus agreement completely, better compatible, can directly apply to have in the Power Supply Monitoring environment of Power Supply Monitoring bus PMBus control.
2) design integration I2C bus of the present invention, is equally also the communication protocols standard that meets the current I2C of serial completely, can, in realizing Power Supply Monitoring, also can realize the transfer of data between bus device.
3) circuit design theory is simple, easily realize, can by after DC logic synthesis by standard gate circuits built, preparation technology is simple.
4) alterability of circuit is good, can need to carry out suitable adjustment and modification according to concrete utilization.
5) realized the integration of high performance PMBus interface and I2C interface with the simplest structure, occupied chip area little, power consumption is also less.
Accompanying drawing explanation
Fig. 1 is flow chart of the present invention.
Fig. 2 is system state diagram of the present invention.
Fig. 3 be two kinds of patterns of the present invention while switching main signal be related to schematic diagram (first half).
Fig. 4 be two kinds of patterns of the present invention while switching main signal be related to schematic diagram (latter half).
Fig. 5 is the simulation waveform figure (first half) that two kinds of patterns of the present invention are switched.
Fig. 6 is the simulation waveform figure (latter half) that two kinds of patterns of the present invention are switched.
Embodiment
An interface realizing method for integrating power supply controlling bus agreement and serial communication protocol, is characterized in that:
Flow process enters and starts 1, directly carrying out afterwards start signal 2 judges, judge on Power Supply Monitoring bus PMBus and whether have start signal, if there is no start signal, return and start 1, if there is start signal, enter mode decision 3, judgement is PMBus communication pattern, or I2C communication pattern.
If be judged as Power Supply Monitoring bus PMBus communication pattern, carry out fault interrupting ARA4 judgement, judge whether to exist fault interrupting ARA; If there is fault interrupting ARA, enter failure response ARA response 5, send slave addresses data to PMBus bus, and enter beginning 1 after completing address transmission; If there is no ARA interrupts, enter Power Supply Monitoring bus PMBus operation read-write and judge 6, judge whether to carry out PMBus read operation, if PMBus read operation, further reading of 1 byte or 2 byte datas carried out in judgement, if the reading of 1 byte data, enter Power Supply Monitoring bus PMBus pattern, read 1 byte 8, after completing 1 byte and reading, enter and start 1, if the reading of 2 byte datas, enter 2 bytes 9 of Power Supply Monitoring bus PMBus mode reads, complete after 2 bytes read and enter and start 1; If not Power Supply Monitoring bus PMBus read operation, writing of 1 byte or 2 byte datas carried out in judgement, if the writing of 1 byte data, enter Power Supply Monitoring bus PMBus pattern and write 1 byte 11, complete after 1 byte writes and enter and start 1, if writing of 2 byte datas enters Power Supply Monitoring bus PMBus pattern and write 2 bytes 9, complete after 2 bytes write and enter and start 1.
Not Power Supply Monitoring bus PMBus communication pattern if be judged as, enter the judgement of serial communication I2C read operation 13, if be judged as read operation, enter serial communication I2C mode reads operation 14 and carry out reading of data, then under serial communication I2C pattern, carry out bus read operation stop signal 15 and judge, judge and in bus, whether have stop signal, if there is stop signal, complete data and read, and enter beginning 1, if there is no stop signal, keeps carrying out reading of data; If be judged as write operation, enter I2C pattern write operation 16 and carry out writing of data, under I2C pattern, carry out again the total line write transactions stop of PMBus signal 17, judge and in bus, whether have stop signal, if there is stop signal, data have write, and enter beginning 1, if there is no stop signal, keeps carrying out writing of data.
This method is based on state machine design, state machine comprises IDLE, Addr, ARA & send address, COMMAND, Data_Write, Restart & Addr_R, Data_Read, I2C_Write, I2C_Read and ten states of STOP, if detect within any stage and have stop signal in PMBus bus, state machine directly enters beginning, otherwise normally works.State machine is in the time starting or during without any operation, always in starting, and in the time start signal being detected in PMBus bus, state machine enters Addr state, when now mode_sel signal is low level, enter PMBus transmission mode, if mode_sel signal enters I2C transmission mode while being high level, under PMBus transmission mode, in the time that alert_n is low level, illustrate that ARA interrupts, state machine enters ARA & send address state, under this state, slave addresses data are sent to the output of PMBus bus, ARA response complement mark port produces high level pulse signal indication and completes ARA response, can carry out subsequent operation, otherwise state machine enters COMMAND state, state machine receives the serial order data of a byte in PMBus bus, and export from order output port, produce a high level pulse signal at order output enable end simultaneously, if while now restart signal being detected in PMBus bus, enter Data_Write state, otherwise proceed to Data_Read state after entering the read data address that Restart & Addr_R state reads PMBus bus input, under Data_Write state, if when byte or word select signal to be high level, represent a byte manipulation, the data of PMBus bus input are delivered to data-out port output, and produce high level pulse signal at data output enable end, if when byte or word select signal to be low level, two byte datas of PMBus bus input are exported by data-out port successively, and after each byte end of transmission, produce a high level pulse signal at data output enable end, and enter beginning, under Data_Read state, the input port data that need send to PMBus bus data will be read, if signal selected in byte or word is high level, high level pulse signal of data latch enable output output, and read the data that need send to PMBus bus a byte on the input port of data, if signal selected in byte or word is low level, two high level pulse signals of data latch enable output output, and being read successively by high level pulse signal controlling need be to the data of two bytes on the input port of PMBus bus transmission data, after having read of data, enter beginning.Under I2C transmission mode, read by turn after the 8bits data on PMBus universal serial bus according to I2C agreement, judge read-write operation according to the lowest order of institute's read data, in the time that lowest order is high level, I2C enters I2C_Read state, and on data latch enable output, produce a high level pulse signal, the data that now need send on the input port of data to PMBus bus are delivered to PMBus bus, and duplicate reading is according to operation afterwards; Enter I2C_Write pattern if lowest order is low level I2C, the 8bits data on data-out port parallel output PMBus universal serial bus, and a high level pulse signal of data output enable end generation, repeat data writing operation afterwards.If detect under I2C_Read state and I2C_Write state, PMBus bus stop signal proceeds to beginning, waits for monitoring or the transfer of data of a new round.
Below in conjunction with accompanying drawing and example, circuit structure of the present invention, operation principle and process are described further.
Fig. 1 is flow chart of the present invention, and flow process comprises beginning, start signal, PMBus pattern, ARA interruption, ARA response, PMB read operation, reads 1 byte, 1 byte of PMBus mode reads, 2 bytes of PMBus mode reads, writes 1 byte, PMBus pattern is write 1 byte, PMBus pattern is write 2 bytes, I2C read operation, the operation of I2C mode reads, read operation stop signal, I2C write operation and 17 steps of write operation stop signal.Object of the present invention is exactly to realize the data transmission of two kinds of patterns, so the mode realizing enters under corresponding pattern exactly, then complete reading or write operation of response, and be all to need judge and select according to specific condition entering which kind of pattern and carrying out which kind of operation, so the core of this flow chart is made corresponding judgement according to characteristic signals exactly, then complete the selection of pattern and action type according to flow process, thereby realize the integration of two kinds of protocol interfaces.
Be state diagram of the present invention referring to Fig. 2, comprise IDLE, Addr, ARA & send address, COMMAND, Data_Write, Restart & Addr_R, Data_Read, I2C_Write, I2C_Read and ten states of STOP.The present invention has designed a kind of state machine that adopts less status number, thereby has well realized the interface method of PMBus protocol interface and the integration of I2C protocol interface.This interface method has PMBus pattern and two kinds of patterns of I2C pattern, and under PMBus pattern, can respond ARA interrupts, under PMBus pattern, can realize monitoring to power supply or the read-write of fixed byte data, and under I2C pattern, can realize the data read-write operation of indefinite byte number, under two patterns, this interface method has all played the effect of string data transaction.By the subsequent conditioning circuit of the giving parallel serial data from PMBus, or from subsequent conditioning circuit, read parallel data, then sending to PMBus bus of serial.
Fig. 3 be two kinds of patterns of the present invention while switching main signal be related to schematic diagram (first half).The PMBus pattern before conversion of having drawn in figure under two kinds of patterns of PMBus and I2C transmission reads the schematic diagram of the key signal of two byte datas, when transmission is high level from scl, sda is from the low level commencing signal of hypermutation, then bus transmits slave addresses, from figure, can read it is 8 ' hD0 (8 ' b11010000), then PMBus bus send master_data[7:0] on order data 8 ' h10, through 9 scl clocks, cmd_accept[7:0] receive order data 8 ' h10, and cmd_en produces a high level pulse; Then bus produces heavy commencing signal, then bus transmits slave addresses, from figure, can read it is 8 ' hD1 (8 ' b11010001), then read continuously data_accept[7:0] on two data 8 ' h20 and 8 ' h46, and produce a stop_en high level pulse, represent end operation.Then mode_sel becomes high level from original low level, represents to be transformed to I2C communication pattern.
Fig. 4 be two kinds of patterns of the present invention while switching main signal be related to schematic diagram (latter half).This figure is actually the continuity of Fig. 3, but owing to considering typesetting, so the graph of a relation that two kinds of patterns are switched is divided into Fig. 3 and Fig. 4.The I2C pattern after conversion of having drawn in figure under two kinds of patterns of PMBus and I2C transmission writes the schematic diagram of the key signal of three byte datas, mode_sel becomes high level from low level and starts, now pattern is I2C pattern by PMBus Mode change, when transmission is high level from scl, sda is from the low level commencing signal of hypermutation, then PMBus bus transmits slave addresses, from figure, can read it is 8 ' hD0 (8 ' b11010000), then PMBus bus send master_data[7:0] on order data 8 ' h05, through 9 scl clocks, data accept[7:0] receive data 8 ' h05, and data_en produces a high level pulse, then PMBus bus sends master_data[7:0 for the second time] on order data 8 ' h17, through 9 scl clocks, data_accept[7:0] receive data 8 ' h17, and data_en produce a high level pulse, then PMBus bus sends master_data[7:0 for the third time] on order data 8 ' h28, through 9 scl clocks, data_accept[7:0] receive data 8 ' h29, and data_en produce a high level pulse, complete the rear PMBus of writing of three secondary data and produce a stop signal, so stop_en produces a high level pulse, represent EO.
Fig. 5 is the simulation waveform figure (first half) that two kinds of patterns of the present invention are switched.This figure is the first half that is read two byte datas and write to I2C pattern the analogous diagram that three byte datas switch by PMBus pattern, and namely PMBus pattern reads the oscillogram of two byte datas.As can be seen from the figure, this interface circuit can switch smoothly between PMBus and two patterns of I2C.In figure at cmd_accept[7:0] receive order data 8 ' h08 that main frame sends, after cmd_en enables effectively, the rcv_data[7:0 of main frame] receive continuously two from machine data 8 ' h0a and 8 ' h0f.
Fig. 6 is the simulation waveform figure (latter half) that two kinds of patterns of the present invention are switched.This figure is the latter half that is read two byte datas and write to I2C pattern the analogous diagram that three byte datas switch by PMBus pattern, and namely I2C pattern writes the oscillogram of three byte datas.In fact, this simulation figure is the continuity of Fig. 5, so but be also in order to consider that analogous diagram is divided into Fig. 5 and Fig. 6 by typesetting.As can be seen from the figure, this interface circuit can switch smoothly between PMBus and two patterns of I2C.In figure at master_rcv[7:0] receive smoothly data 8 ' h0f, and produced stop_en high level pulse.Then mode_sel signal becomes high level from low level, namely pattern becomes I2C pattern, data_accept[7:0] once receive data 8 ' h18,8 ' h20 and 8 ' h28 from PMBus bus, and produce corresponding data_en and enabled high level pulse signal, finally produce stop_en high level pulse, represented the end of transmission.
Claims (1)
1. an interface realizing method for integrating power supply controlling bus agreement and serial communication protocol, is characterized in that:
Flow process enters beginning (1), directly carry out afterwards start signal (2) judgement, judge on Power Supply Monitoring bus PMBus and whether have start signal, if there is no start signal, return to beginning (1), if there is start signal, enter mode decision (3), judgement is PMBus communication pattern, or I2C communication pattern, described mode decision is as follows: state machine is in the time starting or during without any operation, always in starting, and in the time start signal being detected in PMBus bus, state machine enters Addr state, when now mode_sel signal is low level, enter PMBus transmission mode, if mode_sel signal enters I2C transmission mode while being high level,
If be judged as Power Supply Monitoring bus PMBus communication pattern, carry out fault interrupting ARA (4) judgement, judge whether to exist fault interrupting ARA, if there is fault interrupting ARA, enter failure response ARA response (5), send slave addresses data to PMBus bus, and enter beginning (1) after completing address transmission, if there is no ARA interrupts, enter Power Supply Monitoring bus PMBus operation read-write judgement (6), judge whether to carry out PMBus read operation, if PMBus read operation, further reading of 1 byte or 2 byte datas carried out in judgement, if the reading of 1 byte data, enter Power Supply Monitoring bus PMBus pattern, read 1 byte (8), after completing 1 byte and reading, enter beginning (1), if the reading of 2 byte datas, enter Power Supply Monitoring bus PMBus 2 bytes of mode reads (9), complete after 2 bytes read and enter beginning (1), if not Power Supply Monitoring bus PMBus read operation, writing of 1 byte or 2 byte datas carried out in judgement, if the writing of 1 byte data, enter Power Supply Monitoring bus PMBus pattern and write 1 byte (11), complete after 1 byte writes and enter beginning (1), if writing of 2 byte datas enters Power Supply Monitoring bus PMBus pattern and write 2 bytes (9), complete after 2 bytes write and enter beginning (1),
Not Power Supply Monitoring bus PMBus communication pattern if be judged as, enter the judgement of serial communication I2C read operation (13), if be judged as read operation, enter serial communication I2C mode reads operation (14) and carry out reading of data, under serial communication I2C pattern, carry out again bus read operation stop signal (15) judgement, judge and in bus, whether have stop signal, if there is stop signal, completing data reads, and enter beginning (1), if there is no stop signal, keeps carrying out reading of data; If be judged as write operation, enter I2C pattern write operation (16) and carry out writing of data, under I2C pattern, carry out again the total line write transactions stop of PMBus signal (17) judgement, judge and in bus, whether have stop signal, if there is stop signal, data have write, and enter beginning (1), if there is no stop signal, keeps carrying out writing of data.
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| US20110302357A1 (en) * | 2010-06-07 | 2011-12-08 | Sullivan Jason A | Systems and methods for dynamic multi-link compilation partitioning |
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