CN102546611B - Interface implementation method integrating power monitoring bus protocol and serial communication protocol - Google Patents

Abstract

Integrated power monitoring bus protocol and serial communication protocol interface implementation method, the present invention integrates the power monitoring bus PMBus protocol and serial communication bus I2C protocol in the form of a state machine, and the work flow of the invention starts with the start signal on the bus, if If there is a start signal, the mode judgment is first performed to determine whether it is the power monitoring bus PMBus mode or the serial communication I2C mode. If it is the PMBus mode of the power supply monitoring bus, it is further judged whether there is a fault interrupt ARA and whether it is a read or write operation judgment, and finally judges whether it is a read or write operation of one or two bytes, so as to realize reading 1 byte, reading One of the four operations of 2 bytes, write 1 byte, and write 2 bytes. If it is a serial communication I2C mode, further judge whether it is a read or write operation, and finally end the transmission with the stop signal of the bus.

Description

Implementation method of integrated power monitoring bus protocol and serial communication protocol interface

technical field

The invention relates to a power monitoring protocol PMBus interface and a serial communication I2C interface, which belongs to the design of integrated circuits and belongs to the field of electronic technology.

Background technique

The Power Management Bus (PMBus) communication protocol specification defines an open standard digital power management protocol (including interfaces and commands) used between power conversion devices and management devices. With PMBus, digital power supplies can be configured, monitored, and maintained according to a set of standard commands. In the event of a fault or operational warning, designers can use PMBus commands to set operating parameters of the power supply, monitor its operating status, and implement corrective measures. The serial communication I2C protocol is a two-wire serial communication standard. Each slave has a specific address. The transmission rate of I2C can reach 100kbit/s in standard mode and 400kbit/s in fast mode. , up to 3.4Mbit/s in high-speed mode.

The communication specification of the data link layer of PMBus agreement is derived from I2C agreement, but PMBus seldom needs the data transmission of large amount of data and high-speed transmission mode, so the present invention aims at designing an interface circuit, and this interface circuit can satisfy PMBus simultaneously. Protocol and I2C protocol, in PMBus mode, PMBus can be realized without very fast speed and large data volume, while in I2C mode, fast and large data volume data transmission can be realized. In this way, on the basis of a single physical address, the monitoring of the PMBus protocol and the data transmission of the I2C protocol with a large amount of data can be realized at the same time.

Contents of the invention

The present invention provides a method for implementing an integrated power monitoring bus protocol and a serial communication protocol interface. The method fully optimizes the integration of the two interfaces while complying with the PMBus protocol and the I2C communication protocol, and realizes it with less than ten states invented.

Technical scheme of the present invention is as follows:

A method for implementing an interface integrating a power supply monitoring bus protocol and a serial communication protocol, characterized in that:

The process enters the beginning, and then directly judges the start signal to judge whether there is a start signal on the power monitoring bus PMBus. If there is no start signal, return to the beginning. If there is a start signal, enter the mode judgment to judge whether it is PMBus communication mode or I2C communication model.

If it is judged to be the PMBus communication mode of the power supply monitoring bus, it will judge whether there is a fault interrupt ARA to judge whether there is a fault interrupt ARA; if there is a fault interrupt ARA, it will enter a fault response ARA response, send the slave address data to the PMBus bus, and complete the address sending Then enter the start; if there is no ARA interrupt, enter the power monitoring bus PMBus operation read and write judgment, judge whether to perform PMBus read operation, if it is PMBus read operation, then further judge whether to perform 1 byte or 2 byte data Read, if it is the reading of 1 byte of data, enter the power monitoring bus PMBus mode, read 1 byte, after completing the reading of 1 byte, enter the start, if it is the reading of 2 bytes of data , then enter the power monitoring bus PMBus mode to read 2 bytes, and enter the start after completing the reading of 2 bytes; if it is not a power monitoring bus PMBus read operation, then judge whether to write 1 byte or 2 bytes of data Enter, if it is a write of 1 byte of data, then enter the power monitoring bus PMBus mode to write 1 byte, after completing the writing of 1 byte, enter the start, if it is the writing of 2 bytes of data, enter Write 2 bytes in power monitoring bus PMBus mode, and enter the start after completing the writing of 2 bytes.

If it is judged that it is not the PMBus communication mode of the power supply monitoring bus, then enter the judgment of the serial communication I2C read operation, if it is judged as a read operation, then enter the serial communication I2C mode read operation to read the data, and then enter the serial communication I2C mode Next, judge the stop signal of the bus read operation to judge whether there is a stop signal on the bus. If there is a stop signal, complete the data reading and enter the start. If there is no stop signal, keep reading the data; if it is judged to be a write operation, enter the I2C mode write operation to write data, and then perform the PMBus bus write operation stop signal in the I2C mode to judge whether there is a stop signal on the bus. If there is a stop signal, the data writing is completed and enters the start. If there is no stop signal, data writing is kept.

The invention of the implementation method of the composite PMBus protocol and I2C protocol interface is completely written in VerilogHDL, has passed the functional verification, and can be synthesized by DC logic synthesis software, so that the standard gate unit circuit can be used to build, and the design flexibility is very large. If The design needs to be adjusted, and it can be properly adjusted and modified according to the needs at any time, with strong applicability.

Advantage of the present invention and beneficial result:

1) The present invention is based on the design of the PMBus bus, fully conforms to the standard of the PMBus protocol of the power monitoring bus, has good compatibility, and can be directly applied to a power monitoring environment controlled by the PMBus control of the power monitoring bus.

2) The design of the present invention integrates the I2C bus, which also fully complies with the serial I2C common protocol standard, and can realize data transmission between bus devices while realizing power supply monitoring.

3) The circuit design concept is simple and easy to implement, and can be constructed from standard gate circuits after DC logic synthesis, and the preparation process is simple.

4) The modifiability of the circuit is good, and appropriate adjustments and modifications can be made according to specific application needs.

5) The integration of high-performance PMBus interface and I2C interface is realized with the simplest structure, which occupies a small chip area and consumes less power.

Description of drawings

Fig. 1 is a flow chart of the present invention.

Fig. 2 is a system state diagram of the present invention.

Fig. 3 is a schematic diagram (the first half) of the relationship between the main signals when the two modes are switched in the present invention.

Fig. 4 is a schematic diagram of the relationship between the main signals when the two modes are switched in the present invention (the second half).

Fig. 5 is a simulation waveform diagram (first half) of switching between two modes in the present invention.

Fig. 6 is a simulation waveform diagram (second half) of switching between two modes in the present invention.

Detailed ways

A method for implementing an interface integrating a power supply monitoring bus protocol and a serial communication protocol, characterized in that:

The process enters the start 1, and then directly judges the start signal 2 to judge whether there is a start signal on the PMBus of the power monitoring bus. If there is no start signal, return to the start 1. If there is a start signal, enter the mode judgment 3, and judge that it is the PMBus communication mode. , or I2C communication mode.

If it is judged to be the PMBus communication mode of the power supply monitoring bus, judge whether there is a fault interrupt ARA4, and judge whether there is a fault interrupt ARA; if there is a fault interrupt ARA, then enter the fault response ARA response 5, send the slave address data to the PMBus bus, and complete the address After sending, enter start 1; if there is no ARA interrupt, enter power monitoring bus PMBus operation read and write judgment 6, judge whether to perform PMBus read operation, if it is PMBus read operation, further judge whether to perform 1 byte or 2 words The reading of section data, if it is the reading of 1 byte data, enter the power monitoring bus PMBus mode, read 1 byte 8, after completing the reading of 1 byte, enter the start 1, if it is 2 words To read the section data, enter the power monitoring bus PMBus mode to read 2 bytes 9, and enter the start 1 after completing the reading of 2 bytes; if it is not the power monitoring bus PMBus read operation, then judge whether to perform 1 byte or 2 bytes of data writing, if it is 1 byte of data writing, then enter the power monitoring bus PMBus mode to write 1 byte 11, after completing 1 byte writing, enter start 1, if it is 2 To write byte data, enter the power monitoring bus PMBus mode to write 2 bytes 9, and enter start 1 after completing the writing of 2 bytes.

If it is judged not to be the power supply monitoring bus PMBus communication mode, then enter the judgment of the serial communication I2C read operation 13, if it is judged as a read operation, then enter the serial communication I2C mode read operation 14 to read the data, then in the serial communication In the I2C mode, the bus read operation stop signal 15 is judged to judge whether there is a stop signal on the bus. If there is a stop signal, the data reading is completed and enters the start 1. If there is no stop signal, the data reading is kept; If it is judged as a write operation, then enter the I2C mode write operation 16 to write the data, then perform the PMBus bus write operation stop signal 17 in the I2C mode, judge whether there is a stop signal on the bus, if there is a stop signal, then write the data Complete, and enter start 1, if there is no stop signal, keep writing data.

This method is designed based on the state machine. The state machine includes ten states of IDLE, Addr, ARA & send address, COMMAND, Data_Write, Restart & Addr_R, Data_Read, I2C_Write, I2C_Read and STOP. If there is a stop signal, the state machine directly enters the start, otherwise it works normally. The state machine is always at the beginning when it is started or when there is no operation, and when the start signal is detected on the PMBus bus, the state machine enters the Addr state. At this time, when the mode_sel signal is low, it enters the PMBus transmission mode. If the mode_sel signal is high Enter the I2C transmission mode when the level is low. In the PMBus transmission mode, when alert_n is low, it means that there is an ARA interrupt, and the state machine enters the ARA & send address state. In this state, the slave address data is sent to the PMBus bus output, ARA The response completion flag port generates a high-level pulse signal to indicate that the ARA response is completed, and subsequent operations can be performed; otherwise, the state machine enters the COMMAND state, and the state machine receives a byte of serial command data on the PMBus bus and outputs it from the command output port. At the same time, a high-level pulse signal is generated at the command output enable terminal. At this time, if the restart signal is detected on the PMBus bus, it will enter the Data_Write state, otherwise it will enter the Restart & Addr_R state to read the read data address input by the PMBus bus and then transfer to Data_Read state; in the Data_Write state, if the byte or word selection signal is high level, it means a byte operation, and the data input by the PMBus bus is sent to the data output port for output, and a high level is generated at the data output enable terminal Pulse signal; if the byte or word selection signal is low, the two bytes of data input by the PMBus bus are output through the data output port in turn, and after each byte is transmitted, a data output enable terminal is generated. High level pulse signal, and enter the start; in the Data_Read state, the input port data that needs to be sent to the PMBus bus will be read, if the byte or word selection signal is high level, the data latch enables the output port to output A high-level pulse signal, and read a byte of data on the input port that needs to send data to the PMBus bus. If the byte or word selection signal is low, the data latch enable output outputs two high Level pulse signal, and is controlled by the high level pulse signal to sequentially read the two bytes of data on the input port that needs to send data to the PMBus bus, and enter the start after the data reading is completed. In the I2C transmission mode, after reading the 8bits data on the PMBus serial bus bit by bit according to the I2C protocol, the read and write operations are judged according to the lowest bit of the read data. When the lowest bit is high, the I2C enters the I2C_Read state and the data is locked. A high-level pulse signal is generated on the storage enable output terminal. At this time, the data on the input port that needs to send data to the PMBus bus is sent to the PMBus bus, and then the read data operation is repeated; if the lowest bit is low, I2C enters I2C_Write mode, the data output port outputs 8bits data on the PMBus serial bus in parallel, and the data output enable terminal generates a high-level pulse signal, and then repeats the write data operation. In the I2C_Read state and I2C_Write state, if the stop signal of the PMBus bus is detected, it will be transferred to start, waiting for a new round of monitoring or data transmission.

The circuit structure, working principle and process of the present invention will be further described below in conjunction with the accompanying drawings and examples.

Fig. 1 is a flow chart of the present invention, and flow process comprises start, start signal, PMBus mode, ARA interrupt, ARA response, PMB read operation, read 1 byte, PMBus mode reads 1 byte, PMBus mode reads 2 bytes, Write 1 byte, PMBus mode write 1 byte, PMBus mode write 2 bytes, I2C read operation, I2C mode read operation, read operation stop signal, I2C write operation and write operation stop signal seventeen steps. The purpose of the present invention is to be able to realize the data transmission of the two modes, so the way to realize it is to enter the corresponding mode, and then complete the corresponding read or write operation, and which mode to enter and which operation to perform are required according to the specific Therefore, the core of this flow chart is to make corresponding judgments based on characteristic signals, and then to complete the selection of the mode and operation type according to the process, so as to realize the integration of the two protocol interfaces.

2 is a state diagram of the present invention, including IDLE, Addr, ARA & send address, COMMAND, Data_Write, Restart & Addr_R, Data_Read, I2C_Write, I2C_Read and STOP ten states. The present invention designs a state machine with less number of states, thereby well realizing the interface method of PMBus protocol interface and I2C protocol interface integration. This interface method has two modes: PMBus mode and I2C mode. In PMBus mode, it can respond to ARA interrupt. In PMBus mode, it can monitor the power supply or read and write fixed byte data. In I2C mode, Data read and write operations with variable number of bytes can be realized. In both modes, this interface method plays the role of serial-to-parallel data conversion. Send the serial data from the PMBus to the subsequent circuit in parallel, or read the parallel data from the subsequent circuit, and then send it serially to the PMBus bus.

Fig. 3 is a schematic diagram (the first half) of the relationship between the main signals when the two modes are switched in the present invention. The figure shows a schematic diagram of the key signal for reading two bytes of data in PMBus mode before conversion in the two modes of PMBus and I2C transmission, and transmits the start signal of sda changing from high to low when scl is high, and then The bus transmits the slave address, which can be read from the figure as 8'hD0 (8'b11010000), and then the PMBus bus sends the command data 8'h10 on master_data[7:0], after 9 scl clocks, cmd_accept[7 :0] Command data 8'h10 is received, and cmd_en generates a high-level pulse; then the bus generates a restart signal, and then the bus transmits the slave address, which can be read as 8'hD1 (8'b11010001) from the figure , and then continuously read the two data 8'h20 and 8'h46 on data_accept[7:0], and generate a stop_en high-level pulse, indicating the end of the operation. Then mode_sel changes from the original low level to high level, indicating the conversion to I2C communication mode.

Fig. 4 is a schematic diagram of the relationship between the main signals when the two modes are switched in the present invention (the second half). This figure is actually a continuation of Figure 3, but due to the consideration of layout, the relationship diagram of the two modes switching is divided into Figure 3 and Figure 4. The figure shows a schematic diagram of the key signal for writing three bytes of data in the I2C mode after conversion in the two modes of PMBus and I2C transmission. Mode_sel starts from low level to high level, and the mode changes from PMBus mode at this time. In I2C mode, the start signal of sda changing from high to low when scl is high is transmitted, and then the PMBus bus transmits the slave address, which can be read from the figure as 8'hD0 (8'b11010000), and then the PMBus bus Send the command data 8′h05 on master_data[7:0], after 9 scl clocks, data accept[7:0] receives the data 8′h05, and data_en generates a high-level pulse; then the PMBus bus for the second time Send the command data 8'h17 on master_data[7:0], after 9 scl clocks, data_accept[7:0] receives the data 8'h17, and data_en generates a high level pulse; then the PMBus bus sends for the third time Command data 8′h28 on master_data[7:0], after 9 scl clocks, data_accept[7:0] receives data 8′h29, and data_en generates a high-level pulse; PMBus after three data writes A stop signal is generated, so stop_en generates a high level pulse, indicating the end of the operation.

Fig. 5 is a simulation waveform diagram (first half) of switching between two modes in the present invention. This figure is the first half of the simulation diagram of reading two bytes of data in PMBus mode and writing three bytes of data in I2C mode, that is, the waveform diagram of reading two bytes of data in PMBus mode. It can be seen from the figure that the interface circuit can switch smoothly between PMBus and I2C modes. In the figure, cmd_accept[7:0] receives the command data 8'h08 sent by the host, and after cmd_en is enabled, the host's rcv_data[7:0] continuously receives two slave data 8'h0a and 8'h0f.

Fig. 6 is a simulation waveform diagram (second half) of switching between two modes in the present invention. This figure is the second half of the simulation diagram for switching from reading two bytes of data in PMBus mode to writing three bytes of data in I2C mode, that is, the waveform diagram of writing three bytes of data in I2C mode. In fact, this simulation graph is a continuation of Figure 5, but the simulation graph is also divided into Figure 5 and Figure 6 to consider layout. It can be seen from the figure that the interface circuit can switch smoothly between PMBus and I2C modes. In the figure, master_rcv[7:0] has successfully received the data 8′h0f, and a stop_en high-level pulse is generated. Then the mode_sel signal changes from low level to high level, that is, the mode changes to I2C mode, data_accept[7:0] receives data 8'h18, 8'h20 and 8'h28 from the PMBus bus at one time, and generates The corresponding data_en enables a high-level pulse signal, and finally generates a stop_en high-level pulse, indicating the end of the transmission.

Claims (1)

1. an interface implementation method integrating power monitoring bus protocol and serial communication protocol, characterized in that: The process enters the start (1), and then directly performs the start signal (2) judgment to determine whether there is a start signal on the power monitoring bus PMBus. If there is no start signal, return to the start (1). If there is a start signal, then enter the mode judgment ( 3), judging whether it is the PMBus communication mode or the I2C communication mode, the mode is judged as follows: the state machine is always at the beginning when starting or without any operation, and when the start signal is detected on the PMBus bus, the state machine enters Addr State, at this time, when the mode_sel signal is low, it enters the PMBus transmission mode, and if the mode_sel signal is high, it enters the I2C transmission mode; If it is judged to be the PMBus communication mode of the power supply monitoring bus, then perform a fault interrupt ARA (4) judgment to determine whether there is a fault interrupt ARA; if there is a fault interrupt ARA, then enter the fault response ARA response (5), and send the slave address to the PMBus bus data, and complete the address sending and enter start (1); if there is no ARA interrupt, then enter the power monitoring bus PMBus operation read and write judgment (6), judge whether to perform PMBus read operation, if it is PMBus read operation, then further judge whether it is Read 1 byte or 2 bytes of data. If it is 1 byte of data, enter the PMBus mode of the power monitoring bus, read 1 byte (8), and complete the reading of 1 byte. After that, enter the start (1), if it is the reading of 2 bytes of data, then enter the power monitoring bus PMBus mode to read 2 bytes (9), after completing the reading of 2 bytes, enter the start (1); if If it is not a power monitoring bus PMBus read operation, it is judged whether to write 1 byte or 2 bytes of data. If it is a writing of 1 byte data, enter the power monitoring bus PMBus mode to write 1 byte ( 11), after completing the writing of 1 byte, enter the start (1), if it is the writing of 2 bytes of data, then enter the power monitoring bus PMBus mode to write 2 bytes (9), and complete the writing of 2 bytes enter after enter start(1); If it is judged not to be the power supply monitoring bus PMBus communication mode, then enter the judgment of the serial communication I2C read operation (13), if it is judged as a read operation, then enter the serial communication I2C mode read operation (14) to read the data, and then Carry out bus read operation stop signal (15) judgment under serial communication I2C mode, judge whether there is stop signal on the bus, if there is stop signal, then complete data reading, and enter start (1), if do not exist stop signal, Then keep reading of data; if it is judged as a write operation, then enter I2C mode write operation (16) to write data, then carry out PMBus bus write operation stop signal (17) judgment under I2C mode, judge whether on the bus There is a stop signal, if there is a stop signal, the data writing is completed, and enters start (1), if there is no stop signal, then the data writing is kept.

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