CN102543852A - Metal interconnection structure and manufacturing method thereof - Google Patents
Metal interconnection structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102543852A CN102543852A CN2011104466331A CN201110446633A CN102543852A CN 102543852 A CN102543852 A CN 102543852A CN 2011104466331 A CN2011104466331 A CN 2011104466331A CN 201110446633 A CN201110446633 A CN 201110446633A CN 102543852 A CN102543852 A CN 102543852A
- Authority
- CN
- China
- Prior art keywords
- interconnect structure
- metal interconnect
- dielectric layer
- metal
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a metal interconnection structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: manufacturing a metal interconnection structure on a substrate, wherein the metal interconnection structure comprises a metal wire pattern, a conductive plug and a medium layer which is filled between the metal wire pattern and the conductive plug; performing photoetching, and etching the metal interconnection structure by adopting an anisotropic dry etching method from top to bottom, and at least forming a through hole or a groove on an area which is a medium layer from top to bottom; and removing the medium layer below the metal wire pattern by adopting an isotropic removing method to form a novel metal interconnection structure, wherein the two ends of the novel metal interconnection structure are embedded into the medium layer, and other parts of the novel metal interconnection structure float in the groove or the hole. Due to the adoption of the technical scheme of the invention, certain requirements on a suspended metal interconnection structure can be met, e.g., non-matching conditions with a lens can be reduced, the light crosstalk phenomenon is reduced, and needed materials can be filled into a suspended structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of metal interconnect structure and preparation method thereof.
Background technology
The imageing sensor that comes into the market at present is divided into complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, CMOS) transducer and charge coupled cell (Charge-coupled Device, CCD) transducer.CMOS or ccd sensor have hundreds thousand of even millions of pixels usually so that light signal is converted into the signal of telecommunication, make that in imageing sensor the raw video with people or thing is converted into the signal of telecommunication.Volume is little, low in energy consumption, low cost and other advantages owing to having for CMOS or ccd image sensor, has been widely used at present in the various digital image equipment, for example: in the electronic equipments such as digital camera, DV.
Structure about cmos image sensor of the prior art; As shown in Figure 1; In Semiconductor substrate 10, be formed with photosensitive unit, for example photodiode 11,11 ', are formed with interlayer dielectric layer 12 on it; A plurality of grid structures 13 are formed in the interlayer dielectric layer 12, and this grid structure 13 for example is used to form transportation electric charge circuit.Be formed with the multiple layer metal interconnecting construction on the interlayer dielectric layer 12.Fig. 1 is example with two-layer, and this metal interconnected line structure comprises: a plurality of metal intermetallic dielectric layer IMD1, IMD2 and the metal interconnecting wires M1, the M2 that are positioned at metal intermetallic dielectric layer IMD1, IMD2.
Yet; In digital camera or DV structure; Usually need add camera lens before the imageing sensor, and along with the popularizing of electronic equipment, people to it portable new demand have been proposed; This just makes digital camera or video camera need reduce volume or thickness, and this causes the distance of camera lens and imageing sensor to have to more and more nearer.Before the reducing of this distance caused can through which floor eyeglass change light path with reach each sensor unit at utmost the method for vertical incidence can't use, have to adopt the individual layer eyeglass of adjustment weak effect to be realized.In other words, in the present miniaturized electric subset, the normal of the light after incident ray reflects via camera lens and the photosensitive unit of imageing sensor forms an angle; As shown in Figure 1; The light that is positioned at zone line impinges perpendicularly on photosensitive unit, and for example on the photodiode 11, the light oblique illumination that is positioned at fringe region is to the photodiode 11 ' of these photodiode 11 close regions; And the closer to fringe region, the inclined degree of incident ray is big more.The light of this non-normal incidence can cause the optical crosstalk of photodiode, and it is serious more to tilt, and crosstalk phenomenon is obvious more.Photodiode 11 among Fig. 1, a plurality of photodiodes have been omitted between 11 '.In addition, for the cmos image sensor of colour, optical crosstalk can produce the colour mixture problem, influences image quality.
To the demand, the conventional images transducer among Fig. 1 obviously can not satisfy.The inventor analyzes the problems referred to above, proposes a kind of manufacture method of new metal interconnect structure and the metal interconnect structure of formation, solving the problems referred to above of imageing sensor, but is not limited to the problems referred to above.
Summary of the invention
The problem that the present invention solves is to propose a kind of manufacture method of new metal interconnect structure and the metal interconnect structure of formation, solving the optical crosstalk problem of imageing sensor, but is not limited to this problem.
For addressing the above problem, the present invention provides a kind of manufacture method of metal interconnect structure, comprising:
In substrate, make metal interconnect structure, said metal interconnect structure comprises that one deck metal line pattern, conductive plunger reach the dielectric layer of filling therebetween at least;
After the photoetching, adopting the said metal interconnect structure of anisotropic dry etching from top to down etching, is the zone formation through hole or the groove of dielectric layer from top to bottom at least;
Adopt isotropism to remove method the dielectric layer under the metal line pattern is removed the new metal interconnect structure of formation, this new metal interconnect structure is embedded in the dielectric layer except two ends, and other part is floated in groove or hole.
Alternatively, form in the through hole step in the zone that is dielectric layer from top to bottom at least, the mask plate pattern that photoetching is used is at least one hole or banded structure, and said hole or banded structure are aligned in and are the zone of dielectric layer from top to bottom.
Alternatively; At least form in the through hole step in the zone that is dielectric layer from top to bottom; The mask plate pattern that photoetching is used be at least one hole or banded structure, and said hole or banded structure are aligned in from top to bottom to the zone of dielectric layer and are the zone of metal line pattern from top to bottom, in the said metal interconnect structure step of from top to down etching; When running into metal line pattern, etching stopping is on the metal line pattern surface.
Alternatively, with being that dry etching is removed in the removal of the dielectric layer under the metal line pattern step, dry etching gas is isotropic etching gas.
Alternatively, the dielectric layer under the metal line pattern is removed be the wet method removal in the step.
Alternatively, said dielectric layer is a silicon dioxide, and said isotropic etching gas is HF acid gas phase steam.
Alternatively, said dielectric layer is silicon dioxide or silicon nitride, adopts HF acid or HF acid cushioning liquid to remove the silicon dioxide as dielectric layer, adopts phosphoric acid to remove the silicon nitride as dielectric layer.
Alternatively, it is characterized in that said substrate is a Semiconductor substrate, behind the said metal interconnect structure of employing anisotropic dry etching from top to down etching, continue the said Semiconductor substrate of etching and when this Semiconductor substrate is penetrated, stop.
Alternatively; It is characterized in that; Said substrate is a Semiconductor substrate, adopt the said metal interconnect structure of anisotropic dry etching from top to down etching after, carry out photoetching at the said Semiconductor substrate back side, this Semiconductor substrate of etching stops when connecting with the metal interconnect structure of floating.
Alternatively, also carry out the step of the crooked said metal interconnect structure of floating behind the metal interconnect structure that formation is floated.
Alternatively, also carry out after the crooked said metal interconnect structure step of floating filling the insulation macromolecular material, solidify the back and form curved surface metal interconnect structure with insulation macromolecular material filler said metal interconnected of floating.
Alternatively, said insulation macromolecular material is a polyimides, and baking is adopted in said curing.
Alternatively, said substrate is a Semiconductor substrate, also is formed with a plurality of MOS transistors and photodiode on the said Semiconductor substrate, and said metal interconnect structure one deck metal line pattern at least is the interconnection line between said a plurality of MOS transistor and photodiode.
Alternatively, said making metal interconnect structure step comprises:
Substrate is provided;
Deposit first dielectric layer in said substrate;
Utilize lithographic definition to go out through-hole pattern;
The deposit conductive material is to fill said through hole;
Adopt CMP, remove the outer conductive material of through hole;
Deposit ground floor metal;
Utilize chemical wet etching to define the ground floor metal line pattern;
Deposit top layer dielectric layer;
The said top layer dielectric layer of CMP.
Alternatively, also carry out repeatedly dielectric layer deposited to the step that forms metal line pattern after defining ground floor metal line pattern step,, carry out deposit top layer dielectric layer step afterwards to form the interconnection structure of a plurality of metal levels.
In addition, the present invention also provides a kind of metal interconnect structure, and said metal interconnect structure is embedded in the dielectric layer except two ends, and other part is floated in groove or hole.
Alternatively, said dielectric layer is silicon nitride or silicon dioxide.
Alternatively, said metal interconnect structure comprises metal line pattern and conductive plunger, and the material of said metal line pattern is copper or aluminium, and said conductive plunger material is a tungsten.
Compared with prior art, the present invention has the following advantages:
At first in substrate, make metal interconnect structure, this metal interconnect structure comprises metal line pattern, conductive plunger and the dielectric layer of filling therebetween; Then, after the photoetching, adopting the said metal interconnect structure of anisotropic dry etching from top to down etching, is the zone formation through hole or the groove of dielectric layer from top to bottom at least; Adopt isotropism to remove method at last the dielectric layer under the metal line pattern is removed the new metal interconnect structure of formation, this new metal interconnect structure is embedded in the dielectric layer except two ends, and other part is floated in groove or hole.The structure that said method forms has satisfied some demands to unsettled metal interconnect structure, for example forms the imageing sensor that matees with lens shape, reduces cross-interference issue; In addition; In order to make the layer capacitance between the metal reduce to improve the performance of chip; Can improve the higher problem of K value of dielectric material in the traditional standard technology through in the deep trouth of unsettled metal wire provided by the invention, filling the dielectric material of low k, can also be in deep trouth at unsettled metal wire provided by the invention the filling flexible material; Make the array-type flexible pressure sensor; This pressure sensor adopts any 2 flexibilities or gentle/distribution of contact-making surface surface action power just to detect, and not only has the advantage of generic array formula transducer, also has good pliability; Can free bend even folding, can be easily the part of complex surface shape be detected.
Further; After the photoetching; Adopt the said metal interconnect structure of anisotropic dry etching from top to down etching that two kinds of methods are arranged; A kind of is to be the formation hole, zone or the groove of dielectric layer earlier from top to bottom, removes the dielectric layer of clad metal line pattern then through this hole or groove, and the dielectric layer of this clad metal line pattern comprises the dielectric layer under the metal line pattern; Corresponding method is that the mask plate pattern that photoetching is used is at least one hole or banded structure, and said hole or banded structure are aligned in and are the zone of dielectric layer from top to bottom;
Another kind of for all carrying out the anisotropic etching for the zone of metal line pattern from top to bottom for dielectric layer reaches from top to bottom; Still can form hole or groove for the zone of dielectric layer from top to bottom; When running into metal line pattern in the etching process from top to bottom; Etching stopping is removed the dielectric layer under the metal line pattern at last on the surface of metal line pattern; Corresponding method is that the mask plate pattern that photoetching is used is at least one hole or banded structure; Said hole or banded structure be aligned in from top to bottom for the zone of dielectric layer be the zone of metal line pattern from top to bottom; In the said metal interconnect structure step of from top to down etching; When running into metal line pattern, etching stopping is on the metal line pattern surface;
Further, this substrate is a Semiconductor substrate, behind the said metal interconnect structure of employing anisotropic dry etching from top to down etching, continues the said Semiconductor substrate of etching and when this Semiconductor substrate is penetrated, stops; The metal interconnect structure of above-mentioned formation is unsettled in through hole; The structure of crooked above-mentioned formation can be so that the shape of imageing sensor form fit camera lens; Increased the light of the photosensitive unit that impinges perpendicularly on this transducer, thereby, the image quality of imageing sensor increased;
Further; This substrate is a Semiconductor substrate; After adopting the said metal interconnect structure of anisotropic dry etching from top to down etching, carry out photoetching at the said Semiconductor substrate back side, this Semiconductor substrate of etching stops when connecting with the metal interconnect structure of floating; This programme provides another kind of metal interconnect structure unsettled in through hole;
Further, in deep trouth or through hole, fill the insulation macromolecular material, solidify the back and form curved surface metal interconnect structure, improved metal interconnect structure performance in use with insulation macromolecular material filler;
Further, said substrate is a Semiconductor substrate, also is formed with a plurality of MOS transistors and photodiode on the said Semiconductor substrate, and said metal interconnect structure one deck metal line pattern at least is the interconnection line between said a plurality of MOS transistor and photodiode; This programme can be grafted directly in the existing imageing sensor manufacture craft, and is strong with the conventional semiconductor processing compatibility.
Description of drawings
Fig. 1 is the structural representation of cmos image sensor of the prior art;
Fig. 2 is the flow chart of the manufacture method of the new metal interconnect structure that provides of present embodiment one;
Fig. 3 to Fig. 6 is the intermediate structure sketch map of metal interconnect structure in manufacturing process of three metal levels;
Fig. 7 is that the metal interconnect structure of three metal levels is made the vertical view that finishes;
Fig. 8 be among Fig. 7 structure along the cutaway view of A-A straight line;
Fig. 9 be among Fig. 7 structure along the cutaway view of B-B straight line;
Figure 10 is that structure adopts the mask plate among the embodiment one to carry out the structural representation after lithography step is accomplished among Fig. 7;
Figure 11 be among Figure 10 structure from top to bottom etching finish the back along the cutaway view of B-B straight line;
Figure 12 be among Figure 10 structure from top to bottom etching finish the back along the cutaway view of A-A straight line;
Figure 13 be among Figure 10 structure from top to bottom etching finish and remove under the metal line pattern behind the dielectric layer cutaway view along the B-B straight line;
Figure 14 be among Figure 10 structure from top to bottom etching finish and remove under the metal line pattern behind the dielectric layer cutaway view along the A-A straight line;
Figure 15 is that structured substrate is carved the cutaway view after wearing among Figure 14;
Figure 16 is the structural representation of the cmos image sensor that provides of present embodiment one;
Figure 17 is that structure adopts the mask plate among the embodiment two to carry out the structural representation after lithography step is accomplished among Fig. 7;
Figure 18 be among Figure 17 structure from top to bottom etching finish the back along the cutaway view of B-B straight line.
Embodiment
The manufacture method of metal interconnect structure provided by the invention comprises: at first in substrate, make metal interconnect structure, this metal interconnect structure comprises metal line pattern, conductive plunger and the dielectric layer of filling therebetween; Then, after the photoetching, adopting the said metal interconnect structure of anisotropic dry etching from top to down etching, is the zone formation through hole or the groove of dielectric layer from top to bottom at least; Adopt isotropism to remove method at last the dielectric layer under the metal line pattern is removed the new metal interconnect structure of formation, this new metal interconnect structure is embedded in the dielectric layer except two ends, and other part is floated in groove or hole.Such structure has satisfied some demands to unsettled metal interconnect structure.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing two embodiments of the present invention done detailed explanation.
Embodiment one
Following image taking sensor is an example, introduces metal interconnect structure wherein and preparation method thereof in detail.The flow chart of the manufacture method of the metal interconnect structure that Fig. 2 provides for present embodiment one.Fig. 3 to Fig. 6 is the intermediate structure sketch map of metal interconnect structure in manufacturing process.Fig. 7 makes the vertical view finish for metal interconnect structure, and Fig. 8, Fig. 9 are respectively among Fig. 7 the cutaway view along A-A straight line, B-B straight line.
In conjunction with Fig. 2, Fig. 8 and Fig. 9, at first carry out S11, on Semiconductor substrate 20, make metal interconnect structure 27, said metal interconnect structure 27 comprises metal line pattern, conductive plunger and the dielectric layer of filling therebetween.
Particularly, the combining image transducer, this step may further comprise the steps S110-S118 in the process of implementation.
At first carry out S110, Semiconductor substrate 20 is provided; Also be formed with a plurality of MOS transistors 23 and photodiode 21 on the said Semiconductor substrate 20, the cross section structure sketch map of this Semiconductor substrate is as shown in Figure 3, has wherein shown 3 photodiodes 21 and 3 MOS transistors 23.The material of this Semiconductor substrate 20 can be silicon, germanium, silicon-germanium etc., but is not limited to above-mentioned material.In addition, in other embodiments, also be not limited to Semiconductor substrate, as long as can form the substrate of metal interconnecting layer on it.
Then carry out S111, deposit first dielectric layer 22 on said Semiconductor substrate 20, it is as shown in Figure 4 to form the structural section sketch map.First dielectric layer 22 can be existing dielectric material, for example silicon dioxide, silicon nitride etc., but be not limited to above-mentioned material.
Carry out S112 then, utilize lithographic definition to go out through hole (via) 24 patterns, it is as shown in Figure 5 to form the structural section sketch map after the etching.This through hole 24 can be communicated with the metal interconnect structure that forms thereafter with MOS transistor 23.Photoetching in this step, etching technics can adopt existing processes.
Then carry out S113, the deposit conductive material is to fill said through hole 24.This depositing technics can be sputter or physical vapor deposition (PVD).The filling purpose of conductive material is in through hole 24, to form conductive plunger, and therefore, conductive material can be selected copper, tungsten etc., but is not limited to above-mentioned metal.
Carry out S114 then, CMP removes the conductive material outside the through hole 24.CMP is a cmp, can adopt existing processes.
Then carry out S115, deposit ground floor metal 25, it is as shown in Figure 6 to form the structural section sketch map.Ground floor metal 25 materials can be copper, aluminium etc., but are not limited to the above-mentioned material of enumerating.
Carry out S116, utilize chemical wet etching to define the ground floor metal line pattern.Photoetching in this step, etching technics can adopt existing processes.
The ground floor metal line pattern that this step forms can be the interconnection line between a plurality of MOS transistors and photodiode.
Afterwards, can also be according to the imageing sensor needs, execution in step S111-S116 many times is to form the interconnection structure of a plurality of metal levels.In the present embodiment one, carry out twice again, form metal interconnect structure 27 with three metal levels.With reference to Fig. 8 and shown in Figure 9; Work the conductive plunger that is electrically connected, the dielectric layer between its said structure between the metal interconnect structure 27 of above-mentioned three metal levels comprises the three-layer metal line pattern, play electrical connection between every layer conductive plunger and ground floor metal line pattern and the Semiconductor substrate 20.
Afterwards, carry out S117, deposit top layer dielectric layer 26 is still with reference to Fig. 8 and shown in Figure 9.This top layer dielectric layer 26 can be identical or different with first dielectric layer, 22 materials.
Carry out S118, it is as shown in Figure 7 that the metal interconnect structure 27 of 26, three metal levels of the said top layer dielectric layer of CMP is made the vertical view that finishes, along cutaway view such as Fig. 8, shown in Figure 9 of A-A straight line, B-B straight line.
Then carry out S12; Make the alignment mark in mask plate pattern and the Semiconductor substrate 20; The mask plate pattern is at least one hole or banded structure, said hole or banded structure be aligned in from top to bottom for the zone of dielectric layer be the zone of metal line pattern from top to bottom; After the photoetching, adopt the metal interconnect structure 27 of said three metal levels of anisotropic dry etching from top to down etching; When top-down structure was dielectric layer, said dielectric layer was etched and forms through hole or groove; When running into metal line pattern in the etching process from top to bottom, etching stopping is on the metal line pattern surface.
In the present embodiment one, the mask plate pattern is a banded structure, this mask plate design transfer to the photoresist after, form banded exposure area 28, its vertical view is shown in figure 10.
With this photoresist pattern is mask, in the from top to down etching process, can run into dielectric layer, also can run into metal line pattern.When running into dielectric layer, said dielectric layer is etched and forms through hole or groove, and when running into metal line pattern, etching stopping is on the metal line pattern surface.
In the practical implementation process, anisotropic dry etching gas is CF
4, CHF
3, C
2F
6, C
3F
8, C
4F
8In at least a.
In the practical implementation process, the surface that can etch into Semiconductor substrate 20 stops to form the metal interconnect structure 27 ' of three new metal levels, like Figure 11 and shown in Figure 12.
In addition, above-mentioned etching process from top to bottom can selective etching not stop behind the surface of Semiconductor substrate 20 yet, continues the said Semiconductor substrate 20 of etching and when this Semiconductor substrate 20 is penetrated, stops.
Except from Semiconductor substrate 20 positive etchings; Can also be behind the said metal interconnect structure 27 ' of from top to down etching; Carry out photoetching, this Semiconductor substrate 20 of etching from the back side of said Semiconductor substrate 20 and when connecting, stop, carrying out photoetching overleaf, etching technics is easier to control with the metal interconnect structure of floating 27 '.
Carry out S13 then, adopt isotropism to remove method the dielectric layer under the metal line pattern is removed the new metal interconnect structure 27 of formation ", this new metal interconnect structure 27 " except two ends are embedded in the dielectric layer, other part is floated in groove or hole.
In the practical implementation process, this step can be removed according to need, or claims that the dielectric layer material of emptying is different, selects dry etching or wet method to remove.
Different with step S12 is that in the practical implementation process, when being silicon dioxide, isotropic etching can adopt dry etching to each dielectric layer (comprising first dielectric layer 22 and top layer dielectric layer 26), also can adopt wet method to remove.Dry etching gas can be selected HF acid gas phase steam.Wet method is removed and can be adopted HF acid or HF acid cushioning liquid.
Each dielectric layer (comprising first dielectric layer 22 and top layer dielectric layer 26) is when being silicon nitride, and wet method is removed and adopted phosphoric acid.
Figure 13, Figure 14 are respectively structure among Figure 10 cutaway view along B-B straight line, A-A straight line after step S12 accomplishes.On Semiconductor substrate 20, to form array structure is example; Pass through metal interconnect structure 27 between the part adjacent cells " be communicated with this structure 27 " except two ends are embedded in the dielectric layer in the unit, remainder is unsettled in groove or hole; Such structure has many application; For example be applied to existing imageing sensor, can be crooked to alleviate and the camera lens situation that do not match, reduce the optical crosstalk phenomenon.
In addition, among the step S12, etching process can selective etching can not stop behind the surface of Semiconductor substrate 20 yet from top to bottom; Continuing the said Semiconductor substrate 20 of etching stops when this Semiconductor substrate 20 is penetrated; Execution in step S13 afterwards, the metal interconnect structure 27 of formation ", schematic cross-section is shown in figure 15; this structure 27 " unsettled in through hole or the groove that runs through up and down, crooked this structure can be so that the shape of imageing sensor form fit camera lens.
Except from Semiconductor substrate 20 positive etchings; Can also be behind the said metal interconnect structure of from top to down etching; Carry out at the back side of said Semiconductor substrate 20 photoetching, this Semiconductor substrate 20 of etching until with the metal interconnect structure of floating 27 " stop when connecting, carry out photoetching overleaf, etching technics is easier to control.
So far, the metal interconnect structure of floating 27 " form.
Need to prove; With reference to shown in Figure 7, the metal interconnect structure 27 that leans between each unit in the horizontal direction that provides in the present embodiment one connects, in other embodiments; Also can there be metal interconnect structure to connect in vertical direction between each unit, forms " well " font structure.In addition; Shown in Fig. 7 is a metal interconnect structure 27; This metal interconnect structure 27 is the interconnection structure that three metal interlevels lean on conductive plunger to connect, and among other embodiment, a plurality of these parallel three metal levels or the metal interconnect structure of a plurality of metal levels can be set also.
In the practical implementation process, form the metal interconnect structure 27 float " after also carry out the step of the crooked said metal interconnect structure of floating, form the metal interconnect structure 27 ' shown in Figure 16 ".This metal interconnect structure 27 ' " when being applied on the cmos image sensor, with camera lens coupling, the light that incides the photosensitive unit of this transducer is vertical incidence basically, has reduced the optical crosstalk phenomenon, thereby, increased the image quality of imageing sensor.
The crooked said metal interconnect structure of floating 27 " can also be as required after the step; at the said metal interconnect structure of floating 27 " between fill the insulation macromolecular material, solidify the back and form curved surface metal interconnect structure 27 ' with insulation macromolecular material filler ".In the present embodiment one; Be to improve metal interconnect structure 27 ' " in use performance; the crooked said metal interconnect structure of floating 27 " can also in deep trouth or through hole, fill the insulation macromolecular material before or after the step, solidify the back and form curved surface metal interconnect structure with the macromolecular material filler that insulate.
In the practical implementation process, this insulation macromolecular material can be polyimides, and baking is adopted in said curing.
Carry out each step of foregoing description; Formed a kind of metal interconnect structure; Said metal interconnect structure such as Figure 13, Figure 14, Figure 15 and shown in Figure 16; This structure is the metal interconnect structure of floating, and except two ends are embedded in the dielectric layer, remainder can be floated in deep trouth or the through hole according to different process.This metal interconnect structure comprises metal line pattern and conductive plunger, and the material of said metal line pattern is copper or aluminium, and said conductive plunger material is a tungsten.The dielectric layer of two ends embedding is silicon nitride or silicon dioxide.
Embodiment two
In step S12 implementation; Hole in the mask plate pattern that in the photoetching process of embodiment one, provides or banded structure are aligned in from top to bottom for the zone of dielectric layer and from top to bottom for the zone of metal line pattern; Hole in the mask plate pattern that provides in the photoetching process of present embodiment two or banded structure only are aligned in and are the zone of dielectric layer from top to bottom; This mask plate design transfer to the photoresist after, form banded exposure area 28 ', its vertical view is shown in figure 17.With this photoresist pattern is mask, and in etching process from top to bottom, what run into has only dielectric layer, and said dielectric layer is etched and forms through hole or groove, and it is shown in figure 18 along the cutaway view of B-B straight line to form structure.The parameter that adopts in this etching process is identical with embodiment one.
Afterwards, carry out S13, adopt isotropism to remove method the dielectric layer under the metal line pattern is removed the new metal interconnect structure 27 of formation ", this new metal interconnect structure 27 " except two ends are embedded in the dielectric layer, other part is floated in groove or hole.
This step in the process of implementation, the technology of removing the dielectric layer under the metal line pattern is identical with embodiment one.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art are not breaking away under the technical scheme scope situation of the present invention, and all the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (18)
1. the manufacture method of a metal interconnect structure is characterized in that, comprising:
In substrate, make metal interconnect structure, said metal interconnect structure comprises that one deck metal line pattern, conductive plunger reach the dielectric layer of filling therebetween at least;
After the photoetching, adopting the said metal interconnect structure of anisotropic dry etching from top to down etching, is the zone formation through hole or the groove of dielectric layer from top to bottom at least;
Adopt isotropism to remove method the dielectric layer under the metal line pattern is removed the new metal interconnect structure of formation, this new metal interconnect structure is embedded in the dielectric layer except two ends, and other part is floated in groove or hole.
2. the manufacture method of metal interconnect structure according to claim 1; It is characterized in that; At least form in the through hole step in the zone that is dielectric layer from top to bottom; The mask plate pattern that photoetching is used is at least one hole or banded structure, and said hole or banded structure are aligned in and are the zone of dielectric layer from top to bottom.
3. the manufacture method of metal interconnect structure according to claim 1; It is characterized in that form in the through hole step in the zone that is dielectric layer from top to bottom at least, the mask plate pattern that photoetching is used is at least one hole or banded structure; Said hole or banded structure be aligned in from top to bottom for the zone of dielectric layer be the zone of metal line pattern from top to bottom; In the said metal interconnect structure step of from top to down etching, when running into metal line pattern, etching stopping is on the metal line pattern surface.
4. according to the manufacture method of any described metal interconnect structure in the claim 1 to 3, it is characterized in that the dielectric layer under the metal line pattern is removed in the step removed for dry etching, dry etching gas is isotropic etching gas.
5. according to the manufacture method of any described metal interconnect structure in the claim 1 to 3, it is characterized in that, the dielectric layer under the metal line pattern is removed in the step removed for wet method.
6. the manufacture method of metal interconnect structure according to claim 4 is characterized in that, said dielectric layer is a silicon dioxide, and said isotropic etching gas is HF acid gas phase steam.
7. the manufacture method of metal interconnect structure according to claim 5; It is characterized in that; Said dielectric layer is silicon dioxide or silicon nitride, adopts HF acid or HF acid cushioning liquid to remove the silicon dioxide as dielectric layer, adopts phosphoric acid to remove the silicon nitride as dielectric layer.
8. according to the manufacture method of any described metal interconnect structure in the claim 1 to 3; It is characterized in that; Said substrate is a Semiconductor substrate; After adopting the said metal interconnect structure of anisotropic dry etching from top to down etching, continue the said Semiconductor substrate of etching and when this Semiconductor substrate is penetrated, stop.
9. according to the manufacture method of any described metal interconnect structure in the claim 1 to 3; It is characterized in that; Said substrate is a Semiconductor substrate; After adopting the said metal interconnect structure of anisotropic dry etching from top to down etching, carry out photoetching at the said Semiconductor substrate back side, this Semiconductor substrate of etching stops when connecting with the metal interconnect structure of floating.
10. the manufacture method of metal interconnect structure according to claim 9 is characterized in that, also carries out the step of the crooked said metal interconnect structure of floating behind the metal interconnect structure that formation is floated.
11. the manufacture method of metal interconnect structure according to claim 10; It is characterized in that; Also carry out after the crooked said metal interconnect structure step of floating filling the insulation macromolecular material, solidify the back and form curved surface metal interconnect structure with insulation macromolecular material filler said metal interconnected of floating.
12. the manufacture method of metal interconnect structure according to claim 11 is characterized in that, said insulation macromolecular material is a polyimides, and baking is adopted in said curing.
13. manufacture method according to any described metal interconnect structure in the claim 1 to 3; It is characterized in that; Said substrate is a Semiconductor substrate; Also be formed with a plurality of MOS transistors and photodiode on the said Semiconductor substrate, said metal interconnect structure one deck metal line pattern at least is the interconnection line between said a plurality of MOS transistor and photodiode.
14. the manufacture method according to any described metal interconnect structure in the claim 1 to 3 is characterized in that, said making metal interconnect structure step comprises:
Substrate is provided;
Deposit first dielectric layer in said substrate;
Utilize lithographic definition to go out through-hole pattern;
The deposit conductive material is to fill said through hole;
Adopt CMP, remove the outer conductive material of through hole;
Deposit ground floor metal;
Utilize chemical wet etching to define the ground floor metal line pattern;
Deposit top layer dielectric layer;
The said top layer dielectric layer of CMP.
15. the manufacture method of metal interconnect structure according to claim 14; It is characterized in that; Also carry out repeatedly dielectric layer deposited to the step that forms metal line pattern after defining ground floor metal line pattern step; To form the interconnection structure of a plurality of metal levels, carry out deposit top layer dielectric layer step afterwards.
16. a metal interconnect structure is characterized in that, said metal interconnect structure is embedded in the dielectric layer except two ends, and other part is floated in groove or hole.
17. metal interconnect structure according to claim 16 is characterized in that, said dielectric layer is silicon nitride or silicon dioxide.
18. metal interconnect structure according to claim 16 is characterized in that, said metal interconnect structure comprises metal line pattern and conductive plunger, and the material of said metal line pattern is copper or aluminium, and said conductive plunger material is a tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110446633.1A CN102543852B (en) | 2011-12-27 | 2011-12-27 | Metal interconnection structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110446633.1A CN102543852B (en) | 2011-12-27 | 2011-12-27 | Metal interconnection structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102543852A true CN102543852A (en) | 2012-07-04 |
| CN102543852B CN102543852B (en) | 2014-07-16 |
Family
ID=46350396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110446633.1A Active CN102543852B (en) | 2011-12-27 | 2011-12-27 | Metal interconnection structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102543852B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261623A (en) * | 2014-07-16 | 2016-01-20 | 中芯国际集成电路制造(上海)有限公司 | Chip and preparation method thereof and image sensor including chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020160563A1 (en) * | 2000-03-14 | 2002-10-31 | International Business Machines Corporation | Practical air dielectric interconnections by post-processing standard CMOS wafers |
| CN1795552A (en) * | 2003-05-22 | 2006-06-28 | 国际商业机器公司 | Method for manufacturing a multi-level interconnect structure |
-
2011
- 2011-12-27 CN CN201110446633.1A patent/CN102543852B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020160563A1 (en) * | 2000-03-14 | 2002-10-31 | International Business Machines Corporation | Practical air dielectric interconnections by post-processing standard CMOS wafers |
| CN1795552A (en) * | 2003-05-22 | 2006-06-28 | 国际商业机器公司 | Method for manufacturing a multi-level interconnect structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105261623A (en) * | 2014-07-16 | 2016-01-20 | 中芯国际集成电路制造(上海)有限公司 | Chip and preparation method thereof and image sensor including chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102543852B (en) | 2014-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4427949B2 (en) | Solid-state imaging device and manufacturing method thereof | |
| CN105474625B (en) | Integrated camera model and its manufacturing method | |
| US7233037B2 (en) | Solid state imaging device and method of manufacturing the same | |
| CN107039468A (en) | CIS and preparation method thereof | |
| JP2008066732A (en) | Cmos image sensor, and method for manufacturing the same | |
| US8679937B2 (en) | Method for fabricating a capacitor and capacitor structure thereof | |
| KR100905596B1 (en) | Image Sensor and Method for Manufacturing Thereof | |
| CN107946332B (en) | Semiconductor structure, CMOS image sensor and preparation method thereof | |
| KR20200135707A (en) | Image sensor with pad structure | |
| CN104576662A (en) | Stackable CMOS (complementary metal oxide semiconductors) sensor with high quantum conversion efficiency and preparation method of stackable CMOS sensor | |
| CN102891158B (en) | A kind of manufacture method of back-illuminated cmos image sensors | |
| CN102543852B (en) | Metal interconnection structure and manufacturing method thereof | |
| CN103022068B (en) | CMOS (complementary metal oxide semiconductor) image sensor and method for manufacturing same | |
| CN104733489A (en) | Organic image sensor and forming method thereof | |
| US20080157140A1 (en) | Image sensor and fabricating method thereof | |
| US20120018831A1 (en) | Light pipe fabrication with improved sensitivity | |
| KR20090039015A (en) | Method for fabricating of cmos image sensor | |
| CN102891159B (en) | The pixel structure and its manufacturing method of CMOS image sensor | |
| US20080054387A1 (en) | Image Sensor and Method for Manufacturing the Same | |
| TWI701820B (en) | Color filter device and forming method thereof | |
| CN202111094U (en) | Cmos image sensor | |
| CN106601759B (en) | Semiconductor device, manufacturing method thereof and electronic device | |
| US20230215891A1 (en) | Image sensor integrated chip and method for forming the same | |
| CN102231381A (en) | Complementary metal oxide semiconductor (CMOS) image sensor and forming method | |
| CN203179889U (en) | Cmos image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |