CN102543825B - Manufacturing method of semiconductor channel and double channels and structure for isolating elements - Google Patents
Manufacturing method of semiconductor channel and double channels and structure for isolating elements Download PDFInfo
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- CN102543825B CN102543825B CN201010617621.6A CN201010617621A CN102543825B CN 102543825 B CN102543825 B CN 102543825B CN 201010617621 A CN201010617621 A CN 201010617621A CN 102543825 B CN102543825 B CN 102543825B
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Abstract
The invention relates to a manufacturing method of a semiconductor channel and double channels and a structure for isolating elements. The structure for isolating elements is arranged in a substrate provided with a peripheral region and an array region, and comprises a first isolating structure and a second isolating structure, wherein the first isolating structure is provided with a section consisting of at least three steps and is positioned in the substrate in the peripheral region; and the second isolating structure is provided with a section consisting of at least two steps and is positioned in the substrate in the array region.
Description
Technical field
The present invention relates to a kind of semiconductor structure and manufacture method thereof, particularly relate to a kind of two isolation structures or two irrigation canals and ditches structure and manufacture method thereof with different depth.
Background technology
In integrated circuit flourish today, element downsizing and the productive set trend that is inevitable, the important topic of Ye Shi all circles develop actively.Dwindle gradually when component size, integration improves gradually, and interelement isolation structure also must dwindle, and therefore the degree of difficulty of element separation technology also increases gradually.
With current isolation technology, due to shallow slot isolation structure (shallow trench isolation, STI) have advantages of that easy adjustment is big or small, and can avoid the shortcoming that in traditional area oxidation (LOCOS) method isolation technology, beak corrodes, therefore, it,, for inferior half micron or following metal oxide semiconductor processing, is a kind of comparatively desirable isolation technology.
In addition,, in response to the different application of array area and the surrounding zone of memory cell, the degree of depth of its needed isolation structure is not identical yet.Generally speaking, the degree of depth of the shallow slot isolation structure of surrounding zone can be much larger than the degree of depth of the shallow slot isolation structure of array area.Therefore,, in the time that this kind of making has two isolation structure of different depth, conventionally need at least twice lithography process to complete the demand, complex process and Expenses Cost.
As can be seen here, in above-mentioned existing memory cell, there is the manufacture method of two isolation structures of different depth and isolation structure at manufacture method, product structure and use, obviously still having inconvenience and defect, and be urgently further improved.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but have no for a long time applicable design is completed by development always, and conventional method and product do not have appropriate method and structure to address the above problem, this is obviously the problem that the anxious wish of relevant dealer solves.Therefore how to found the manufacture method of a kind of new semiconductor irrigation canals and ditches and two irrigation canals and ditches and the structure in order to isolated component, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
Main purpose of the present invention is, overcome the manufacture method of two isolation structures in existing memory cell with different depth and the defect that isolation structure exists, and a kind of new semiconductor irrigation canals and ditches and the manufacture method of two irrigation canals and ditches and the structure in order to isolated component be provided, technical problem to be solved is to make it only need one lithography process to make two isolation structures with different depth, technique is simple and save cost, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The manufacture method of a kind of semiconductor irrigation canals and ditches that propose according to the present invention.First, provide substrate, substrate has surrounding zone and array area.Then, form cover curtain layer in substrate, cover curtain layer has the first opening of the substrate that exposes surrounding zone to the open air and exposes the second opening of the substrate of array area to the open air.Then, form the first clearance wall at the sidewall of the first opening.Afterwards, take cover curtain layer and the first clearance wall as cover curtain, in the substrate of surrounding zone, form depression.Then, form the second clearance wall at the sidewall of the second opening, and remove part the first clearance wall to expose the drift angle of depression.Next,, take cover curtain layer, the first clearance wall and the second clearance wall as cover curtain, remove part substrate, to form the first irrigation canals and ditches and form the second irrigation canals and ditches in the substrate of surrounding zone in the substrate of array area.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of aforesaid semiconductor irrigation canals and ditches, the first wherein said opening is greater than the second opening.
The manufacture method of aforesaid semiconductor irrigation canals and ditches, wherein comprises in the step that the sidewall of above-mentioned the first opening forms the first clearance wall: in substrate, form dielectric materials layer, the thickness of dielectric materials layer is greater than a half width of the second opening; And remove part dielectric materials layer, until expose the surface of cover curtain layer, wherein remaining dielectric materials layer forms the first clearance wall and fills up the second opening at the sidewall of the first opening.
The manufacture method of aforesaid semiconductor irrigation canals and ditches, is more included in the first irrigation canals and ditches and the second irrigation canals and ditches and inserts the first dielectric layer, and wherein dielectric materials layer is identical with the material of the first dielectric layer.
The manufacture method of aforesaid semiconductor irrigation canals and ditches, wherein, after the step that forms above-mentioned the first irrigation canals and ditches and the second irrigation canals and ditches and before inserting the step of the first dielectric layer, method of the present invention more comprises: remove the first clearance wall and the second clearance wall; And form lining on the surface of the first irrigation canals and ditches and the second irrigation canals and ditches.
The manufacture method of aforesaid semiconductor irrigation canals and ditches, the surface of the substrate that the first wherein said opening and the second opening expose to the open air is lower than the bottom surface of cover curtain layer.
The manufacture method of aforesaid semiconductor irrigation canals and ditches, the first wherein said irrigation canals and ditches have the section at least three rank, and the second irrigation canals and ditches have at least section of second order.
The manufacture method of aforesaid semiconductor irrigation canals and ditches, the degree of depth of the first wherein said irrigation canals and ditches is 2～3 times of the degree of depth of the second irrigation canals and ditches.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The manufacture method of a kind of two irrigation canals and ditches with different depth that propose according to the present invention.First, provide substrate, substrate has the firstth district and Second Region.Then, form cover curtain layer in substrate, cover curtain layer has the first opening of the substrate that exposes the firstth district to the open air and exposes the second opening of the substrate of Second Region to the open air.Then, form the first clearance wall and in the second opening, fill up the first dielectric layer at the sidewall of the first opening.In covering act substrate that is the firstth district, form depression take cover curtain layer and the first clearance wall.Afterwards, remove part of first dielectric layer, to form the second clearance wall at the sidewall of the second opening, and remove part the first clearance wall to expose the drift angle of depression.Then,, take cover curtain layer, the first clearance wall and the second clearance wall as cover curtain, remove part substrate, to form the first irrigation canals and ditches and form the second irrigation canals and ditches in the substrate in the firstth district in the substrate of Second Region.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The manufacture method of the aforesaid two irrigation canals and ditches that have different depth, the first wherein said opening is greater than the second opening.
The manufacture method of the aforesaid two irrigation canals and ditches that have different depth, the step that wherein forms the first clearance wall and fill up the first dielectric layer in the second opening at the sidewall of above-mentioned the first opening comprises: in substrate, form dielectric materials layer, the thickness of dielectric materials layer is greater than a half width of the second opening; And remove part dielectric materials layer, until expose the surface of cover curtain layer.
The manufacture method of the aforesaid two irrigation canals and ditches that have different depth, the degree of depth of the first wherein said irrigation canals and ditches is 2～3 times of the degree of depth of the second irrigation canals and ditches.
The manufacture method of the aforesaid two irrigation canals and ditches that have different depth, the material of wherein said substrate comprises dielectric material.In order to a structure for isolated component, it is disposed in the substrate with surrounding zone and array area.The above-mentioned structure in order to isolated component comprises the first isolation structure.The first isolation structure has the section at least three rank and is arranged in the substrate of surrounding zone.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The aforesaid structure in order to isolated component, more comprises the second isolation structure, is arranged in the substrate of array area, and the second isolation structure has at least section of second order.
The aforesaid structure in order to isolated component, wherein said the first isolation structure and the second isolation structure comprise lining and dielectric layer separately.
The aforesaid structure in order to isolated component, the degree of depth of the first wherein said isolation structure is 2～3 times of the degree of depth of the second isolation structure.
The present invention compared with prior art has obvious advantage and beneficial effect.
By technique scheme, the manufacture method of semiconductor irrigation canals and ditches of the present invention and two irrigation canals and ditches and at least there is following advantages and beneficial effect in order to the structure of isolated component: in the method for the invention, compared with existing known twice lithography process, only need one lithography process to make two isolation structures or two irrigation canals and ditches structure with different depth, method is simple and save cost, can increase competitive advantage.In addition, of the present invention pair of isolation structure has the different degree of depth, can be applied to respectively surrounding zone and the array area of memory cell, meets the design requirement of memory cell.
In sum, the invention relates to the manufacture method of a kind of semiconductor irrigation canals and ditches and two irrigation canals and ditches and the structure in order to isolated component, the above-mentioned structure in order to isolated component is disposed in the substrate with surrounding zone and array area.The above-mentioned structure in order to isolated component comprises the first isolation structure and the second isolation structure.The first isolation structure has the section at least three rank and is arranged in the substrate of surrounding zone.The second isolation structure has the section of second order at least and is arranged in the substrate of array area.The present invention has significant progress technically, has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A to Fig. 1 H is the generalized section of the manufacture method of the structure in order to isolated component that illustrates according to one embodiment of the invention.
100: substrate 100 ', 102 ": surface
101: the first district/surrounding zones 102: cover curtain material layer
102a: cover curtain layer 102 ': bottom surface
103: Second Region/array area 104: patterning photoresist layer
105: 106: the first openings of end silicon oxide layer
107: 108: the second openings of silicon nitride layer
109: top silicon oxide layer 110: dielectric materials layer
114: the first dielectric layers of 112: the first clearance walls
116: 118: the second clearance walls cave in
122: the second irrigation canals and ditches of 120: the first irrigation canals and ditches
124: 126: the second dielectric layers of lining
130: the second isolation structures of 128: the first isolation structures
W1: thickness W2, W3: width
D1, D2: the degree of depth
Embodiment
Technological means and effect of taking for reaching predetermined goal of the invention for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to the semiconductor irrigation canals and ditches that propose according to the present invention and the manufacture method of two irrigation canals and ditches and in order to its embodiment of structure, method, step, structure, feature and effect thereof of isolated component, be described in detail as follows.
Relevant aforementioned and other technology contents of the present invention, Characteristic can be known and present in the following detailed description coordinating with reference to graphic preferred embodiment.By the explanation of embodiment, when obtaining one more deeply and concrete understanding for technological means and effect of reaching predetermined object and taking to the present invention, but appended graphic be only to provide with reference to the use of explanation, be not used for the present invention to be limited.
Figure 1A to 1H is the generalized section of the manufacture method of the structure in order to isolated component that illustrates according to one embodiment of the invention.
Refer to shown in Figure 1A, first, provide substrate 100.Substrate 100 can be that semiconductor base is as silicon base.Substrate 100 has the first district 101 and Second Region 103.In the time that the present invention is applied to memory cell, the first district 101 is for example surrounding zone, and Second Region 103 is for example array area.For clarity of illustration, below take surrounding zone 101 and array area 103 illustrate as example.
Then, in substrate 100, sequentially form cover curtain material layer 102 and patterning photoresist layer 104.The method of above-mentioned formation cover curtain material layer 102 comprises carries out chemical vapour deposition technique.Cover curtain material layer 102 can be single or multiple lift structure.The material of cover curtain material layer 102 is selected from silica, carborundum, silicon nitride, silicon oxynitride and combination thereof.In one embodiment, cover curtain material layer 102 can be three-decker, comprises end silicon oxide layer 105, silicon nitride layer 107 and top silicon oxide layer 109.
Then, refer to shown in Figure 1B, take patterning photoresist layer 104 as cover curtain, remove part cover curtain material layer 102, to form cover curtain layer 102a.Cover curtain layer 102a has the first opening 106 of the substrate 100 that exposes surrounding zone 101 to the open air and exposes the second opening 108 of the substrate 100 of array area 103 to the open air, and wherein the first opening 106 is greater than the second opening 108.The above-mentioned method that removes part cover curtain material layer 102 comprises carries out dry ecthing method.Dry ecthing method comprises brokenly etching step, main etching step and over etching step.In one embodiment, carrying out in over etching step, the surface 100 of the substrate 100 that the first opening 106 and the second opening 108 expose to the open air ' lower than the bottom surface 102 of cover curtain layer 102a ', as shown in Figure 1B.(do not illustrate) in another embodiment, the bottom surface 102 of the surface 101 of the substrate 100 that the first opening 106 and the second opening 108 expose to the open air ' also can be substantially equal to cover curtain layer 102a '.Then, remove patterning photoresist layer 104.
In the above-described embodiments, be to illustrate as an example of first opening 106 and two the second openings 108 example, but the present invention is not as limit.In other words, the present invention is not restricted the quantity of the first opening 106 and the second opening 108.
Afterwards, refer to shown in Fig. 1 C, in substrate 100, form dielectric materials layer 110.The method of above-mentioned formation dielectric materials layer 110 comprises carries out chemical vapour deposition technique.The material of dielectric materials layer 110 is for example silica or silicon nitride.Be noted that especially the thickness W1 of dielectric materials layer 110 is greater than the half of the width W 2 of the second opening 108, but be less than the half of the width W 3 of the first opening 106.That is to say, the thickness W1 of dielectric materials layer 110 needs thick in being enough to fill up the second opening 108, but the first opening 106 can not filled up.
Then, refer to shown in Fig. 1 D, remove part dielectric materials layer 110, until expose the surface 102 of cover curtain layer 102a ", to form the first clearance wall 112 at the sidewall of the first opening 106, and in the second opening 108, fill up the first dielectric layer 114.Then, take cover curtain layer 102a and the first clearance wall 112 as cover curtain, to form depression 116 in the substrate 100 of surrounding zone 101.The above-mentioned method that removes part dielectric materials layer 110 and formation depression 116 comprises the dry ecthing method that carries out two steps, that is to say, the step of above-mentioned Fig. 1 D can be carried out in same reative cell.
Then, refer to shown in Fig. 1 E, remove part of first dielectric layer 114 to form the second clearance wall 118 at the sidewall of the second opening 108, and remove part the first clearance wall 112 to expose the drift angle A of depression 116.The above-mentioned method that removes part of first dielectric layer 114 and remove part the first clearance wall 112 comprises carries out wet etch method.
Afterwards, refer to shown in Fig. 1 F, take cover curtain layer 102a, the first clearance wall 112 and the second clearance wall 118 as cover curtain, remove part substrate 100, to form the first irrigation canals and ditches 120 and form the second irrigation canals and ditches 122 in the substrate 100 of surrounding zone 101 in the substrate 100 of array area 103.The first irrigation canals and ditches 120 have the section at least three rank, and the second irrigation canals and ditches 122 have at least section of second order.The depth D 1 of the first irrigation canals and ditches 120 is 2～3 times of depth D 2 of the second irrigation canals and ditches 122.In one embodiment, the depth D 1 of the first irrigation canals and ditches 120 is 3500 dusts
and the depth D 2 of the second irrigation canals and ditches 122 is 1400 dusts.The method of above-mentioned formation the first irrigation canals and ditches 120 and the second irrigation canals and ditches 122 comprises carries out dry ecthing method.
Then, refer to shown in Fig. 1 G, remove the first clearance wall 112 and the second clearance wall 118.The above-mentioned method that removes the first clearance wall 112 and the second clearance wall 118 comprises carries out wet etch method.Then, form lining 124 on the surface of the first irrigation canals and ditches 120 and the second irrigation canals and ditches 122.The material of lining 124 is for example silica.The method of above-mentioned formation lining 124 comprises carries out thermal oxidation method.In the process of formation lining 124, the wedge angle of the first irrigation canals and ditches 120 and the second irrigation canals and ditches 122 also can be by round and smoothization (rounded).
Then, in the first irrigation canals and ditches 120 and the second irrigation canals and ditches 122, insert the second dielectric layer 126.The above-mentioned method of inserting the second dielectric layer 126 comprises carries out chemical vapour deposition technique.The material of the second dielectric layer 126 is for example silica.In one embodiment, the second dielectric layer 126 is identical with the material of dielectric materials layer 110, for example, be silica.In another embodiment, the second dielectric layer 126 is different from the material of dielectric materials layer 110.
What pay special attention to is, the above-mentioned step that removes the first clearance wall 112 and the second clearance wall 118 and the step that forms lining 124 also can be omitted, and make the second dielectric layer 126 be formed directly on the first clearance wall 112 and the second clearance wall 118 and insert in the first irrigation canals and ditches 120 and the second irrigation canals and ditches 122.
Afterwards, refer to shown in Fig. 1 H, utilize dry ecthing method to remove the second dielectric layer 126 outside the first irrigation canals and ditches 120 and the second irrigation canals and ditches 122.Then, utilize dry ecthing method to remove cover curtain layer 102a.So far, complete the making of the first isolation structure 128 and the second isolation structure 130.
Based on the above, structure in order to isolated component of the present invention is two isolation structures (being the first isolation structure 128 and the second isolation structure 130 of Fig. 1 H) with different depth, in its manufacture process, only need one lithography process (the patterning photoresist layer 104 of Figure 1A), not only technique is simple but also can save cost.
Next, will the structure in order to isolated component of the present invention be described with the structure of Fig. 1 H.Structure in order to isolated component of the present invention is disposed in the substrate 100 with surrounding zone 101 and array area 103.The above-mentioned structure in order to isolated component comprises the first isolation structure 128 and the second isolation structure 130.The first isolation structure 128 has the section at least three rank and is arranged in the substrate 100 of surrounding zone 101.The second isolation structure 130 has the section of second order at least and is arranged in the substrate 100 of array area 103.The first isolation structure 128 and the second isolation structure 130 comprise lining 124 and the second dielectric layer 126 separately.The depth D 1 of the first isolation structure 128 is 2～3 times of depth D 2 of the second isolation structure 130.
In the above-described embodiments, the manufacture method of above-mentioned irrigation canals and ditches is to be applied to the structure forming in order to isolated component, but the present invention is not limited to this.The manufacture method of above-mentioned irrigation canals and ditches also can be applied in the material layer of any irrigation canals and ditches that need to make different depth.For instance, above-mentioned substrate is not limited to semiconductor base, can be also dielectric material substrate, and the channel layer filling among irrigation canals and ditches is also not limited to dielectric layer.In another embodiment, two irrigation canals and ditches are formed in dielectric layer, and the material layer filling among irrigation canals and ditches can be conductive layer, for example, be metal level, and metal level has different thickness, and it can be as wire, or is called metal wire.
In sum, method of the present invention only needs one lithography process to make two isolation structures or two irrigation canals and ditches structure with different depth, does not need existing known twice lithography process, and method is simple and save cost, can increase competitive advantage.In addition, of the present invention pair of isolation structure has the different degree of depth, can be applied to respectively surrounding zone and the array area of memory cell, meets the design requirement of memory cell.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (9)
1. a manufacture method for semiconductor irrigation canals and ditches, is characterized in that it comprises the following steps:
One substrate is provided, and this substrate has a surrounding zone and an array district;
In this substrate, form a cover curtain layer, this cover curtain layer has one first opening of this substrate that exposes this surrounding zone to the open air and exposes one second opening of this substrate of this array area to the open air;
Sidewall at this first opening forms one first clearance wall;
Take this cover curtain layer and this first clearance wall as cover curtain, in this substrate of this surrounding zone, form a depression;
Sidewall at this second opening forms one second clearance wall, and removes this first clearance wall of part to expose the drift angle of this depression; And
Take this cover curtain layer, this first clearance wall and this second clearance wall as cover curtain, remove this substrate of part, to form one first irrigation canals and ditches and form one second irrigation canals and ditches in this substrate of this surrounding zone in this substrate of this array area.
2. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, is characterized in that the first wherein said opening is greater than this second opening.
3. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, is characterized in that wherein the step that forms this first clearance wall at the sidewall of this first opening comprises:
In this substrate, form a dielectric materials layer, the thickness of this dielectric materials layer is greater than a half width of this second opening; And
Remove this dielectric materials layer of part, until expose the surface of this cover curtain layer, wherein remaining this dielectric materials layer forms this first clearance wall and fills up this second opening at the sidewall of this first opening.
4. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, it is characterized in that the first wherein said irrigation canals and ditches have the section at least three rank, and these second irrigation canals and ditches has at least section of second order.
5. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, the degree of depth that it is characterized in that the first wherein said irrigation canals and ditches is 2～3 times of the degree of depth of these the second irrigation canals and ditches.
6. there is a manufacture method for two irrigation canals and ditches of different depth, it is characterized in that it comprises the following steps:
One substrate is provided, and this substrate has one first district and a Second Region;
In this substrate, form a cover curtain layer, this cover curtain layer has one first opening of this substrate that exposes this firstth district to the open air and exposes one second opening of this substrate of this Second Region to the open air;
Sidewall at this first opening forms one first clearance wall and in this second opening, fills up one first dielectric layer;
Take this cover curtain layer and this first clearance wall as cover curtain, in this substrate in this firstth district, form a depression;
Remove this first dielectric layer of part, form one second clearance wall with the sidewall at this second opening, and remove this first clearance wall of part to expose the drift angle of this depression; And
Take this cover curtain layer, this first clearance wall and this second clearance wall as cover curtain, remove this substrate of part, to form one first irrigation canals and ditches and form one second irrigation canals and ditches in this substrate in this firstth district in this substrate of this Second Region.
7. the manufacture method of two irrigation canals and ditches with different depth according to claim 6, is characterized in that the first wherein said opening is greater than this second opening.
8. the manufacture method of two irrigation canals and ditches with different depth according to claim 6, is characterized in that wherein the step that forms this first clearance wall and fill up this first dielectric layer in this second opening at the sidewall of this first opening comprises:
In this substrate, form a dielectric materials layer, the thickness of this dielectric materials layer is greater than a half width of this second opening; And
Remove this dielectric materials layer of part, until expose the surface of this cover curtain layer.
9. the manufacture method of two irrigation canals and ditches with different depth according to claim 6, the degree of depth that it is characterized in that the first wherein said irrigation canals and ditches is 2～3 times of the degree of depth of these the second irrigation canals and ditches.
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| US20140167206A1 (en) * | 2012-12-17 | 2014-06-19 | Macronix International Co., Ltd. | Shallow trench isolation structure and method of manufacture |
| CN106328651B (en) * | 2016-09-19 | 2019-12-06 | 中国电子科技集团公司第五十八研究所 | Dielectric isolation structure for SOI process and method thereof |
| TWI636547B (en) * | 2017-08-25 | 2018-09-21 | 旺宏電子股份有限公司 | Semiconductor memory device and method of manufacturing the same |
| US10354924B2 (en) | 2017-08-30 | 2019-07-16 | Macronix International Co., Ltd. | Semiconductor memory device and method of manufacturing the same |
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| CN1638088A (en) * | 2003-12-26 | 2005-07-13 | 恩益禧电子股份有限公司 | Method for manufacturing semiconductor device |
| CN101118868A (en) * | 2006-08-02 | 2008-02-06 | 力晶半导体股份有限公司 | Method for manufacturing isolation structure |
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| KR100389031B1 (en) * | 2001-06-19 | 2003-06-25 | 삼성전자주식회사 | Method of fabricating semiconductor device having trench isolation structure |
| JP2005294759A (en) * | 2004-04-05 | 2005-10-20 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
| US20080283930A1 (en) * | 2007-05-15 | 2008-11-20 | International Business Machines Corporation | Extended depth inter-well isolation structure |
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| CN1638088A (en) * | 2003-12-26 | 2005-07-13 | 恩益禧电子股份有限公司 | Method for manufacturing semiconductor device |
| CN101118868A (en) * | 2006-08-02 | 2008-02-06 | 力晶半导体股份有限公司 | Method for manufacturing isolation structure |
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| C06 | Publication | ||
| PB01 | Publication | ||
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