CN102542320A - Radio frequency identification (RFID) chip structure and test method for reducing test crosstalk - Google Patents
Radio frequency identification (RFID) chip structure and test method for reducing test crosstalk Download PDFInfo
- Publication number
- CN102542320A CN102542320A CN2010105825638A CN201010582563A CN102542320A CN 102542320 A CN102542320 A CN 102542320A CN 2010105825638 A CN2010105825638 A CN 2010105825638A CN 201010582563 A CN201010582563 A CN 201010582563A CN 102542320 A CN102542320 A CN 102542320A
- Authority
- CN
- China
- Prior art keywords
- test
- rfid chip
- ground terminal
- welding point
- pressure welding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a radio frequency identification (RFID) chip structure for reducing test crosstalk. Except conventional radio frequency antenna terminals are arranged in a RFID chip, at least one ground terminal connected with a silicon substrate is additionally arranged in the RFID chip. A test pressure welding point guided out of the ground terminal serves as a reference ground test pressure welding point. The invention further discloses a test method for reducing the test crosstalk and corresponding to the chip structure. The test pressure welding point of the ground terminal is in connection with a signal reference ground of a test system through a probe card in a wafer-level test of the RFID chip, so that reference ground level of the chip of a tested object can be consistent with the reference ground of the signal of the test system, then the crosstalk caused by fluctuation of the reference ground level is reduced, and test stability is improved.
Description
Technical field
The present invention relates to a kind of RFID chip structure, particularly a kind ofly can reduce the RFID chip structure that test is crosstalked in the wafer-level test.The invention still further relates to a kind of method of testing that test is crosstalked that reduces.
Background technology
During test chip RF function, be to improve testing efficiency in the RFID chip die level test, reduce testing cost; Can test a plurality of tested objects simultaneously, promptly many tested objects close on the definition of tested object with surveying when being illustrated in figure 1 as many tested objects with survey; Be example to use 16 same survey probe to contact for 1 time among the figure; Shown the matrix that closes on tested object, if chip 12 is tested, 15 chips of other in this matrix are and close on tested object.Because RFID chip testing, many tested objects are with bringing the cross-interference issue that closes between tested object in the survey process, and its reason mainly contains: the one, and the signal cross-talk between TCH test channel; The 2nd, the non-isolation of chip on wafer.It is continuous through shared wafer silicon substrate that wherein the latter is embodied in the reference ground that closes on the tested object chip; Promptly altogether; And the characteristics of RFID chip be the transmission of signal are to carry out through two antenna terminals, as far as chip its with reference to the level decision of ground level, because the common ground characteristics of closing on chip by two input signals; If when a certain object chip is carried out the RF test; The fluctuating of the ground reference that imports during the action of this chip can influence the fluctuating that it closes on the ground level of tested object, thereby causes the circuit working that closes on tested object undesired and bring test unstable, finally influences testing yield.
To the problems referred to above, existing technical solution mainly focuses on shielding and the isolation of strengthening between test channel signal, promptly mainly be the technical scheme to above-mentioned reason one, so its effect is limited; Or reduce many tested objects and reduce the mutual probability of interference that closes on the tested object chip with the quantity of surveying, but can reduce chip testing efficiency so undoubtedly, improve testing cost.For can further solving the problems of the technologies described above; The present invention is directed to the test cross-interference issue that said reason two causes; Propose a kind ofly can reduce RFID chip structure and the method for testing that such is crosstalked, in the hope of solving many tested objects of facing in the test of RFID chip die level with surveying instability problem.
Summary of the invention
The technical matters that the present invention will solve provides a kind of RFID chip structure, and it can improve the stability of test when multi-object is with survey in the wafer-level test, eliminates the same survey number of objects quantitative limitation that causes because of crosstalking.
For solving the problems of the technologies described above; The RFID chip structure that reduction test of the present invention is crosstalked; Its in the RFID chip except that being designed with the RF antenna terminal; Also design increases the ground terminal that has at least one to be connected with silicon substrate, and this ground terminal leads to ground terminal test pressure welding point (PAD), tests pressure welding point as a reference.Many tested objects of RFID chip die level test with the survey process in tested object the signal reference of terminal test pressure welding point in said ground through probe and test macro be connected.
The present invention also provides a kind of method of testing that test is crosstalked that reduces, and its technical scheme is to adopt following steps to test:
The first step is drawn the ground terminal on RFID chip silicon substrate, this ground terminal is drawn ground terminal test pressure welding point;
In second step, said ground terminal test pressure welding point is connected with the signal reference ground of test macro through probe;
The 3rd step is through test system and test RFID chip performance.
Technique effect of the present invention:
Because respectively closing on the reference ground of tested object chip all is connected with the reference ground of test macro; Therefore the reference ground level of tested object chip can be consistent with the signal reference ground of test macro, thereby the fluctuating of the reference ground level of tested object chip in the test process is greatly reduced, can effectively reduce close on tested object in test process by crosstalking of causing with reference to the ground level fluctuating; Improved the stability of test; Eliminate the same survey number of objects quantitative limitation that causes because of crosstalking, thereby improved the efficient of RFID chip die level test, reduced testing cost; Illustrate; Before not adopting the present invention, it is 2 with surveying that Datong District surveys number of objects, and crosstalks and cause that the unstable yield loss of test is 10%; After adopting the present invention, it is 64 with surveying that Datong District surveys number of objects, causes that by crosstalking the unstable yield loss of test is 0.5%, like this, only considers with the raising of surveying number, just can the test duration cost be reduced to original 1/32.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 defines synoptic diagram for the wafer-level test multi-object with closing on tested object in surveying;
Fig. 2 is not for using RFID chip layout design diagram of the present invention;
Fig. 3 is the ground terminal physical connection synoptic diagram of example with P type wafer substrate for the present invention;
Fig. 4 is for using RFID chip layout design diagram of the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage are clearer, below in conjunction with specific embodiment, with reference to accompanying drawing, the present invention are done further explain.
Shown in Figure 2 for not using RFID chip layout design of the present invention, it has two antenna terminal ANT1 and ANT2.Shown in Figure 3ly close on chip for of the present invention two; Chip A and chip B; It is except having original device architecture; Outside RF antenna terminal (antenna terminal test pressure welding point) ANT1 and ANT2, metal-oxide-semiconductor etc., also design increases the ground terminal have at least one to be connected with silicon substrate, in this example with P type wafer substrate be example lead to terminal.Shown in Figure 4 for using RFID chip layout design of the present invention; Each chip is an example with 2 ground terminals; This various places terminal leads to test pressure welding point 1 and 2 respectively; Test solder joint as a reference, so chip structure of the present invention is except having antenna terminal (antenna terminal test pressure welding point) ANT1 and ANT2, also has two ground terminals (terminal test pressure welding point) 1 and 2.
The present invention reduces the method for testing that test is crosstalked, and it adopts following steps to test:
The first step, as shown in Figure 3, on RFID chip silicon substrate, draw the ground terminal, this ground terminal is drawn ground terminal test pressure welding point, and is as shown in Figure 4;
In second step, said ground terminal test pressure welding point is connected with the signal reference ground of test macro through probe;
The 3rd step is through test system and test RFID chip performance.
Said ground terminal test pressure welding point 1 with tested object when many tested objects are surveyed together is connected with the signal reference ground of test macro through probe with 2; Therefore the reference ground level of tested object chip can with the signal reference of test macro be consistent; Thereby greatly reduce tested object chip in the test process with reference to the fluctuating of ground level, also just reduced the cross-interference issue that closes on the tested object chip chamber.
Claims (2)
1. one kind is reduced the RFID chip structure that test is crosstalked; In the RFID chip except that being designed with conventional RF antenna terminal; It is characterized in that, also comprise: the ground terminal that at least one is connected with silicon substrate, this ground terminal lead to ground terminal test pressure welding point; It tests pressure welding point as a reference, this ground terminal test pressure welding point many tested objects of RFID chip die level test with the survey process in through probe and test macro signal reference be connected.
2. one kind is reduced the method for testing that RFID chip testing is crosstalked, and its test that can reduce in the test of RFID chip die level is crosstalked, and it is characterized in that, adopts following steps to test:
The first step is drawn the ground terminal on RFID chip silicon substrate, this ground terminal is drawn ground terminal test pressure welding point;
In second step, said ground terminal test pressure welding point is connected with the signal reference ground of test macro through probe;
The 3rd step is through test system and test RFID chip performance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010582563.8A CN102542320B (en) | 2010-12-10 | 2010-12-10 | Radio frequency identification (RFID) chip structure and test method for reducing test crosstalk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010582563.8A CN102542320B (en) | 2010-12-10 | 2010-12-10 | Radio frequency identification (RFID) chip structure and test method for reducing test crosstalk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102542320A true CN102542320A (en) | 2012-07-04 |
| CN102542320B CN102542320B (en) | 2014-12-10 |
Family
ID=46349168
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010582563.8A Active CN102542320B (en) | 2010-12-10 | 2010-12-10 | Radio frequency identification (RFID) chip structure and test method for reducing test crosstalk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102542320B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103336935A (en) * | 2013-06-03 | 2013-10-02 | 上海华力微电子有限公司 | Probe card identification device and probe card identification method |
| CN103630819A (en) * | 2013-11-29 | 2014-03-12 | 浙江德马科技有限公司 | Device for testing performance of RFID chip |
| CN106409707A (en) * | 2015-07-28 | 2017-02-15 | 中芯国际集成电路制造(上海)有限公司 | Non-contact RF chip wafer testing method and apparatus |
| CN106872874A (en) * | 2015-12-11 | 2017-06-20 | 华大半导体有限公司 | One kind concentrates CP method of testings for RFID label chip |
| CN111432308A (en) * | 2020-03-30 | 2020-07-17 | 上海闻泰电子科技有限公司 | Audio communication circuit, electronic equipment and audio communication test system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146908A (en) * | 1999-03-12 | 2000-11-14 | Stmicroelectronics, S.A. | Method of manufacturing a test circuit on a silicon wafer |
| CN101452042A (en) * | 2007-11-30 | 2009-06-10 | 中芯国际集成电路制造(上海)有限公司 | Wafer grade reliability parallel test method for field effect tube negative temperature instability |
| CN101196554B (en) * | 2006-12-04 | 2010-05-12 | 上海华虹Nec电子有限公司 | Wafer multi-test object parallel test system |
-
2010
- 2010-12-10 CN CN201010582563.8A patent/CN102542320B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146908A (en) * | 1999-03-12 | 2000-11-14 | Stmicroelectronics, S.A. | Method of manufacturing a test circuit on a silicon wafer |
| CN101196554B (en) * | 2006-12-04 | 2010-05-12 | 上海华虹Nec电子有限公司 | Wafer multi-test object parallel test system |
| CN101452042A (en) * | 2007-11-30 | 2009-06-10 | 中芯国际集成电路制造(上海)有限公司 | Wafer grade reliability parallel test method for field effect tube negative temperature instability |
Non-Patent Citations (1)
| Title |
|---|
| 杨之廉: "《集成电路导论》", 31 March 2003, 清华大学出版社 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103336935A (en) * | 2013-06-03 | 2013-10-02 | 上海华力微电子有限公司 | Probe card identification device and probe card identification method |
| CN103336935B (en) * | 2013-06-03 | 2016-08-10 | 上海华力微电子有限公司 | A kind of probe card identification apparatus and method |
| CN103630819A (en) * | 2013-11-29 | 2014-03-12 | 浙江德马科技有限公司 | Device for testing performance of RFID chip |
| CN103630819B (en) * | 2013-11-29 | 2016-01-27 | 浙江德马科技有限公司 | Device for testing performance of RFID chip |
| CN106409707A (en) * | 2015-07-28 | 2017-02-15 | 中芯国际集成电路制造(上海)有限公司 | Non-contact RF chip wafer testing method and apparatus |
| CN106872874A (en) * | 2015-12-11 | 2017-06-20 | 华大半导体有限公司 | One kind concentrates CP method of testings for RFID label chip |
| CN111432308A (en) * | 2020-03-30 | 2020-07-17 | 上海闻泰电子科技有限公司 | Audio communication circuit, electronic equipment and audio communication test system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102542320B (en) | 2014-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102542320B (en) | Radio frequency identification (RFID) chip structure and test method for reducing test crosstalk | |
| US8941401B2 (en) | Test circuit of an integrated circuit on a wafer | |
| US20090297146A1 (en) | Multiple core system | |
| US9444510B2 (en) | Method and apparatus for incorporating passive devices in an integrated passive device separate from a die | |
| US9024315B2 (en) | Daisy chain connection for testing continuity in a semiconductor die | |
| CN104253095A (en) | Semiconductor package having wire bond wall to reduce coupling | |
| US20120319912A1 (en) | Communication device and semiconductor chip | |
| CN103630824A (en) | Chip concurrent test system | |
| CN101196554B (en) | Wafer multi-test object parallel test system | |
| CN205450046U (en) | Many probe test subassembly | |
| CN104133169B (en) | Non-contact chip test system and method | |
| CN102854455A (en) | Integrated circuit testing system and control method for same | |
| CN105445509A (en) | Cantilever-type probe system for parallel testing of multiple radio frequency chips | |
| US20140210496A1 (en) | Chip-to-chip signal transmission system and chip-to-chip capacitive coupling transmission circuit | |
| CN106792803B (en) | Parallel test method and system for dual-frequency multi-antenna to-be-tested equipment | |
| Elisabeth | Advanced RF packaging technology trends, from WLP and 3D integration to 5G and mmWave applications | |
| US8773162B2 (en) | Communication cell for an integrated circuit, chip comprising said communication cell, electronic system including the chip, and test apparatus | |
| CN104614658A (en) | Method for testing high-frequency chip wafers through multi-channel probe card | |
| CN201332098Y (en) | ESD protecting circuit of depletion type pHEMT chips | |
| US20150061725A1 (en) | Semiconductor integrated circuit | |
| CN106054057B (en) | Interposer device for testing semiconductor chips | |
| CN115267685B (en) | Built-in microwave signal state data readback TR component wave control module | |
| US20120091575A1 (en) | Semiconductor Package And Method For Making The Same | |
| CN106330243A (en) | Method and device for switching receiving sensitivity of terminal | |
| US20110156739A1 (en) | Test kit for testing a chip subassembly and a testing method by using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140103 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140103 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |