CN102522987B

CN102522987B - Incoherent re-sampling device

Info

Publication number: CN102522987B
Application number: CN201110460892XA
Authority: CN
Inventors: 潘申富; 王赛宇; 陈敬乔; 张静
Original assignee: CETC 54 Research Institute
Current assignee: CETC 54 Research Institute
Priority date: 2011-12-31
Filing date: 2011-12-31
Publication date: 2013-11-20
Anticipated expiration: 2031-12-31
Also published as: CN102522987A

Abstract

The invention discloses an incoherent re-sampling device, and relates to sampling rate conversion technology in the communication field. The incoherent re-sampling device comprises a data caching unit (1), an interpolation filtering unit (2) and a clock adjustment unit (3). Different frequency control words are set and address signals sent by the clock adjustment unit are utilized to search the temporal relation between input samples and output samples, and the sampling rate conversion purpose is realized after interpolation filtering. As the re-sampling and low-pass filtering integrated design is adopted, compared with the traditional realization method of re-sampling technology, the incoherent re-sampling device provided by the invention has the advantages of easiness in realization, stable and reliable performance, non-linear distortion prevention and the like, and is particularly suitable for input and output sampling rate conversion in a communication system.

Description

Incoherent re-sampling device

Technical field

The present invention relates to a kind of Incoherent re-sampling device in the communications field, be specially adapted to the conversion as sample rate in communication system.

Background technology

Sampling rate conversion is a kind of method that changes Digital Signal Processing speed, important effect is arranged in communication engineering, when multiple traffic rate or processing clock being arranged not during homology in system, can make speed normalization by sampling rate conversion, in former design, simulated assembly or special chip that sampling rate conversion can only rely on AD and DA to form are realized, complex structure, power consumption is large, and the chip that can select is less.Adopt incoherent digital resampling technology to realize that the conversion of multiple traffic rate has important using value.

Summary of the invention

The object of the invention is to avoid the weak point in the above-mentioned background technology and provide a kind of in the situation that do not affect the signal normal transmission,, according to having sampling point and any sampling rate conversion demand, producing the sampling rate conversion device of new sampling point.The characteristics such as that the present invention also has is stable and reliable for performance, low in energy consumption, can realize the conversion of fraction time sampling rate, complexity is low.

the object of the present invention is achieved like this: it is by data buffer storage unit 1, filtering interpolation unit 2, clock adjustment unit 3 forms, it is characterized in that: also comprise filtering interpolation unit 2, clock adjustment unit 3, wherein end 1 pin that enters of data buffer storage unit 1 is connected with outer input data A, the data that needs are resampled are sent into data buffer storage unit 1 and are carried out buffer memory, end 2 pin that enter of data buffer storage unit 1 are connected with end 1 pin that goes out of clock adjustment unit 3, give data buffer storage unit 1 with the address information of clock adjustment unit 3 outputs, data buffer storage unit 1 reads corresponding data according to address information, and data are exported through going out end 3 pin, send into the input FPDP 2 of filtering interpolation unit 2, filtering interpolation unit 2 enters end 1 pin and goes out to hold 2 pin to be connected with clock adjustment unit 3, receive the location of interpolation information of self-clock adjustment unit 3, the output data of filtering interpolation unit 2 are connected with external data output mouth B through going out end 3 pin, end 3 pin that enter of clock adjustment unit 3 are connected with the clock C of the outside input data of sending here, end 4 pin that enter of clock adjustment unit 3 are connected with the clock D of the outside output data of sending here, clock adjustment unit 3 enters end 5 pin and is connected with the outside frequency control word E that sends here.

filtering interpolation of the present invention unit 2 is by filter coefficient table module 4, convolution module 5 forms, wherein filter coefficient table module 4 enters to hold 1 pin and clock adjustment unit 3 to go out to hold 2 pin to be connected, corresponding certain the group coefficient of the address choice of sending according to clock adjustment unit 3, selected coefficient is exported through end 2 pin that go out of filter coefficient table module 4, send into the input port 1 of convolution module 5, end 2 pin that enter of convolution module 5 are connected with end 3 pin that go out of buffer unit 1, receive the output data of buffer unit 1, the input data of convolution module 5 are exported through going out end 3 pin after completing convolution with corresponding coefficient.

clock adjustment unit 3 of the present invention is by input clock frequency divider 6, output clock frequency divider 7, clocking error extractor 8, loop filter 9, NCO10 forms, wherein input clock frequency divider 6 enters to hold 1 pin to be connected with input clock C, clock after frequency division is connected through going out to hold 2 pin and clocking error extractor 8 to enter end 1 pin, output clock frequency divider 7 enters end 1 pin and is connected with input clock D, clock after frequency division is connected through going out to hold 2 pin and clocking error extractor 8 to enter end 2 pin, two clock signals of 8 pairs of inputs of clocking error extractor compare rear output phase discrimination signal, end 3 pin that go out through clocking error extractor 8 are exported, end 1 pin that enters of sending into loop filter 9 carries out filtering, loop filter 9 goes out end 2 pin and is connected with end 1 pin that enters of NCO10, end 2 pin that enter of NCO10 are connected with the outside frequency control word E that sends here, NCO10 goes out end 3 pin and is connected with end 3 pin that enter of output clock frequency divider 7, the data address information of NCO10 output is connected through going out to hold 4 pin and data buffer storage unit 1 to enter end 2 pin, for providing, data buffer storage unit 1 reads address, the coefficient address information of NCO10 output is connected through going out to hold 5 pin and filtering interpolation unit 2 to enter end 1 pin, for filtering interpolation unit 2 provides corresponding coefficient address.

The present invention compares with background technology has following advantage:

1. the present invention adopts the low pass filter that group delay changes with the resample points position, can realize high-precision synchronous arbitrarily under low sample rate, thereby its computation complexity is very low, even can not pay extra calculation cost can well keep resampling before and after waveform and the spectral characteristic of signal constant, can not produce nonlinear distortion after conversion, the signal to noise ratio of signal does not reduce substantially, and simulation result shows that incoherent digital resampling performance is fine.

2. the present invention is portable strong, low in energy consumption, stable and reliable for performance.

3. the present invention is simple in structure, and implementation complexity is very low, and cost is low, has application value.

Description of drawings

Fig. 1 is functional-block diagram of the present invention.

Fig. 2 is the electrical schematic diagram of base filtering interpolation of the present invention unit 2.

Fig. 3 is the electrical schematic diagram of clock adjustment unit 3 of the present invention.

Embodiment

, referring to figs. 1 through Fig. 3, the present invention includes data buffer storage unit 1, filtering interpolation unit 2, clock adjustment unit 3.Fig. 1 is functional-block diagram of the present invention, and embodiment presses Fig. 1 connection line.Wherein data buffer storage unit 1 its effect is the data of storage certain-length, and 2 its effects of filtering interpolation unit are that the input data are carried out filtering interpolation, and 3 its effects of clock adjustment unit are to produce the clock phase discrimination signal, and calculate the position that needs interpolation according to error.

Filtering interpolation of the present invention unit 2 is comprised of filter coefficient table module 4, convolution module 5.Fig. 2 is the electrical schematic diagram of filtering interpolation unit 2, and embodiment presses Fig. 2 connection line.Wherein the effect of filter coefficient table module 4 is coefficients of storage interpolation filter, and the effect of convolution module 5 is that the data of input and the filter coefficient of the gained of tabling look-up are carried out convolution, reaches the purpose of filtering.

Clock adjustment unit 3 of the present invention is by input clock frequency divider 6, output clock frequency divider 7, clocking error extractor 8, loop filter 9, and NCO10 forms.Fig. 3 is the electrical schematic diagram of clock adjustment unit 3, and embodiment presses Fig. 3 connection line.Wherein the effect of input clock frequency divider 6 is that input clock C is carried out frequency division, the effect of output clock frequency divider 7 is that output clock D is carried out frequency division, the effect of clocking error extractor 8 is that two clocks inputting are carried out phase demodulation, obtain error signal, the effect of loop filter 9 is that error signal is carried out filtering, the effect of NCO10 is to control Clock dividers 7, generation data address signal and coefficient address signal, wherein data address signal is given data buffer storage unit 1, and the coefficient address signal is given filtering interpolation unit 2.

The concise and to the point operation principle of the present invention is as follows: incoherent numeral resamples in the system of multiple sampling rate or occurs that clock not during the data-linkage of homology, will bear the effect of sampling rate conversion.The present invention, according to input clock, output clock and input data, produces the sampled point that makes new advances, thereby realizes the conversion of sample rate.Its internal main will be by data buffer storage unit 1, and filtering interpolation unit 2, clock adjustment unit 3 form.Clock control module is completed the phase demodulation of input clock and output clock and the generation of data buffer storage address and interpolater coefficient address.Data buffer storage unit is mainly completed the buffer memory of data.The interpolation of interpolation filter settling signal and filtering.

the course of work of Incoherent re-sampling is as follows, input data clock and output data clock from outside enter clock adjustment unit 3, respectively must be with the frequency clock after input clock frequency divider 6 and output clock frequency divider 7, clock after frequency division is sent into clocking error extractor 8, obtain phase discrimination signal, phase discrimination signal carries out filtering through loop filter 9, filtered signal is given NCO10 and is used for adjusting output clock frequency divider 7, obtain simultaneously the address information of interpolation position by NCO10, address information inputs to data buffer storage unit 1 and filtering interpolation unit 2, data buffer storage unit 1 is chosen corresponding data according to address, corresponding one group of coefficient is chosen according to address in filtering interpolation unit 2, the data of choosing and coefficient all input to filtering interpolation unit 2 and carry out interpolation, complete the function of resampling.

Claims

1. Incoherent re-sampling device, comprise data buffer storage unit (1), it is characterized in that: also comprise filtering interpolation unit (2), clock adjustment unit (3), wherein end 1 pin that enters of data buffer storage unit (1) is connected with outer input data A, the data that needs are resampled are sent into data buffer storage unit (1) and are carried out buffer memory, end 2 pin that enter of data buffer storage unit (1) are connected with end 1 pin that goes out of clock adjustment unit (3), give data buffer storage unit (1) with the address information of clock adjustment unit (3) output, data buffer storage unit (1) reads corresponding data according to address information, and data are exported through going out end 3 pin, send into the input FPDP 2 of filtering interpolation unit (2), filtering interpolation unit (2) enters end 1 pin and goes out to hold 2 pin to be connected with clock adjustment unit (3), receive the location of interpolation information of self-clock adjustment unit (3), the output data of filtering interpolation unit (2) are connected with external data output mouth B through going out end 3 pin, clock adjustment unit (3) enters end 3 pin and is connected with the clock C of the outside input data of sending here, clock adjustment unit (3) enters end 4 pin and is connected with the clock D of the outside output data of sending here, and clock adjustment unit (3) enters end 5 pin and is connected with the outside frequency control word E that sends here,

clock adjustment unit (3) comprises input clock frequency divider (6), output clock frequency divider (7), clocking error extractor (8), loop filter (9) and NCO (10), wherein input clock frequency divider (6) enters to hold 1 pin to be connected with input clock C, and the clock after frequency division enters to hold 1 pin to be connected through going out end 2 pin and clocking error extractor (8), output clock frequency divider (7) enters end 1 pin and is connected with input clock D, and the clock after frequency division enters to hold 2 pin to be connected through going out end 2 pin and clocking error extractor (8), clocking error extractor (8) compares rear output phase discrimination signal to two clock signals of input, end 3 pin that go out through clocking error extractor (8) are exported, end 1 pin that enters of sending into loop filter (9) carries out filtering, loop filter (9) goes out end 2 pin and is connected with end 1 pin that enters of NCO (10), end 2 pin that enter of NCO (10) are connected with the outside frequency control word E that sends here, NCO (10) goes out end 3 pin and is connected with end 3 pin that enter of output clock frequency divider (7), the data address information of NCO (10) output enters to hold 2 pin to be connected through going out end 4 pin and data buffer storage unit (1), for providing, data buffer storage unit (1) reads address, the coefficient address information of NCO (10) output enters to hold 1 pin to be connected through going out end 5 pin and filtering interpolation unit (2), for filtering interpolation unit (2) provide corresponding coefficient address.

2. Incoherent re-sampling device according to claim 1, it is characterized in that: filtering interpolation unit (2) are comprised of filter coefficient table module (4) and convolution module (5), wherein filter coefficient table module (4) enters to hold 1 pin and clock adjustment unit (3) to go out to hold 2 pin to be connected, corresponding certain the group coefficient of the address choice of sending according to clock adjustment unit (3), selected coefficient is exported through end 2 pin that go out of filter coefficient table module (4), sends into the input port 1 of convolution module (5); End 2 pin that enter of convolution module (5) are connected with 3 pin that go out to hold of buffer unit (1), receive the output data of buffer unit (1), and the input data of convolution module (5) are exported through going out end 3 pin after completing convolution with corresponding coefficient.