CN102520337B - Method for accessing register, device and automatic testing machine - Google Patents
Method for accessing register, device and automatic testing machine Download PDFInfo
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Abstract
The invention discloses a method for accessing a register, a device and an automatic testing machine and belongs to the technical field of electronics. The method comprises the following steps of: confirming a basic vector for accessing the register on the basis of an interface which is a connecting interface between a chip and the automatic testing machine; refreshing the basic vector according to an address of a to-be-accessed register, thereby obtaining a refreshed basic vector; and accessing the to-be-accessed register by calling the refreshed basic vector. According to the method, the basic vector for accessing the register is confirmed on the basis of the interface, so that the vector does not need to be confirmed in a simulating form and the confirmation is unlimited by the time for simulating the vector. The refreshed basic vector is obtained by refreshing the basic vector according to the address of the to-be-accessed register and then the to-be-accessed register is accessed by calling the refreshed basic vector, so that the operation of accessing the register is simplified, the operation speed is increased and the test speed is increased.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of method of access register, device and automatic test machine.
Background technology
Along with the fast development of electronic industry, chip output grows with each passing day.In chip volume production process, by ATE(Automatic Test Equipment, automatic test machine) test, can screen defective chip.The standard of screening is to provide some vectors and moves on ATE, and vectorial FAIL represents chip defectiveness.Vector imports after ATE, need to, through debugging after a while, just can make vector sum ATE correctly coordinate, successful execution; In debug process, for accurate orientation problem, need to check chip status, and effective method is that chip register is conducted interviews.
Prior art is on ATE during access register, need first by emulator, the logical code of register place chip to be carried out to emulation output waveform, then by steering volume instrument, the waveform of output is changed into binary file, this binary file is by the vector of the definite access register of emulation; In addition, correct in order to ensure the process of steering volume, also need again binary file to be carried out to emulation, and after emulation is passed through, carry out again the operation of access register.
The mode of access register of the prior art is loaded down with trivial details, extremely inconvenient, and the mode of prior art operation note is limited to and simulates vectorial time restriction, causes whole closed loop procedure reaction too slow.
Summary of the invention
The embodiment of the present invention provides a kind of method, device and automatic test machine of access register, can simplified access register manipulation, improve the speed of accessing operation.Described technical scheme is as follows:
On the one hand, provide a kind of method of access register, described method comprises:
Based on interface, be identified for the basis vector of access register, described interface is the connecting interface between chip and automatic test machine;
According to basis vector described in the address flush of register to be visited, the basis vector that obtains refreshing;
By the described register to be visited of basis vector access refreshing described in calling;
Wherein, describedly according to basis vector described in the address flush of register to be visited, comprise:
If accessing described register manipulation to be visited is read operation, with the address of described register to be visited, replace the address signal initial value in described basis vector;
If accessing described register manipulation to be visited is write operation, with the address of described register to be visited, replaces the address signal initial value in described basis vector, and replace the data-signal initial value in described basis vector with value to be written.
On the other hand, provide a kind of device of access register, described device comprises:
Determining unit, for be identified for the basis vector of access register based on interface, described interface is the connecting interface between chip and automatic test machine;
Refresh unit, for according to the definite basis vector of determining unit described in the address flush of register to be visited, the basis vector that obtains refreshing;
Addressed location, for the described register to be visited of the basis vector refreshing access obtaining by calling described refresh unit;
Wherein, described refresh unit comprises:
The first refresh module, if be read operation for accessing described register manipulation to be visited, replaces the address signal initial value in described basis vector with the address of described register to be visited;
The second refresh module, if be write operation for accessing described register manipulation to be visited, with the address of described register to be visited, replace the address signal initial value in described basis vector, and replace the data-signal initial value in described basis vector with value to be written.
On the one hand, also provide a kind of automatic test machine again, comprised device and the proving installation of access register;
The device of described access register is as the device of above-mentioned access register;
Described proving installation, completes after the access of register to be visited for the device in described access register, and the chip at described register place to be visited is tested.
The embodiment of the present invention is by being identified for the basis vector of access register based on interface, without determine vector by emulation, also without being limited to the vectorial time that simulates, and by the basis vector that obtains refreshing according to the address flush basis vector of register to be visited, by calling the basis vector refreshing, access register to be visited again, thereby simplified the operation of access register, and then improved operating speed.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the method flow diagram of the access register that provides of the embodiment of the present invention one;
Fig. 2 is the method flow diagram of the access register that provides of the embodiment of the present invention two;
Fig. 3 is the method flow diagram of the access register that provides of the embodiment of the present invention three;
Fig. 4 reads sequential schematic diagram for what the embodiment of the present invention three provided;
Fig. 5 is the structural representation of the device of the access register that provides of the embodiment of the present invention four;
Fig. 6 is the structural representation of the refresh unit that provides of the embodiment of the present invention four;
Fig. 7 is the structural representation of the first refresh module of providing of the embodiment of the present invention four;
Fig. 8 is the structural representation of the second refresh module of providing of the embodiment of the present invention four;
Fig. 9 is the structural representation of the automatic test machine that provides of the embodiment of the present invention five.
Embodiment
For making goal of the invention of the present invention, feature, advantage can be more obvious and understandable, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, but not whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment mono-
The present embodiment provides a kind of method of access register, and referring to Fig. 1, method flow can comprise:
101: based on interface, be identified for the basis vector of access register, described interface is the connecting interface between chip and automatic test machine;
102: according to this basis vector of the address flush of register to be visited, the basis vector that obtains refreshing;
Wherein, because the described basis vector refreshing is to obtain by the address flush basis vector according to register to be visited, therefore, described in the basis vector that refreshes be applicable to register to be visited.
103: by the described register to be visited of basis vector access refreshing described in calling.
Further, the periodicity information that while being identified for the basis vector of access register based on interface, definite basis vector at least comprises chip selection signal, reads enable signal, writes enable signal, address signal, data-signal and interface signal keep low and high level;
Wherein, interface signal comprises chip selection signal, reads enable signal, writes enable signal, address signal and data-signal, and address signal and data-signal are initial value.
Particularly, the address flush basis vector according to register to be visited, can comprise:
If accessing this register manipulation to be visited is read operation, with the address of this register to be visited, replace the address signal initial value in basis vector;
If accessing this register manipulation to be visited is write operation, with the address of this register to be visited, replaces the address signal initial value in basis vector, and replace the data-signal initial value in basis vector with value to be written.
Further, with the address of this register to be visited, replace the address signal initial value in basis vector, can comprise:
The address of this register to be visited is passed to the bottom layer driving of writing in advance, by the bottom layer driving of writing in advance, with the address of this register to be visited, replace the address signal initial value in basis vector;
The address signal initial value in basis vector is replaced in address with this register to be visited, and replaces the data-signal initial value in basis vector with value to be written, can comprise:
The address of this register to be visited and value to be written are passed to the bottom layer driving of writing in advance, by the bottom layer driving of writing in advance, with the address of register to be visited, replace the address signal initial value in basis vector, and replace the data-signal initial value in basis vector with value to be written.
Wherein, the address of this register to be visited is passed to the bottom layer driving of writing in advance, can comprise:
By the top code of writing in advance, the address of this register to be visited is passed to the bottom layer driving of writing in advance;
The address of this register to be visited and value to be written are passed to the bottom layer driving of writing in advance, comprising:
By the top code of writing in advance, the address of this register to be visited and value to be written are passed to the bottom layer driving of writing in advance.
The method that the present embodiment provides can realize by processor (such as central processor CPU) or special-purpose circuit.
The method that the present embodiment provides, by be identified for the basis vector of access register based on interface, without determine vector by emulation, also without being limited to the vectorial time that simulates, and by the basis vector that obtains refreshing according to the address flush basis vector of register to be visited, by calling the basis vector refreshing, access register to be visited again, thereby simplified the operation of access register, and then improved operating speed.
The method providing in order to set forth in more detail the present embodiment, below, in conjunction with foregoing, by following embodiment bis-and embodiment tri-, the method that the present embodiment is provided is elaborated, and refers to following embodiment bis-and embodiment tri-:
Embodiment bis-
The present embodiment provides a kind of method of access register, and wherein, the operation of access register comprises write operation and read operation, and what the present embodiment only be take access register is operating as write operation as example, and the method that the present embodiment is provided is illustrated.Referring to Fig. 2, the method flow that the present embodiment provides is specific as follows:
201: based on interface, be identified for the basis vector of access register, described interface is the connecting interface between chip and automatic test machine;
Wherein, the connecting interface between chip and automatic test machine can be serial ports, for example, and SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) interface; Also can be parallel port, for example, HOST interface.For convenience of explanation, the present embodiment be take HOST interface and is illustrated as example.
In addition, the present embodiment does not limit the content of the basis vector for access register of determining based on interface, the INTEL pattern of protocol interface HOST interface of standard of take is example, and the basis vector for access register of determining during write operation can be as shown in table 1 below:
Table 1
In table 1, PHOST_CS_N is chip selection signal, PHOST_OE_N is for reading enable signal, PHOST_WE_N is for writing enable signal, PHOST_ADDR_ is address signal, PHOST_DATA_ is data-signal, rpt(10), rpt(30), rpt(10) the periodicity information that each interface signal of HOST keeps low and high level is described respectively, it determines chip selection signal, reads enable signal, writes the periodicity that enable signal keeps low and high level according to features, and it is grouped together and forms the sequential based on HOST interface.As can be seen here, the periodicity information that all applicable to accessing all registers in order to guarantee definite basis vector, the basis vector of definite access register at least comprises chip selection signal, reads enable signal, writes enable signal, address signal, data-signal and interface signal keep low and high level; For register to be visited, now the address signal in basis vector and data-signal are initial value, and during write operation, the value that test machine is write needs is put on data-signal.
PHOST_CS_N in table 1, PHOST_OE_N and PHOST_WE_N are 1, identify these signaling interfaces in disarmed state, if 0, identify these signaling interfaces in effective status, certainly, herein can also be with 0 id signal interface in disarmed state, with 1 id signal interface in effective status, or adopting other identification means, the present embodiment is not done concrete restriction to this.In addition, the value of PHOST_ADDR and PHOST_DATA_ is initial value 0X0, and this 0x0 is 0 in 16 systems, certainly, can also PHOST_ADDR and the initial value of PHOST_DATA_ be set to other values, concrete restriction is not done in this enforcement equally to this.
202: by the top code of writing in advance, the address of register to be visited and value to be written are passed to the bottom layer driving of writing in advance;
For this step, the present embodiment does not limit the top code of writing in advance and bottom layer driving, the address of register to be visited and value to be written is not limited equally.During specific implementation, with the address of register to be visited and value to be written, be respectively 0x25001,0x1 is example, and top code can be as follows:
By above-mentioned top code, can find out, top code is by being used write_reg (0x25001,0x1) that register address 0x25001 to be visited and value 0x1 to be written are passed to bottom layer driving.
203: by bottom layer driving, according to the address of register to be visited and value to be written, refresh basis vector, the basis vector that obtains refreshing;
For this step, the mode that the present embodiment does not refresh basis vector to bottom layer driving according to the address of register to be visited and value to be written limits.During specific implementation, the address signal initial value in basis vector is replaced in the address of the register that bottom layer driving can be to be visited, with value to be written, replaces the data-signal initial value in basis vector.
Particularly, by the top code in above-mentioned steps 202, the address of register to be visited and value to be written are passed to after the bottom layer driving of writing in advance, bottom layer driving can be by using label_edit that the address 0x25001 of register to be visited and value 0x1 to be written are brushed respectively to the 5th, 6 row into the basis vector shown in Fig. 1, specific as follows shown in:
Bottom layer driving is as follows:
By bottom layer driving, to the refreshing of basis vector, obtain one and comprise the write address 0x25001 refreshing, the basis vector of the value of writing 0x1, now, the basis vector refreshing can be as shown in Table 2 below:
Table 2
In table 2, the PHOST_CS_N of the 3rd row is 0, identifies this sheet and elects as effectively, and PHOST_WE_N is 0, is designated to write to enable.
204: by calling the basis vector refreshing, register to be visited is carried out to write operation.
For this step, the content of the basis vector refreshing shown in associative list 2, because the address signal in this basis vector refreshing and data-signal are respectively the address of register to be visited and value to be written, therefore, the basis vector refreshing by calling this, make its register to be visited that is 0x25001 by value 0x1 writing address to be written, thereby realize the write operation to register to be visited.
The method that the present embodiment provides can realize by processor (such as central processor CPU) or special-purpose circuit.
The method that the present embodiment provides, by be identified for the basis vector of access register based on interface, without determine vector by emulation, also without being limited to the vectorial time that simulates, and by the basis vector that obtains refreshing according to the address flush basis vector of register to be visited, by calling the basis vector refreshing, access register to be visited again, thereby simplified the operation of access register, and then improved operating speed.
Embodiment tri-
The present embodiment provides a kind of method of access register, and what the method be take access register is operating as read operation as example, and the method that the present embodiment is provided is illustrated.Referring to Fig. 3, the method flow that the present embodiment provides is specific as follows:
301: based on interface, be identified for the basis vector of access register, described interface is the connecting interface between chip and automatic test machine;
For this step, with the description of step 201 in above-described embodiment two, the connecting interface between chip and automatic test machine can be serial ports, for example, and SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) interface; Also can be parallel port, for example, HOST interface.For convenience of explanation, the present embodiment still be take HOST interface and is illustrated as example.
In addition, the present embodiment does not limit the content of the basis vector for access register of determining based on interface equally, the periodicity information that all applicable to all registers in order to guarantee definite basis vector, it at least comprises chip selection signal, reads enable signal, writes enable signal, address signal, data-signal and interface signal keep low and high level; For register to be visited, now the address signal in basis vector and data-signal are initial value.The INTEL pattern of protocol interface HOST interface of standard of take is example, the basis vector of the register that read operation is corresponding as shown in Table 3 below:
Table 3
In table 3, PHOST_CS_N is chip selection signal, PHOST_OE_N is for reading enable signal, PHOST_WE_N is for writing enable signal, PHOST_ADDR_ is address signal, PHOST_DATA_ is data-signal, rpt(10), rpt(30), rpt(10) the periodicity information that each interface signal of HOST keeps low and high level is described respectively, each project determines chip selection signal, reads enable signal, writes the periodicity that enable signal keeps low and high level according to features, it is grouped together and forms the sequential based on HOST interface, and this HOST interface is read sequential can be as shown in Figure 4.During read operation, the data that chip returns are put on data-signal.
PHOST_CS_N in table 3, PHOST_OE_N and PHOST_WE_N are 1, identify these signaling interfaces in disarmed state, if 0, identify these signaling interfaces in effective status, certainly, herein can also be with 0 id signal interface in disarmed state, with 1 id signal interface in effective status, or adopting other identification means, the present embodiment is not done concrete restriction to this.In addition, the value of PHOST_ADDR is initial value 0X0, and this 0x0 is 0 in 16 systems, why PHOST_DATA_ is X, and sign is not construed as limiting this, certainly, can also PHOST_ADDR and the value of PHOST_DATA_ be set to other values, concrete restriction is not done in this enforcement equally to this.
302: by the top code of writing in advance, the address of register to be visited is passed to the bottom layer driving of writing in advance;
For this step, the present embodiment does not limit the top code of writing in advance and bottom layer driving, the address of register to be visited is not limited equally.During specific implementation, take reading address as two of 0x2500a and 0x25510 registers to be visited be example, top code can be as follows:
By above-mentioned top code and bottom layer driving, can be found out, having read address is 0x2500a and two registers to be visited of 0x25510, when the value of these two registers to be visited is respectively 0 and 3, and vectorial PASS, otherwise vectorial FAIL.
303: by bottom layer driving according to the address flush basis vector of register to be visited, the basis vector that obtains refreshing;
For this step, the present embodiment does not limit according to the mode of the address flush basis vector of register to be visited bottom layer driving.During specific implementation, the address signal initial value in basis vector is replaced in the address of the register that bottom layer driving can be to be visited.
Particularly, by the top code in above-mentioned steps 302, the address of register to be visited is passed to after the bottom layer driving of writing in advance, bottom layer driving can be by utilizing label_edit to refresh basis vector, specifically can be as follows:
The basis vector as shown in table 3 that the step 302 of take is determined is example, and because being has read two registers to be visited, therefore, this step is after bottom layer driving refreshes basis vector, and the basis vector refreshing obtaining is respectively as shown in table 4 and table 5 below:
Table 4
Table 5
In the 3rd row of table 4 and table 5, PHOST_CS_N is 0, identifies this chip selection signal for effective, and PHOST_OE_N is 0, is designated and reads to enable.
304: by calling the basis vector refreshing, register to be visited is carried out to read operation.
For this step, the content of the basis vector refreshing shown in associative list 4 and table 5, because the address signal in this basis vector refreshing is the address of register to be visited, therefore, by calling the basis vector refreshing, making its reading address is the value of 0x2500a and two registers to be visited of 0x25510, thereby realize, register to be visited is carried out to read operation.
In addition, the method that the present embodiment provides is after turning back on data-signal by the register value to be visited reading, and the method that the present embodiment provides can also recycle digital_capture technology by under data acquisition, returns to user.
The method that the present embodiment provides can realize by processor (such as central processor CPU) or special-purpose circuit.
The method that the present embodiment provides, by be identified for the basis vector of access register based on interface, without determine vector by emulation, also without being limited to the vectorial time that simulates, and by the basis vector that obtains refreshing according to the address flush basis vector of register to be visited, by calling the basis vector refreshing, access register to be visited again, thereby simplified the operation of access register, and then improved operating speed.
Embodiment tetra-
The present embodiment provides a kind of device of access register, and this device is for carrying out the method that above-described embodiment one, embodiment bis-and embodiment tri-provide, and referring to Fig. 5, this device comprises:
Determining unit 501, for be identified for the basis vector of access register based on interface, described interface is the connecting interface between chip and automatic test machine;
Further, the periodicity information that the definite basis vector of determining unit 501 at least comprises chip selection signal, reads enable signal, writes enable signal, address signal, data-signal and interface signal keep low and high level;
Wherein, interface signal is chip selection signal, read enable signal, write enable signal, address signal and data-signal, and address signal and data-signal are initial value.
Particularly, referring to Fig. 6, refresh unit 502, comprising:
The first refresh module 502a, if be read operation for accessing register manipulation to be visited, replaces the address signal initial value in basis vector with the address of register to be visited;
The second refresh module 502b, if be write operation for accessing register manipulation to be visited, replace the address signal initial value in basis vector with the address of register to be visited, and replaces the data-signal initial value in basis vector with value to be written.
Further, referring to Fig. 7, the first refresh module 502a, comprising:
First transmits submodule 502a1, for the address of register to be visited being passed to the bottom layer driving of writing in advance;
First refreshes submodule 502a2, and the address signal initial value of basis vector is replaced in the address of the register to be visited transmitting with the first transmission submodule 502a1 for the bottom layer driving by writing in advance;
Referring to Fig. 8, the second refresh module 502b, comprising:
Second transmits submodule 502b1, for the address of register to be visited and value to be written are passed to the bottom layer driving of writing in advance;
Second refreshes submodule 502b2, for replacing the address signal initial value of basis vector by the bottom layer driving of writing in advance with the address of the register to be visited of the second transmission submodule 502b1 transmission, and replace the data-signal initial value in basis vector with value to be written.
Particularly, first transmits submodule 502a1, for the top code by writing in advance, the address of register to be visited is passed to the bottom layer driving of writing in advance;
Second transmits submodule 502b1, for the top code by writing in advance, the address of register to be visited and value to be written is passed to the bottom layer driving of writing in advance.
The device that the present embodiment provides can be processor or special-purpose circuit etc.
The device that the present embodiment provides, by be identified for the basis vector of access register based on interface, without determine vector by emulation, also without being limited to the vectorial time that simulates, and by the basis vector that obtains refreshing according to the address flush basis vector of register to be visited, by calling the basis vector refreshing, access register to be visited again, thereby simplified the operation of access register, and then improved operating speed.
Embodiment five
The present embodiment provides a kind of automatic test machine, and referring to Fig. 9, this automatic test machine comprises: the device 901 of access register and proving installation 902;
The device of the access register that wherein, the device 901 of access register provides as above-described embodiment four;
Proving installation 902, completes after the access of register to be visited for the device 901 in access register, and the chip at this register place to be visited is tested.Concrete test process can, with reference to the flow process of existing automatic test machine test chip, repeat no more herein.
The device 901 of the access register that the present embodiment provides and proving installation 902 can be processor or special-purpose circuit etc.
The automatic test machine that the present embodiment provides, device by access register is identified for the basis vector of access register based on interface, without determine vector by emulation, also without being limited to the vectorial time that simulates, and by the basis vector that obtains refreshing according to the address flush basis vector of register to be visited, by calling the basis vector refreshing, access register to be visited again, thereby simplified the operation of access register, improve operating speed, and then improved test speed.
It should be noted that: the device of the access register that above-described embodiment provides is when access register, only the division with above-mentioned each functional module is illustrated, in practical application, can above-mentioned functions be distributed and by different functional modules, completed as required, the inner structure that is about to device is divided into different functional modules, to complete all or part of function described above.In addition, the device of the access register that above-described embodiment provides and the embodiment of the method for access register belong to same design, and its specific implementation process refers to embodiment of the method, repeats no more here.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
Part steps in the embodiment of the present invention, can utilize software to realize, and corresponding software program can be stored in the storage medium can read, as CD or hard disk etc.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a method for access register, is characterized in that, described method comprises:
Based on interface, be identified for the basis vector of access register, described interface is the connecting interface between chip and automatic test machine;
According to basis vector described in the address flush of register to be visited, the basis vector that obtains refreshing;
By the described register to be visited of basis vector access refreshing described in calling;
Wherein, describedly according to basis vector described in the address flush of register to be visited, comprise:
If accessing described register manipulation to be visited is read operation, with the address of described register to be visited, replace the address signal initial value in described basis vector;
If accessing described register manipulation to be visited is write operation, with the address of described register to be visited, replaces the address signal initial value in described basis vector, and replace the data-signal initial value in described basis vector with value to be written.
2. method according to claim 1, it is characterized in that, the periodicity information that described while being identified for the basis vector of access register based on interface, described basis vector at least comprises chip selection signal, reads enable signal, writes enable signal, address signal, data-signal and interface signal keep low and high level;
Wherein, described interface signal comprises described chip selection signal, reads enable signal, writes enable signal, address signal and data-signal, and described address signal and data-signal are initial value.
3. method according to claim 1, is characterized in that, the address signal initial value that replace in described basis vector the described address with described register to be visited comprises:
The address of described register to be visited is passed to the bottom layer driving of writing in advance, by described bottom layer driving of writing in advance, with the address of described register to be visited, replace the address signal initial value in described basis vector;
The address signal initial value in described basis vector is replaced in the described address with described register to be visited, and the data-signal initial value of replacing in described basis vector with value to be written comprises:
The bottom layer driving of writing in advance described in the address of described register to be visited and described value to be written are passed to, by described bottom layer driving of writing in advance, with the address of described register to be visited, replace the address signal initial value in described basis vector, and replace the data-signal initial value in described basis vector with described value to be written.
4. method according to claim 3, is characterized in that, the described address by described register to be visited passes to the bottom layer driving of writing in advance and comprises:
The bottom layer driving of writing in advance described in the address of described register to be visited being passed to by the top code of writing in advance;
Described bottom layer driving of writing in advance described in the address of described register to be visited and described value to be written are passed to, comprising:
The bottom layer driving of writing in advance described in the address of described register to be visited and described value to be written being passed to by described top code of writing in advance.
5. a device for access register, is characterized in that, described device comprises:
Determining unit, for be identified for the basis vector of access register based on interface, described interface is the connecting interface between chip and automatic test machine;
Refresh unit, for according to the definite basis vector of determining unit described in the address flush of register to be visited, the basis vector that obtains refreshing;
Addressed location, for the described register to be visited of the basis vector refreshing access obtaining by calling described refresh unit;
Wherein, described refresh unit comprises:
The first refresh module, if be read operation for accessing described register manipulation to be visited, replaces the address signal initial value in described basis vector with the address of described register to be visited;
The second refresh module, if be write operation for accessing described register manipulation to be visited, with the address of described register to be visited, replace the address signal initial value in described basis vector, and replace the data-signal initial value in described basis vector with value to be written.
6. device according to claim 5, it is characterized in that the periodicity information that the definite basis vector of described determining unit at least comprises chip selection signal, reads enable signal, writes enable signal, address signal, data-signal and interface signal keep low and high level;
Wherein, described interface signal comprises described chip selection signal, reads enable signal, writes enable signal, address signal and data-signal, and described address signal and data-signal are initial value.
7. device according to claim 6, is characterized in that, described the first refresh module comprises:
First transmits submodule, for the address of described register to be visited being passed to the bottom layer driving of writing in advance;
First refreshes submodule, for replacing the address signal initial value of described basis vector by described bottom layer driving of writing in advance with the described first address of transmitting the register described to be visited of submodule transmission;
Described the second refresh module comprises:
Second transmits submodule, for the bottom layer driving of writing in advance described in the address of described register to be visited and described value to be written are passed to;
Second refreshes submodule, for replacing the address signal initial value of described basis vector by described bottom layer driving of writing in advance with the described second address of transmitting the register described to be visited of submodule transmission, and replace the data-signal initial value in described basis vector with described value to be written.
8. device according to claim 7, is characterized in that, described first transmits submodule, the bottom layer driving of writing in advance described in for the top code by writing in advance, the address of described register to be visited being passed to;
Described second transmits submodule, for the bottom layer driving of writing in advance described in the address of described register to be visited and described value to be written being passed to by described top code of writing in advance.
9. an automatic test machine, is characterized in that, comprises device and the proving installation of access register;
The device of the access register of the device of described access register as described in claim 5-8 any one;
Described proving installation, completes after the access of register to be visited for the device in described access register, and the chip at described register place to be visited is tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110359784.3A CN102520337B (en) | 2011-11-14 | 2011-11-14 | Method for accessing register, device and automatic testing machine |
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