JP2012226658A - Test device, verification model development method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily construct a verification environment corresponding to each of various interfaces in a short period.SOLUTION: A test device includes a signal input/output control part 131 for inputting/outputting a signal between the test device and a test object model 11, a storage part 132 for storing a program P which specifies a function of an interface to be executed by the signal input/output control part 131 and a pseudo processor 133 for setting the signal input/output control part 131 according to the program P. A pseudo model 13 which simulates an operation of a device accessed by the test object model 11 is provided.

Description

  The present invention relates to a test apparatus, a verification model development method, and a program.

  Conventionally, when testing a semiconductor integrated circuit such as SoC (System on a Chip), a pseudo model that simulates the operation of the device accessed by the device under test (DUT) is built on an emulator or simulator. It is known to conduct tests. Such a pseudo model is also called an external model.

  Many external models are used during tests such as SoC. For example, an interface for an SD card, SDRAM (Synchronous Dynamic Random Access Memory), PCI (Peripheral Component Interconnect), AMBA (Advanced Microcontroller Bus Architecture), etc. are simulated as external models.

  Such an external model is described in a hardware description language such as Verilog, VHDL (VHSIC (Very High Speed Integrated Circuits) Hardware Description Language), or SystemC.

  In addition, an acceleration is known in which an external model described in SystemC or the like is built on a simulator and a test is performed with a DUT built on an emulator. In acceleration, there is a method of connecting a simulator and an emulator with a signal line. As another acceleration method, there is known a method in which an emulator and a simulator are cooperatively operated at a transaction level using an SCE-MI (Standard Co-Emulation Modeling Interface) protocol in order to speed up verification.

JP 2010-231607 A JP 2002-41321 A JP 2005-18485 A

However, the conventional method has a problem that it takes time to construct a verification environment including an external model.
For example, a hardware description language has a large amount of description, and it takes time to create and modify an external model. In the case of using acceleration, the SCE-MI part also needs to be described in a hardware description language, which is difficult to correct when the external model is changed, and it takes time to reconstruct the verification model.

  According to one aspect of the invention, a pseudo model for simulating the operation of an apparatus accessed by a model under test is provided, and the pseudo model is a signal input / output that inputs and outputs signals to and from the model under test. A test comprising: a control unit; a storage unit storing a program that specifies an interface function executed by the signal input / output control unit; and a pseudo processor that sets the signal input / output control unit according to the program An apparatus is provided.

  According to another aspect of the invention, a computer specifies a signal input / output control unit for inputting / outputting a signal to / from a model under test, and an interface function executed by the signal input / output control unit. A pseudo-model that simulates the operation of the device accessed by the model under test, and the pseudo-processor generates a pseudo-model according to the program. A verification model development method for setting is provided.

  Further, according to one aspect of the invention, there is provided a program for designating a function of an interface executed by the signal input / output control unit, a signal input / output control unit for inputting / outputting a signal to / from a model under test. Provided is a program that has a stored storage unit and a pseudo processor that sets the signal input / output control unit according to the program, and that functions as a pseudo model that simulates the operation of the device accessed by the model under test Is done.

  According to the disclosed test apparatus, verification model development method, and program, a verification environment corresponding to various interfaces can be easily constructed in a short time.

It is a figure which shows an example of a test apparatus. It is a figure which shows an example of the development method of the verification model using an external model. It is a timing chart which shows an example of the operation | movement at the time of the test of a test apparatus. It is a figure which shows an example of control of a DUT clock. It is a figure which shows an example of a signal input / output control part. It is a figure which shows the example of a setting of an interrupt register and a clock control register. It is a figure which shows the example of a setting of an input register. It is a figure which shows the example of a setting of an output register. It is a figure which shows an example of a program. It is an example of an interrupt function included in a register control program. It is a flowchart which shows the flow of a process of an example of initialization operation | movement. It is a flowchart which shows an example of the process of the external model in every clock cycle of DUT. It is a flowchart which shows an example of a program process. It is a figure which shows the example of a connection with DUT at the time of applying an external model to the interface for SD cards. It is a figure which shows the operation example of the test apparatus when an external model is used as the interface for SD cards. It is a figure which shows an example of the external model corresponding to a some interface function. It is a figure which shows an example of the hardware of a computer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an example of a test apparatus.
The test apparatus 10 is a computer such as an emulator, for example, and includes a model to be tested (hereinafter abbreviated as DUT) 11, a clock generator 12, and a pseudo model (hereinafter referred to as an external model) 13. The DUT 11 is data (for example, a net list) of a semiconductor integrated circuit such as a designed SoC, and is mapped to a logic development board having rewritable logic elements of the test apparatus 10.

The clock generator 12 generates a clock signal to be supplied to the DUT 11.
The external model 13 includes a signal input / output control unit 131, a storage unit 132, a pseudo processor 133, and a bus 134. These are described in a hardware description language capable of logical synthesis, such as Verilog or VHDL.

  The signal input / output control unit 131 inputs and outputs signals (interface signals) with the DUT 11. As will be described in detail later, the signal input / output control unit 131 includes a memory, a register, a buffer, a counter, a control unit, and the like. The signal input / output control unit 131 has a function of outputting a clock control signal to the clock generation unit 12 and a function of outputting an interrupt instruction to the pseudo processor 133.

  The storage unit 132 stores a program P that specifies the function of the interface executed by the signal input / output control unit 131. The program P is described in a programming language with a high level of abstraction such as C language. The program P describes values to be set in the register of the signal input / output control unit 131, program processing performed by the pseudo processor 133, and the like. The program P is compiled and stored in the storage unit 132.

  The pseudo processor 133 sets the signal input / output control unit 131 according to the program P stored in the storage unit 132. When the pseudo processor 133 receives an interrupt command from the signal input / output control unit 131 after setting the signal input / output control unit 131, the pseudo processor 133 performs the program processing described in the program P as the interrupt processing. The pseudo processor 133 is, for example, a model that simulates a CPU (Central Processing Unit).

The bus 134 transmits signals between the signal input / output control unit 131, the storage unit 132, and the pseudo processor 133.
FIG. 2 is a diagram illustrating an example of a verification model development method using an external model.

First, for example, the test apparatus 10 generates an external model 13 as shown in FIG. 1 (step S1).
For example, the test apparatus 10 inputs a setting file including information on the signal input / output control unit 131 edited by the designer according to the interface used (step S1a). In the setting file, the number of interface signal lines and the circuit quantity such as the number and capacity of buffers or registers are specified. For example, when a plurality of interfaces are assumed, the number of buffers or registers to be used is designated in accordance with the maximum number of interface signal lines. In addition, the capacity of the buffer or register is specified according to the amount of data to be acquired or the amount of set values.

Thereby, it is possible to suppress generation of useless circuits in the generated external model 13.
The test apparatus 10 executes a generation tool that generates a module or the like (for example, one created with perl or the like), and generates the external model 13 (step S1b).

  The external model 13 may be generated using a computer different from the test apparatus 10. In that case, the test apparatus 10 captures the generated external model 13 via, for example, a network.

  Thereafter, the pseudo processor 133 sets the signal input / output control unit 131 according to the program P stored in the storage unit 132 (step S2). As a result, a verification model having the external model 13 that simulates the operation of the device accessed by the DUT 11 is generated.

  According to the test device 10 and the verification model development method, the pseudo processor 133 sets the function of the signal input / output control unit 131 of the external model 13 that simulates the operation of the device accessed by the DUT 11 according to the program P. To do. As a result, the number of man-hours can be reduced as compared with the case where various external models are developed in a hardware description language, and a verification environment corresponding to various interfaces can be easily constructed in a short period of time.

  For example, the amount of code can be reduced to about 1/7 as compared with the case where the external model is created entirely in a hardware description language. Moreover, since an emulator is used, testing can be performed at high speed.

  Further, it becomes possible to deal with various external models only by correcting the program P, and the verification environment can be easily corrected and changed. Further, the pseudo processor 133 can easily adjust the timing by setting the output timing of the signal output to the DUT 11 in the signal input / output control unit 131 according to the program P.

The external model 13 generated as described above performs, for example, the following operation according to the setting of the signal input / output control unit 131 when the DUT 11 is tested.
The DUT 11 is tested according to a test bench described in a hardware description language, for example.

FIG. 3 is a timing chart showing an example of the operation of the test apparatus during the test.
A clock signal (DUT clock) to the DUT 11 generated by the clock generation unit 12, a clock signal (external model clock) input to the external model 13, and a signal input / output control unit 131 from the DUT 11 that causes an operation of the external model 13. The input signal to is shown. In addition, a clock control signal output from the signal input / output control unit 131 to the clock generation unit 12 and an interrupt signal output from the signal input / output control unit 131 to the pseudo processor 133 are shown. In addition, an output signal output from the signal input / output control unit 131 to the DUT 11, a value of an output buffer of the signal input / output control unit 131, and a program processing timing of the pseudo processor 133 are shown.

  The operation factor of the external model 13 is a change in an input signal that is an interface signal, a time elapsed after the input signal has changed, and the like in the process of step S2 in FIG. 2 described above. It is set in a register (not shown) of the control unit 131. In the example of FIG. 3, it is assumed that the operation factor of the external model 13 is that the input signal to the signal input / output control unit 131 becomes deasserted (in the example of FIG. 3, L (Low) level).

  When the input signal becomes L level at timing t1, the signal input / output control unit 131 asserts the clock control signal (H (High) level in the example of FIG. 3). Thereby, the clock generator 12 stops the DUT clock (timing t2).

  When the input signal is deasserted, the signal input / output control unit 131 asserts an interrupt signal (timing t3). Thereby, the pseudo processor 133 performs a program process based on the description of the program P stored in the storage unit 132. The example of FIG. 3 shows an example of a program process for changing the value of the output buffer of the signal input / output control unit 131 from 0 to 1 at a certain timing t4.

  When the program process ends (timing t5), the signal input / output control unit 131 deasserts the clock control signal. As a result, the clock generator 12 resumes the supply of the DUT clock to the DUT 11.

FIG. 4 is a diagram illustrating an example of control of the DUT clock.
In FIG. 4, the blocks on the straight line connected to the DUT 11 and the external model 13 indicate processing in each part.

  When the operation factor of the external model 13 as described above is generated by the DUT 11 (timing T1), the external model 13 stops the DUT clock by the clock control signal (timing T2) and executes the program processing. When the program processing is completed, the external model 13 restarts the DUT clock by the clock control signal (timing T3).

When the operating factor of the external model 13 occurs again (timing T4), the DUT clock is stopped (timing T5), and the program processing of the external model 13 is performed.
If parallel processing with the DUT 11 is possible during the program processing of the external model 13, the DUT clock is restarted by the clock control signal in the middle of the program processing (timing T6).

  Thereafter, an operating factor of the external model 13 occurs (timing T7), and when the DUT 11 and the external model 13 cannot be operated in parallel, the DUT clock is stopped (timing T8), and the operation of the DUT 11 is stopped. When the program processing is completed, the DUT clock is restarted (timing T9), and the operation of the DUT 11 is started.

  By controlling the DUT clock as described above, the time difference between the program processing and the DUT operation can be adjusted. If parallel processing of the external model 13 and the DUT 11 is possible, for example, the DUT clock is restarted in the middle of the program processing, and the parallel processing between the DUT 11 and the external model is performed, thereby stopping the DUT clock. Speed reduction can be suppressed.

  By the control shown in FIGS. 3 and 4 as described above, the generated external model 13 simulates a function as a device accessed by the DUT 11. The DUT 11 operates with the external model 13 as an access partner, and signals of each part in the DUT 11 at that time and signals input / output from the DUT 11 are read, and the DUT 11 is verified.

Hereinafter, the external model 13 that realizes the above operation will be described in more detail.
FIG. 5 is a diagram illustrating an example of the signal input / output control unit.
The signal input / output control unit 131 includes an interrupt register 20, a clock control register 21, a plurality of input registers 22-1 to 22-n, input counters 23-1 to 23-n, input buffers 24-1 to 24-n, and outputs. Registers 25-1 to 25-n are included. Further, the signal input / output control unit 131 outputs the output buffers 27-1 to 27-n and the two output counters 26a-1 to 26a-n and 26b- to the output registers 25-1 to 25-n, respectively. 1 to 26b-n. The signal input / output control unit 131 includes an interrupt mask register 28.

  The interrupt register 20 holds the type of interrupt. When the pseudo processor 133 receives the interrupt instruction, the pseudo processor 133 refers to the interrupt register 20 to identify the type of interrupt.

  The clock control register 21 stores a value of a clock control signal that controls whether or not the clock generator 12 is allowed to generate a DUT clock. For example, the value is set so that the DUT clock is restarted at the end of the program processing by the external model 13.

In the input registers 22-1 to 22-n, settings relating to the input signal from the DUT 11 are performed. Interrupt timing and interrupt factors are also set.
The input counters 23-1 to 23-n perform a count operation in synchronization with a clock signal (not shown) according to the set values of the input registers 22-1 to 22-n.

The input buffers 24-1 to 24-n hold the input signal from the DUT 11 by sequentially shifting the bits every clock cycle of the DUT clock.
In the output registers 25-1 to 25-n, control of timing of data output to the DUT 11 and information related to interrupts are set.

  The output counters 26a-1 to 26a-n and 26b-1 to 26b-n perform a count operation in synchronization with a clock signal (not shown) according to the set values of the output registers 25-1 to 25-n. The output counters 26a-1 to 26a-n and 26b-1 to 26b-n are set to 2 for each output register 25-1 to 25-n in order to count the timing of the output signal to the DUT 11 and the interrupt timing. One is provided.

The output buffers 27-1 to 27-n hold information to be output to the DUT 11 by sequentially shifting the bits every clock cycle of the DUT clock.
The interrupt mask register 28 determines whether or not to generate an interrupt due to an interrupt generation factor (for example, an interrupt generated according to a counter value or an interrupt generated by a signal from the DUT 11). Is a register to be set.

In addition to the above, the signal input / output control unit 131 includes, for example, a control unit and a memory, but is not illustrated.
The number of input registers 22-1 to 22-n and output registers 25-1 to 25-n are both n, but they may be different. Similarly, the number of input buffers 24-1 to 24-n and output buffers 27-1 to 27-n may be different.

  Also, a plurality of input buffers 24-1 to 24-n, input counters 23-1 to 23-n, output buffers 27-1 to 27-n, output counters 26a-1 to 26a-n, 26b-1 to 26b- One input register and output register may be provided for n.

  FIG. 6 is a diagram illustrating a setting example of the interrupt register and the clock control register. FIG. 6A shows a setting example of the interrupt register 20, and FIG. 6B shows a setting example of the clock control register 21.

  In the interrupt register 20, bits [n−1: 0] having a bit width n indicated by the name “interrupt by input signal” are areas in which interrupt information by n input signals is set. Yes. For example, when an interrupt due to the nth input signal occurs, “1” is set to the nth bit.

  In addition, interrupt information controlled by the input counters 23-1 to 23-n is set in bits [2n-1: n] having a bit width n indicated by the name "input counter control interrupt". Furthermore, the bits [3n-1: 2n] of the bit width n indicated by the name "output counter control interrupt" are assigned to the output counters 26a-1 to 26a-n or the output counters 26b-1 to 26b-n. Information on interrupts by control is set.

  On the other hand, in the clock control register 21, the value of the clock control signal for controlling whether or not to allow the clock generator 12 to generate the DUT clock is indicated in the bit [0] indicated by the name "DUT clock permission". Stored.

FIG. 7 is a diagram illustrating a setting example of the input register.
FIG. 7 shows areas in which settings relating to interrupts are performed in the input registers 22-1 to 22-n.

In the 33-bit bits [64:32] indicated by the name “count value”, a count value used in count interrupt control is set.
The 7-bit bits [31:25] indicated by the name “reserved” are an unused area.

  The 5-bit bits [24:20] indicated by the name “signal interrupt control” set in what state the input signal from the DUT 11 is to be asserted.

  For example, when “0” is set in the bits [24:20], the interrupt signal by the input signal is not asserted. When bits [24:20] are set to “1”, an interrupt signal is asserted when the input signal changes. When bits [24:20] are set to “2”, the interrupt signal is asserted when the input signal changes to 0. When “3” is set in bits [24:20], the interrupt signal is asserted when the input signal changes to 1. When bits [24:20] are set to “4”, an interrupt signal is asserted when the input signal changes to a certain value X. When bits [24:20] are set to “5”, an interrupt signal is asserted when the input signal changes to a certain value Z.

  For example, when “6” is set in the bits [24:20], the interrupt signal is asserted when the input signal is 0. When “7” is set in bits [24:20], when the input signal is 1, the interrupt signal is asserted. When bits [24:20] are set to “8”, the interrupt signal is asserted when the input signal has a certain value X. When bits [24:20] are set to “9”, an interrupt signal is asserted when the input signal is a certain value Z.

  Information indicating whether or not to reset the input counters 23-1 to 23-n is set in the bit [19] indicated by the name "counter reset". For example, when “1” is set in the bit [19], the count values of the input counters 23-1 to 23-n are reset to 0.

  Information indicating whether or not to operate the input counters 23-1 to 23-n is set in the bit [18] indicated by the name "count start". For example, when “1” is set in the bit [18], counting by the input counters 23-1 to 23-n is performed. When the predetermined count value is reached, bit [18] is set to “0”, and counting by the input counters 23-1 to 23-n is stopped.

  Whether or not to perform count interrupt control for asserting an interrupt signal when the count value set in bits [64:32] is reached is indicated in bit [17] indicated by the name “count interrupt control” Is set. For example, when “1” is set in the bit [17], the interrupt signal is asserted when the count value is reached by the input counters 23-1 to 23-n.

FIG. 8 is a diagram illustrating a setting example of the output register.
The first count value is set in the 16-bit bits [64:48] indicated by the name “count value 0”.

A second count value is set in the 16-bit bits [47:32] indicated by the name “count value 1”.
The 9-bit bits [31:23] indicated by the name “reserved” are an unused area.

  Information indicating whether or not to reset the output counters 26b-1 to 26b-n is set in the bit [22] indicated by the name "counter 1 reset". For example, when “1” is set in the bit [22], the count values of the output counters 26b-1 to 26b-n are reset to 0. When the count value is reset, bit [22] is set to “0”.

  Information indicating whether or not to operate the output counters 26b-1 to 26b-n is set in the bit [21] indicated by the name "count 1 start". For example, when “1” is set in the bit [21], the output counters 26b-1 to 26b-n perform counting. For example, when the count value of bits [47:32] is reached, bit [21] is set to “0”, and counting by the output counters 26b-1 to 26b-n is stopped.

  The bit [20] indicated by the name “count 1 interrupt control” asserts an interrupt signal when the count value of bits [47:32] is reached by the output counters 26b-1 to 26b-n. Whether or not is set. For example, when “1” is set in the bit [20], the interrupt signal is asserted when the output counters 26b-1 to 26b-n reach the count value.

  Information indicating whether or not to reset the output counters 26a-1 to 26a-n is set in the bit [19] indicated by the name "counter 0 reset". For example, when “1” is set in the bit [19], the count values of the output counters 26a-1 to 26a-n are reset to 0. When the count value is reset, bit [19] is set to “0”.

  Information indicating whether or not to operate the output counters 26a-1 to 26a-n is set in the bit [18] indicated by the name "count 0 start". For example, when “1” is set in the bit [18], the output counters 26a-1 to 26a-n perform counting. For example, when the count value of bits [63:48] is reached, bit [18] is set to “0”, and counting by the output counters 26a-1 to 26a-n is stopped.

  In bit [17] indicated by the name “count 0 interrupt control”, whether an interrupt is asserted when the count value of bits [63:48] is reached in the output counters 26a-1 to 26a-n. Whether or not information is set. For example, when “1” is set in the bit [17], the interrupt signal is asserted when the output counters 26a-1 to 26a-n reach the count value.

  In the bit [16] indicated by the name “signal control”, information for controlling the output timing from the output buffers 27-1 to 27-n to the DUT 11 is set. For example, when “1” is set in the bit [16], the output buffers 27-1 to 27-27 until the output counters 26a-1 to 26a-n reach the count value of the bits [63:48]. Wait for output from -n. When “0” is set in the bit [16], an output signal to the DUT 11 is always output from the output buffers 27-1 to 27-n.

  In bits [15:12] indicated by the name “control value — 4 bit pattern”, a 4-bit pattern output to the DUT 11 when a control value described below is a certain value is set. .

  In bits [11: 8] indicated by the name “control value”, for example, when the above bit [16] is “1”, the output counters 26a-1 to 26a-n have bits [63: 48], a value to be output as a control value is set. For example, when “0” is set in bits [11: 8], “0” is output, and when “1” is set, “1” and “2” are set. In this case, the value X is output. When “3” is set, another value Z is output. For example, when “4” is set in bits [11: 8], a 4-bit pattern of the above bits [15:12] is output. An application example of the control value will be described later.

Next, an example of the program P stored in the storage unit 132 of the external model 13 will be described.
FIG. 9 is a diagram illustrating an example of a program.
The program P includes, for example, a functional layer 30 and a register control layer 31.

  The functional layer 30 has a program for realizing the function as the external model 13. Analysis of the input signal from the DUT 11 and creation of response information to the DUT 11 are performed by the program of the functional layer 30.

  The register control layer 31 realizes a function of rewriting the input registers 22-1 to 22-n and the output registers 25-1 to 25-n so that the signal input / output control unit 131 can recognize the interface signal. Have a program. Based on the contents of the register control layer 31, the pseudo processor 133 sets each bit of the input registers 22-1 to 22-n and output registers 25-1 to 25-n as shown in FIGS. Rewrite the value. Thereby, the general-purpose external model 13 corresponding to various interfaces is realized.

  The programs of the functional layer 30 and the register control layer 31 are stored in, for example, the database 40 in accordance with the interface type, function, abstraction level, etc. realized by the external model 13. The database 40 is constructed, for example, in a storage unit 132 in the external model 13, a memory (not shown) in the test apparatus 10, or a computer connected to the test apparatus 10 by wire or wirelessly.

  In the example of FIG. 9, the database 40 has the function programs A and B for the interface 1 and the function program for the interface 2 as programs of the function layer 30. The database 40 includes a register control program for the interface 1 and register control programs A and B for the interface 2 as programs for the register control layer 31.

  For example, the interface 1 is an interface for an SD card, and the interface 2 is an interface for an SDRAM. Although two function programs A and B are shown for the interface 1, the function program A is, for example, a basic function of an interface for an SD card, and the function program B is a program for executing an error generating function, for example. .

  Further, two register control programs A and B are shown for the interface 2, but for example, the register control program A has a high abstraction level and the register control program B has a low abstraction level.

  Under the control of the pseudo processor 133, function programs and register control programs used in the function layer 30 and the register control layer 31 are extracted from the database 40, and the functions and interfaces can be easily switched by rewriting the program P. Can do.

FIG. 10 is an example of an interrupt function included in the register control program.
FIG. 10 shows an example of an interrupt function “Interrupt_RI1 ()”. In FIG. 10, the interrupt register 20 is represented as “interput_reg”, and one of the input buffers 24-1 to 24-n is represented as “S_IN_0 buffer” or “SIN0”. One of the output buffers 27-1 to 27-n is represented as “S_OUT_0 buffer”, and one of the output registers 25-1 to 25-n is represented as “S_OUT_5 register”. Read () is a function that reads data and returns data, and write () is a function that writes data.

  This interrupt function “Interrupt_RI1 ()” reads a certain input buffer when the value of the interrupt register 20 is “0x00000001”, and performs a process of writing to a certain output buffer and output register in accordance with the contents. The function to perform.

Hereinafter, the operation during the test by the test apparatus 10 will be described in more detail.
First, in the external model 13, the pseudo processor 133 executes a startup routine described in the program P, for example, and initializes the signal input / output control unit 131. At the time of this initialization, the setting process of the signal input / output control unit 131 in step S2 of FIG. 2 described above is performed.

FIG. 11 is a flowchart illustrating a flow of an example of the initialization operation.
First, the pseudo processor 133 resets the value of each register of the signal input / output control unit 131 to 0 (step S10). Then, the pseudo processor 133 sets the input registers 22-1 to 22-n and the output registers 25-1 to 25-n according to the program P (step S11).

  The pseudo processor 133 initializes the output buffers 27-1 to 27-n (step S12), and sets the interrupt mask register 28 (step S13). In the setting of the interrupt mask register 28, which interrupt factor is to be enabled or disabled is set.

  Thereafter, the pseudo processor 133 sets the clock control register 21 and permits the generation of the DUT clock (step S14). As a result, the clock generator 12 outputs the DUT clock to the DUT 11, the operation of the DUT 11 starts (step S15), and the initialization operation ends.

Note that the order of steps S11 to S14 in FIG. 11 can be changed as appropriate.
FIG. 12 is a flowchart illustrating an example of processing of the external model in each clock cycle of the DUT.

  When the processing of one clock cycle of the DUT 11 is completed, the signal input / output control unit 131 refers to the input registers 22-1 to 22-n and the output registers 25-1 to 25-n (step S20). Then, the signal input / output control unit 131 refers to the interface signal and the like to determine whether or not an interrupt factor that is an operation factor of the external model 13 is generated (step S21).

  For example, in the input register 22-1 in which a setting value related to a certain interface signal is stored, an interrupt is asserted when the input signal changes to 0 as shown in the above example in bits [24:20] as shown in FIG. Assume that “2” is set. In this case, the signal input / output control unit 131 determines that an interrupt factor has occurred when the interface signal changes to 0 by processing of one clock cycle of the DUT 11.

When the signal input / output control unit 131 determines that an interrupt factor has not occurred, the DUT 11 performs processing of the next clock cycle.
When determining that an interrupt factor has occurred, the signal input / output control unit 131 asserts an interrupt signal (step S22). At this time, the signal input / output control unit 131 sets information indicating which interface signal caused an interrupt in the interrupt register 20. For example, in the interrupt register 20 as shown in FIG. 6A, the bit value corresponding to the interface signal that caused the interrupt is set to “1” in bits [n−1: 0].

Then, for example, the signal input / output control unit 131 sets “0” in the clock control register 21 and causes the clock generation unit 12 to stop generating the DUT clock (step S23).
The pseudo processor 133 refers to the interrupt register 20 and identifies the type of interrupt (step S24). Then, the pseudo processor 133 performs program processing according to the program of the function layer 30 of the program P (step S25). When the program process ends, the pseudo processor 133 sets “1” in the clock control register 21 and causes the clock generation unit 12 to resume the generation of the DUT clock (step S26). As a result, the DUT 11 performs processing for the next clock cycle.

FIG. 13 is a flowchart illustrating an example of a program process.
The pseudo processor 133 determines whether or not the process uses the input information based on the contents of the program P during the program process (step S30). In the case of processing using input information, the pseudo processor 133 reads input information from the DUT 11 from the input buffers 24-1 to 24-n (step S31).

  When the input information is not used or after the process of step S31, the pseudo processor 133 determines whether to set the input registers 22-1 to 22-n (step S32). For example, if the program P includes an instruction for invalidating an interrupt due to an input signal or invalidating for a certain period, the pseudo processor 133 sets that in the input registers 22-1 to 22-n (step S33).

  For example, the pseudo processor 133 sets the bit [24:20] area to “0” in the setting example of the input registers 22-1 to 22-n shown in FIG. Disable. Thereby, it is suppressed that the program processing under execution is interrupted by interruption.

  When the input registers 22-1 to 22-n are not set, or after the process of step S33, the pseudo processor 133 determines whether to set the output registers 25-1 to 25-n (step S34). ). For example, if the program P includes an instruction to control the output timing to the DUT 11, the pseudo processor 133 sets that in the output registers 25-1 to 25-n (step S35).

  For example, in the setting example of the output registers 25-1 to 25-n illustrated in FIG. 8, the pseudo processor 133 sets “1” in the bit [16] area until the count value is reached. The output from the buffers 27-1 to 27-n can be waited.

  When the output registers 25-1 to 25-n are not set or after the process of step S35, the pseudo processor 133 determines whether or not to write to the output buffers 27-1 to 27-n (step S35). S36). For example, when an instruction to output the analysis result in the program processing or the response information to the DUT 11 to the DUT 11 side is executed, the information is written to the output buffers 27-1 to 27-n (step S37).

  When writing to the output buffers 27-1 to 27-n is not performed, or after the process of step S37, the pseudo processor 133 determines whether or not the program process is finished (step S38).

  When the program processing is completed, the pseudo processor 133 performs the process of step S26 described above and restarts the generation of the DUT clock. If the program processing has not ended, the processing from step S30 is repeated.

Note that the order of steps S30 to S37 in FIG. 13 can be changed as appropriate.
As described above, the control as shown in FIGS. 11 to 13 allows the external model 13 to simulate the function as a device accessed by the DUT 11.

Next, an example in which an external model is applied as an interface for an SD card will be described.
FIG. 14 is a diagram illustrating an example of connection with a DUT when an external model is applied to an interface for an SD card.

  In FIG. 14, the same elements as those shown in FIG. The signal input / output control unit 131 includes input buffers 24-1 to 24-5, output buffers 27-1 to 27-7, input registers 22-1 to 22-5, and output registers 25-1 to 25-7. ing. In the signal input / output control unit 131, the other elements shown in FIG. 5 are not shown.

  When the external model simulates an interface for an SD card, the signal lines are the same for input and output. Therefore, in the example of FIG. 14, when there is an input from the DUT 11, a plurality of tristate buffers (hereinafter simply referred to as buffers) 51, 52, 53, 54, 55 for controlling the output to the DUT 11 not to be performed. Is provided. The buffer unit 50 is described as an external model in, for example, a hardware description language.

  In the buffer unit 50, the buffer 51 is provided between the signal line CMD to which a command from the DUT 11 and the like are transmitted and the output buffer 27-1. Buffers 52 to 55 are provided between signal lines DAT [0], DAT [1], DAT [2], and DAT [3] through which data and the like are transmitted, and output buffers 27-2 to 27-5. ing.

  Further, the control value from the output buffer 27-7 is input to the buffer 51, the control value from the output buffer 27-6 is input to the buffers 52 to 55, and the information from the signal input / output control unit 131 is received. Whether or not to output is controlled.

FIG. 15 is a diagram illustrating an operation example of the test apparatus when the external model is an interface for an SD card.
In FIG. 15, blocks on a straight line connected to the DUT 11, the signal input / output control unit 131, and the pseudo processor 133 indicate processing in each unit.

  First, the pseudo processor 133 performs initial setting as shown in FIG. 11 for the signal input / output control unit 131 (timing T10). When the initial setting is completed, the signal input / output control unit 131 starts the DUT clock supplied to the DUT 11 (timing T11). When issuance of an instruction from the DUT 11 is started (timing T12), the signal input / output control unit 131 determines that an interrupt factor has been detected and asserts an interrupt signal (timing T13). Further, the signal input / output control unit 131 stops the DUT clock (timing T14). When the pseudo processor 133 receives the interrupt instruction (that is, detects the assertion of the interrupt signal), the pseudo processor 133 checks the interrupt register 20 and specifies the type of interrupt (timing T15). Thereafter, the pseudo processor 133 sets the input register 22-1 to assert an interrupt signal after 48 counts by the input counter 23-1 shown in FIG. 5, for example (timing T16). When the program processing ends, the pseudo processor 133 sets the clock control register 21 and permits the start of the DUT clock (timing T17). Thereby, the signal input / output control unit 131 restarts the DUT clock (timing T18).

  The DUT 11 issues, for example, a 48-bit instruction bit by bit in synchronization with the DUT clock (timing T19), and inputs the instruction to the input buffer 24-1 of the signal input / output control unit 131. When the issuance of the 48th bit instruction is completed (timing T20) and the 48 count by the input counter 23-1 is completed, the signal input / output control unit 131 asserts an interrupt signal (timing T21). Further, the signal input / output control unit 131 stops the DUT clock (timing T22). When the pseudo processor 133 receives the interrupt instruction, it checks the interrupt register 20 and specifies the type of interrupt (timing T23).

  Then, the pseudo processor 133 reads the instruction held in the input buffer 24-1 (timing T24). The pseudo processor 133 analyzes the read instruction by program processing, creates response information, and sets it in the output buffer 27-1 (timing T25). Further, the pseudo processor 133 performs setting for the output register 25-1 so that the data (response information) in the output buffer 27-1 is output after 4 clock cycles (4 counts), for example (timing T26). ).

  Further, the pseudo processor 133 sets a control value for controlling the buffer 51 to output the signal from the signal input / output control unit 131 to the DUT 11 according to the setting of the output register 25-1, and the output buffer 27-7. (Timing T27). Further, the pseudo processor 133 sets the output register 25-7 to supply the control value of the output buffer 27-7 to the buffer 51 after 2 clock cycles (2 counts) (timing T28).

  Thereafter, the pseudo processor 133 sets the clock control register 21 and permits the start of the DUT clock (timing T29). Thereby, the signal input / output control unit 131 restarts the DUT clock (timing T30). Then, the signal input / output control unit 131 outputs the response information held in the output buffer 27-1 to the DUT 11 via the buffer 51 (timing T31).

  As described above, the external model having the signal input / output control unit 131 as shown in FIG. 14 can function properly as an interface of the SD card, and the output timing can be adjusted by changing the program P. This can be done easily by adjusting the setting value of each register.

  In the above description, the signal input / output control unit 131 is set by the program P to realize the function of a certain interface. However, the present invention is not limited to this. You may make it implement | achieve the function of an interface.

FIG. 16 is a diagram illustrating an example of an external model corresponding to a plurality of interface functions.
Elements similar to those in FIG. 1 are denoted by the same reference numerals.
In the test apparatus 10a of FIG. 16, the storage unit 132a of the external model 13a has two programs P1 and P2. In addition, the signal input / output control unit 131a includes an IF1 setting unit 61 and an IF2 setting unit 62.

  Each of the IF1 setting unit 61 and the IF2 setting unit 62 includes each element of the signal input / output control unit 131 as shown in FIG. The program P1 is a program for designating the function of the interface 1 (for example, an interface for an SD card) to the IF1 setting unit 61. The program P2 is a program for designating the function of the interface 2 (for example, an interface for SDRAM) to the setting unit 62 for IF2.

  The pseudo processor 133 sets the input registers 22-1 to 22-n and the output registers 25-1 to 25-n of the IF1 setting unit 61 and the IF2 setting unit 62, respectively, based on the programs P1 and P2. As a result, a plurality of interfaces can be supported at the same time, and a plurality of interfaces of the DUT 11 can be connected.

1 and FIG. 16, the number of the external models 13 and 13a is one, but a plurality of external models 13 and 13a may be provided.
Alternatively, a plurality of pseudo processors and storage units may be provided in the external model, and a plurality of programs may be operated simultaneously so that a plurality of interfaces can be supported at the same time.

Note that the processing of the test apparatuses 10 and 10a described above can be realized by a computer.
FIG. 17 is a diagram illustrating an example of computer hardware.

The entire computer 100 is controlled by a CPU 101. The CPU 101 is connected to the RAM 102 and a plurality of peripheral devices via the bus 108.
The RAM 102 is used as a main storage device of the computer 100. The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data used for processing by the CPU 101.

  Peripheral devices connected to the bus 108 include a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, an optical drive device 106, and a communication interface 107.

  The HDD 103 magnetically writes and reads data to and from the built-in disk. The HDD 103 is used as a secondary storage device of the computer 100. The HDD 103 stores an OS program, application programs, and various data. Note that a semiconductor storage device such as a flash memory can also be used as the secondary storage device.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. Examples of the monitor 104a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits signals sent from the keyboard 105a and the mouse 105b to the CPU 101. Note that the mouse 105b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 106 reads data recorded on the optical disc 106a using laser light or the like. The optical disk 106a is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 106a includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The communication interface 107 is connected to the network 107a. The communication interface 107 transmits / receives data to / from other computers or communication devices via the network 107a.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
Thus, the processing functions of the test apparatuses 10 and 10a can be realized by a computer. In that case, a program describing the processing contents of the functions that the test apparatuses 10 and 10a should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic storage device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Optical discs include DVD, DVD-RAM, CD-ROM / RW, and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, portable recording media such as a DVD and a CD-ROM in which the program is recorded are sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  In addition, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

  As described above, one aspect of the test apparatus, the verification model development method, and the program of the present invention has been described based on the embodiment. However, these are merely examples, and the present invention is not limited to the above description.

DESCRIPTION OF SYMBOLS 10 Test apparatus 11 Model under test 12 Clock generation part 13 Pseudo model (external model)
131 Signal Input / Output Control Unit 132 Storage Unit 133 Pseudo Processor 134 Bus P Program

Claims (9)

It has a pseudo model that simulates the operation of the device accessed by the model under test,
The pseudo model is
A signal input / output control unit for inputting / outputting signals to / from the model to be tested;
A storage unit storing a program for specifying a function of an interface executed by the signal input / output control unit;
A pseudo processor for setting the signal input / output control unit according to the program;
A test apparatus comprising:   The signal input / output control unit stops the operation of the model to be tested when an operation factor of the pseudo model is detected based on a value set by the pseudo processor. The test apparatus described.   3. The test apparatus according to claim 1, wherein the storage unit stores a program selected from a plurality of programs corresponding to the type or function of the interface stored in a database. .   The signal input / output control unit controls a clock signal supplied to the model under test so that the pseudo model and the model under test are operated in parallel based on a value set by the pseudo processor. The test apparatus according to any one of claims 1 to 3, wherein:   The said pseudo processor sets the output timing of the signal output to the said test object model to the said signal input / output control part according to the said program, The any one of Claim 1 thru | or 4 characterized by the above-mentioned. The test apparatus described in 1. The storage unit has a plurality of programs that specify different interface functions,
The signal input / output control unit has a plurality of setting units for setting the function of each interface,
The test apparatus according to claim 1, wherein the pseudo processor sets a function of each interface for the plurality of setting units according to the plurality of programs. A computer has a signal input / output control unit for inputting / outputting signals to / from the model under test, a storage unit storing a program for specifying an interface function executed by the signal input / output control unit, and a pseudo processor Generating a pseudo model that simulates the operation of the device accessed by the model under test;
The verification model development method, wherein the pseudo processor sets the signal input / output control unit according to the program.   The verification model development method according to claim 7, wherein the pseudo model is generated based on a setting file in which a circuit amount in the signal input / output control unit is designated according to an interface to be used. Computer
A signal input / output controller that inputs and outputs signals to and from the model under test;
A storage unit storing a program for designating an interface function executed by the signal input / output control unit;
A pseudo processor for setting the signal input / output control unit according to the program;
And having a function as a pseudo model for simulating the operation of the device accessed by the model under test.

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