CN102495254A - Oscilloscope high speed signal sampling system - Google Patents

Abstract

The invention discloses an oscilloscope high speed signal sampling system, which comprises a reference signal source, an analog front end, digital-analog converters, a time-domain equalizer, a filter and a signal chain compensation controller. The output end of the reference signal source is connected with the input end of the analog front end. Calibrating signals from the reference signal source are input to the four pieces of digital-analog converters to be converted into digital signals after passing through the analog front end and then input to the filter through time-domain equalizer. The digital signals after signal chain compensation are sent to the signal chain compensation controller, the output end of the signal chain compensation controller is connected with the input end of the time-domain equalizer, the signal chain compensation controller inputs calculated compensation signals to the time-domain equalizer and the filter, and the signals are output to a storage and imaging unit through the filter. The oscilloscope high speed signal sampling system overcomes the defect of inconsistency of direct current and alternating current, resolves the problems of phase noise and phase error, and is capable of effectively achieving low-cost signal sampling of 20GSa/s.

Description

A kind of oscillograph high speed signal sampling system

Technical field

The present invention relates to a kind of oscillograph high speed signal sampling system, specifically, relate to the oscillograph high speed signal sampling system that a kind of sampling rate reaches 20GSa/s, belong to the signal testing field of measuring technique.

Background technology

Sampling rate is one of index of digital oscilloscope most critical always.Realize that high real-time sampling rate also is the maximum design difficulty of digital oscilloscope.The key that realizes high sampling rate is ADC (ADC is the english abbreviation of analog-digital converter Analog to Digital Converter).(CMOS is the english abbreviation of CMOS Complementary Metal Oxide Semiconductor to traditional ADC based on CMOS mostly; Refer to PMOS pipe and the common complementary type MOS integrated circuit fabrication process that constitutes of NMOS pipe) or bipolar technology, make its sampling rate be difficult to break through 3GSa/s.Abroad; Along with radio frequency high-speed semiconductor technology; Like GaAs, pHEMT, SiGe etc., the progressively use in ADC makes the sampling rate of monolithic ADC reach 50GSa/s even higher; Emerging SiGe-BiCMOS technology has then combined high integration, the low cost of the high-speed and CMOS technology of SiGe technology, is adopted by the modulus hybrid circuit of flank speed gradually.

At home, though bipolar technology and CMOS technology are very ripe, can't satisfy the demand of high-speed ADC.And only can be used in the RF IC for radio frequency semiconductor technology such as pHEMT, SiGe etc., though frequency very high be the demand that designed capacity or working ability all can't satisfy extensive device such as ADC.And be limited to technology barriers and policy barrier, external ADC product again can't import, therefore, for sampling rate up to 20GSa/s, directly use external monolithic ADC or voluntarily design produce high-speed ADC and all be difficult to realize.

Summary of the invention

The problems referred to above and deficiency to the prior art existence; The purpose of this invention is to provide a kind of method that adopts traditional alternating sampling; Realize single pass High Speed Sampling System with multi-disc ADC; On alternating sampling theoretical foundation, overcome the direct current inconsistency, exchange problem of inconsistency, solve phase noise and phase error problems.

For realizing above-mentioned purpose, the technical scheme that the present invention adopts is following:

A kind of oscillograph high speed signal sampling system; Comprise derived reference signal, AFE(analog front end), digital-to-analogue converter, time domain equalizer, wave filter and signal chains compensating controller; The output terminal of derived reference signal links to each other with the input end of AFE(analog front end), and AFE(analog front end) receives the calibrating signal from derived reference signal, and calibrating signal is imported behind AFE(analog front end) in four digital-to-analogue converters; Conversion of signals is become digital signal with the digital-to-analogue converter after the time domain equalizer input filter; Wave filter links to each other with the signal chains compensating controller, and the digital signal after the signal chains compensation is sent into the signal chains compensating controller, and the output terminal of signal chains compensating controller links to each other with the input end of time domain equalizer; Compensating signal input time domain equalizer and wave filter after the signal chains compensating controller will calculate, signal exports to through wave filter and stores and image-generating unit.

As a kind of preferred version, said derived reference signal, AFE(analog front end), digital-to-analogue converter, time domain equalizer, wave filter and signal chains compensating controller constitute a closed loop.

As further preferred version, said time domain equalizer comprises nonlinear compensation and linear compensation.

As further preferred version, said time domain equalizer is selected field programmable gate array for use.

As further preferred version, said wave filter is selected the general central processing unit of x86 framework for use.

Compared with prior art; The present invention has following beneficial effect: the present invention adopts the method for traditional alternating sampling, realizes single pass High Speed Sampling System with multi-disc ADC, on alternating sampling theoretical foundation; Overcome the direct current inconsistency, exchanged problem of inconsistency; Solved phase noise and phase error problems, and utilization signal chains compensation technique, low-cost 20GSa/s signal sampling can effectively be accomplished.

Description of drawings

Fig. 1 is a K road alternate scheme sample circuit block diagram;

Fig. 2 is an alternating sampling inconsistency simulation result at 2% zero point;

Fig. 3 is an alternating sampling inconsistency simulation result at 5% zero point;

Fig. 4 does not have the phase jitter simulation result for alternating sampling;

Fig. 5 is an alternating sampling 5ps phase jitter simulation result;

Fig. 6 is alternating sampling 5 degree phase error simulation results;

Fig. 7 is alternating sampling 10 degree phase error simulation results;

Fig. 8 is the signal chains compensation technique realization block diagram based on digital signal processing and digital pre-distortion.

Specific embodiments

Below in conjunction with specific embodiment and accompanying drawing the present invention is done further detailed explanation.

Disclosed all characteristics in this instructions, or the step in disclosed all methods or the process are except the speciality of mutual repulsion and/or the step; All can be with any scheme combination; Only if special narration all can be replaced by other equivalences or the alternative features with similar purpose, promptly; Only if special narration, an embodiment in a series of equivalences of each characteristic or the similar characteristics.

A kind of oscillograph high speed signal sampling system provided by the invention; Comprise derived reference signal, AFE(analog front end), digital-to-analogue converter, time domain equalizer, wave filter and signal chains compensating controller; The output terminal of derived reference signal links to each other with the input end of AFE(analog front end); AFE(analog front end) receives the calibrating signal from derived reference signal; Calibrating signal is imported behind AFE(analog front end) in four digital-to-analogue converters, and four digital-to-analogue converters are respectively digital-to-analogue converter 1, digital-to-analogue converter 2, digital-to-analogue converter 3 and digital-to-analogue converter 4; Conversion of signals is become digital signal with the digital-to-analogue converter after the time domain equalizer input filter; Wave filter links to each other with the signal chains compensating controller; Digital signal after the signal chains compensation is sent into the signal chains compensating controller; The output terminal of signal chains compensating controller links to each other with the input end of time domain equalizer, compensating signal input time domain equalizer and wave filter after the signal chains compensating controller will calculate, and signal exports to through wave filter and stores and image-generating unit.Said derived reference signal, AFE(analog front end), digital-to-analogue converter, time domain equalizer, wave filter and signal chains compensating controller constitute a closed loop, and wherein, said time domain equalizer comprises nonlinear compensation and linear compensation; Time domain equalizer is selected field programmable gate array for use; Wave filter is selected the general central processing unit of x86 framework for use.

Principle of work of the present invention is following:

Alternating sampling is theoretical

As shown in Figure 1, Fig. 1 has provided K road alternate scheme sample circuit block diagram.This circuit is made up of power divider, K sheet ADC, sampling clock divider and digital signal processing unit.

Input signal x (t) is assigned as the k road through power divider and sends into independently ADC respectively and carry out the A/D conversion.This K ADC receive sampling clock [m1 (t), m2 (t) ..., mk (t)] driving output transformation result [y1 (t), y2 (t) ..., yk (t)].K road transformation result is merged into net result y (n) output after handling through digital signal processing unit.During alternating sampling, the phase place that staggers between the sampling clock of each ADC, that is:

$m_1\left(t\right)=\underset{n=-\∞}{\overset{\∞}{\mathrm{\Σ}}}\mathrm{\δ}(t-\mathrm{nT})$

$m_2\left(t\right)=\underset{n=-\∞}{\overset{\∞}{\mathrm{\Σ}}}\mathrm{\δ}(t-\mathrm{nT}-\mathrm{\ΔT})$

$m_3\left(t\right)=\underset{n=-\∞}{\overset{\∞}{\mathrm{\Σ}}}\mathrm{\δ}(t-\mathrm{nT}-2\mathrm{\ΔT})$

Λ

$m_k\left(t\right)=\underset{n=-\∞}{\overset{\∞}{\mathrm{\Σ}}}\mathrm{\δ}(t-\mathrm{nT}-(k-1)\mathrm{\ΔT})$

ΔT＝T/k

In the formula, T is the sampling period, and Δ T is the unit interval increment of alternating sampling clock.The digital signal processing part is closed the road successively to the K road alternate data of ADC output, obtains the A/D transform data of one road K times speed, and equivalence has improved K doubly for sampling rate.

In high speed alternating sampling system; System performance is except receiving the performance index of single ADC; Outside the influence like " unalterable quotas " such as integration/differential nonlinearity, harmonic distortion, analog bandwidth, aperture shakes, mainly receive the influence of difference of gain, the direct current offset (being linear error) of K road A/D conversion error aperture time and K ADC.If it is bad that above-mentioned these parameters cooperate, cause nonuniform sampling to occur, can cause sampling quality to descend greatly.If the direct current offset error of K road ADC is respectively ai, i=0,1 ..., K-1, because gain and the direct current offset error of each ADC are definite value basically, therefore, error sequence can be regarded the sequence that the cycle is K as, its frequency spectrum is:

$\mathrm{\ΔX}\left(\mathrm{\ω}\right)=\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}{a}_n{e}^{-\mathrm{j\ωn\ΔT}}=\underset{m=0}{\overset{K-1}{\mathrm{\Σ}}}\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}{a}_{m+\mathrm{nk}}{e}^{-\mathrm{j\ω}(m+\mathrm{nK})\mathrm{\ΔT}}$

$=\underset{m=0}{\overset{K-1}{\mathrm{\Σ}}}\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}{a}_m{e}^{-\mathrm{j\ωm\ΔT}-\mathrm{j\ωnK\ΔT}}=\underset{m=0}{\overset{K-1}{\mathrm{\Σ}}}{a}_m{e}^{-\mathrm{j\ωm\ΔT}}\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}{e}^{-\mathrm{j\ωnK\ΔT}}$

In the formula;

is T=K Δ T, SI to be the signal spectrum that the alternating sampling of Δ T obtains for direct current signal through the cycle, and following formula can further be written as:

$\mathrm{\Δ\; X}\left(\mathrm{\ω}\right)=\underset{m=0}{\overset{K-1}{\mathrm{\Σ}}}{a}_m{e}^{-\mathrm{J\ω\; M\Δ\; T}}\·\frac{2\mathrm{\π}}{\mathrm{K\Δ\; T}}\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}\mathrm{\δ}(\mathrm{\ω}-n\frac{2\mathrm{\π}}{\mathrm{K\Δ\; T}})=\frac{1}{T}\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}\left[\left(\underset{m=0}{\overset{K-1}{\mathrm{\Σ}}}{a}_m{e}^{-j(2\mathrm{\π}/K)\mathrm{Nm}}\right)\mathrm{\δ}(\mathrm{\ω}-n\frac{2\mathrm{\π}}{T})\right]$ Suppose by sampled signal be a band limit (its Fourier transform is X (Ω) for 1/2T, simulating signal 1/2T), and then the frequency spectrum of K road alternating sampling output digital signal is:

$X\left(\mathrm{\ω}\right)=\frac{1}{T}\left(\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}X(\mathrm{\ω}-\mathrm{n\Ω})\right)+\mathrm{\ΔX}\left(\mathrm{\ω}\right)$

Gain and offset error that K road alternating sampling is total are:

${\mathrm{\&Delta;X}}_T\left(\mathrm{\&omega;}\right)=\sqrt{{{\mathrm{\&Delta;<figure-callout\; id="0"\; label="X"\; filenames="HDA0000118624970000012.png,HDA0000118624970000021.png"\; state="\{\{state\}\}">X</figure-callout>}}_0}^2\left(\mathrm{\&omega;}\right)+{{\mathrm{\&Delta;X}}_1}^2\left(\mathrm{\&omega;}\right)+\mathrm{\&Lambda;}+{{\mathrm{\&Delta;X}}_{L-1}}^2\left(\mathrm{\&omega;}\right)}$

Alternating sampling total error aperture time in K road is:

${\mathrm{\&Delta;T}}_T=\sqrt{{({\mathrm{\&Delta;T}}_0-\mathrm{\&Delta;T})}^2+{({\mathrm{\&Delta;T}}_1-\mathrm{\&Delta;T})}^2+\mathrm{\&Lambda;}+{({\mathrm{\&Delta;T}}_{K-1}-\mathrm{\&Delta;T})}^2}$

Therefore, the relative error of the total amplitude-phase place of K road alternating sampling is:

$\mathrm{\&Delta;E}=20\lg \left(\sqrt{{\left(\frac{{\mathrm{\&Delta;X}}_T\left(\mathrm{\&omega;}\right)}{X\left(\mathrm{\&omega;}\right)}\right)}^2+{\left(\frac{{{\mathrm{\&Delta;\&theta;}}_T}^{,}}{\mathrm{\&Delta;\&theta;}}\right)}^2}\right)=20\lg \left(\sqrt{{\left(\frac{{\mathrm{\&Delta;X}}_T\left(\mathrm{\&omega;}\right)}{X\left(\mathrm{\&omega;}\right)}\right)}^2+{\left(\frac{{\mathrm{\&Delta;T}}_T}{\mathrm{\&Delta;T}}\right)}^2}\right)\left(\mathrm{dB}\right)$

In the formula, Δ θ ', Δ θ are respectively total phase error of alternating sampling and differing of twice neighbouring sample.

Theoretical according to alternating sampling, multi-disc high speed alternating sampling can bring a lot of reluctant problems, and wherein sixty-four dollar question is the consistency problem of multi-disc ADC.And consistency problem is broadly divided into two types: the direct current inconsistency with exchange inconsistency.In addition, phase jitter, phase error also will have a strong impact on the performance of sampling system.

To carry out emulation to find out the inconsistency scope that to allow to consistency problem below.

A, direct current inconsistency

When the incoming frequency of ADC was hanged down, it exchanged inconsistency and phase problem can be ignored, but in any one frequency range of ADC, the direct current inconsistency all can have a strong impact on the performance of sampling system.The direct current inconsistency can be divided into inconsistent, inconsistent and non-linear inconsistent three aspects of gain at zero point.Wherein inconsistent meeting at zero point causes the spuious energy at sampling rate respective frequencies place; The inconsistent meeting that gains causes the modulation of SF to measured signal; And non-linear inconsistent meeting causes the rapid decline of the linearity, causes the modulation to measured signal of a large amount of harmonic interference and SF.All direct currents are inconsistent all can to lead to disastrous consequence in time domain and frequency domain.It below is 8 sampling systems of 20GSa/s that the ADC of 4 5GSa/s forms are carried out alternating sampling to the 249MHz signal simulation result.

It is inconsistent that accompanying drawing 2 has added zero point of about 2%.

Can see tangible spurious frequency by figure.

It is inconsistent that accompanying drawing 3 has added about 5% gain.

Visible by figure, no matter be frequency domain or time domain, the direct current inconsistency all will cause great influence, must be eliminated.

B, interchange inconsistency

Exchange inconsistency and be embodied in amplitude and two aspects of phase place.When frequency is higher, influence the performance of sampling system owing to the inconsistent meeting of the different amplitude/phase that cause of amplitude versus frequency characte of ADC with phase-frequency characteristic.Influence to amplitude is equal to the direct current inconsistency, and the influence of phase place is equal to phase jitter.This one section argumentation in detail below.

C, phase noise and phase error

If make sampling system keep best performance, the clock of being distributed to each ADC by clock distributor must guarantee strict phase relation, does not have phase noise, and ADC must begin the sampling maintenance in the time of strictness.In fact, more than statement can't realize that phase noise can bring the uncertainty in sampling time, and phase error can cause definite inhomogeneous sampling.

In the alternating sampling system, phase noise and phase error can embody aspect two: outside the ADC and in the ADC.Outside ADC, phase noise and phase error come from clock source, clock distributor and transmission line, and in ADC, and phase noise and sampling holder, clock distributor and multi-disc ADC in phase error comes from ADC exchange inconsistency.

8 sampling systems of 20GSa/s of forming with the ADC of 4 5GSa/s are example, and input signal is that 2.49GHz is sinusoidal wave.Under the situation that does not have phase noise and phase jitter, time domain and frequency-region signal simulation result are shown in accompanying drawing 4.

The figure left side is time domain waveform (through Sin (x)/x function interpolation), and the right is a frequency spectrum.It is thus clear that frequency spectrum does not have spurious signal.

If sampling system has the random phase shake of 5ps, simulation result is shown in accompanying drawing 5.

Thus it is clear that,, can find out that from frequency domain signal to noise ratio (S/N ratio) has reduced pact-15dB though time domain waveform is difficult to find out variation.

If sampling system has ± (simulation result that promptly ± 2.78ps), obtains is shown in accompanying drawing 6 for the phase error of 5 degree.

The form of significantly being modulated by sampled signal has appearred in visible signal, but the time domain waveform variation is still not obvious.When phase error reached ± (promptly ± 5.56ps) time, tangible distortion has appearred in waveform, shown in accompanying drawing 7 for the phase error of 10 degree.

According to above simulation result; Check to be that main oscillograph is used for time domain waveform; Phase noise and phase error even all can showing the time domain waveform of alternating sampling system, 5% amplitude inconsistency cause obvious influence, though and can seriously influence the signal to noise ratio (S/N ratio) and the SFDR of sampling system.But 5ps or following phase noise and phase error can not cause fatal influence to the time domain shape of waveform for oscillograph.

The signal chains compensation

For reducing the inconsistency of alternating sampling system as far as possible, select good ADC of consistance and careful design clock distributor, make it have as far as possible little phase error and phase noise, be the method that design sampling system institute must employing.But because the discreteness of device is bigger, above method effect is limited.Descend for further reducing the performance that inconsistency brings, use other a kind of method to solve these problems here, promptly based on the signal chains compensation technique of digital signal processing and digital pre-distortion.The realization principle of this technology is shown in accompanying drawing 8.

Derived reference signal, AFE(analog front end), ADC, time domain equalizer, wave filter and signal chains compensating controller have constituted a closed loop.Derived reference signal can produce like multiple calibrating signals such as direct current, frequency sweep sine waves.Calibrating signal is sent into 4 ADC respectively through behind the AFE(analog front end); Send into time domain equalizer and wave filter after converting 4 way word signals into; Reference signal after the signal chains compensation is sent into the signal chains compensating controller; Calculate by the latter, draw further compensating parameter and send into time domain equalizer and wave filter, up to reaching optimum signal quality.Wherein time domain equalizer has been realized the time domain compensation of signal, comprises nonlinear compensation and linear compensation, and wave filter has been realized frequency domain equalization and phase place adjustment.System after the signal chains compensation can be with the determinacy error of the whole signal chains that comprises AFE(analog front end), ADC; Comprise that amplitude is inconsistent, non-linear, phase error etc.; Eliminate to minimum; Thereby realize the function of digital pre-distortion compensation signal chain, amplitude and phase place unevenness that simultaneously can the compensating analog front end further improve and import bandwidth.

The critical component of realizing the signal chains compensation is balanced device, wave filter and compensating controller.The former need keep the full rate computing when sampling, therefore use FPGA to realize; And the latter need move the required neural network algorithm of digital pre-distortion, and algorithm is complicated, therefore uses the universal cpu of x86 framework to realize.

Be necessary at last to be pointed out that at this that above-mentioned explanation is not to be limitation of the present invention, the present invention also is not limited to above-mentioned giving an example; Those skilled in the art; In essential scope of the present invention, the variation of having done, remodeling, interpolation or replacement all will belong to protection scope of the present invention.

Claims (5)

1. oscillograph high speed signal sampling system; Comprise derived reference signal, AFE(analog front end) and digital-to-analogue converter; It is characterized in that: also comprise time domain equalizer, wave filter and signal chains compensating controller; The output terminal of derived reference signal links to each other with the input end of AFE(analog front end), and AFE(analog front end) receives the calibrating signal from derived reference signal, and calibrating signal is imported behind AFE(analog front end) in four digital-to-analogue converters; Conversion of signals is become digital signal with the digital-to-analogue converter after the time domain equalizer input filter; Wave filter links to each other with the signal chains compensating controller, and the digital signal after the signal chains compensation is sent into the signal chains compensating controller, and the output terminal of signal chains compensating controller links to each other with the input end of time domain equalizer; Compensating signal input time domain equalizer and wave filter after the signal chains compensating controller will calculate, signal exports to through wave filter and stores and image-generating unit.

2. oscillograph high speed signal sampling system as claimed in claim 1 is characterized in that: said derived reference signal, AFE(analog front end), digital-to-analogue converter, time domain equalizer, wave filter and signal chains compensating controller constitute a closed loop.

3. oscillograph high speed signal sampling system as claimed in claim 2, it is characterized in that: said time domain equalizer comprises nonlinear compensation and linear compensation.

4. oscillograph high speed signal sampling system as claimed in claim 2, it is characterized in that: said time domain equalizer is selected field programmable gate array for use.

5. oscillograph high speed signal sampling system as claimed in claim 2 is characterized in that: said wave filter is selected the general central processing unit of x86 framework for use.

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