CN102456733B - Transistor and preparation method thereof - Google Patents
Transistor and preparation method thereof Download PDFInfo
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- CN102456733B CN102456733B CN201010524964.8A CN201010524964A CN102456733B CN 102456733 B CN102456733 B CN 102456733B CN 201010524964 A CN201010524964 A CN 201010524964A CN 102456733 B CN102456733 B CN 102456733B
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Abstract
A kind of transistor, it comprises nano wire, substrate, source electrode (Source), drain electrode (Drain), insulating barrier and grid (Gate), this source electrode and drain electrode relative being attached on this substrate in interval, this nano wire is overlapped between this source electrode and drain electrode, this insulating barrier is covered in the region between this source electrode, drain electrode and this source electrode and drain electrode, this grid is stacked on this insulating barrier, the opposite end of this source electrode and drain electrode is tip-shape design, and this nano wire is connected between this source electrode and the tip of drain electrode. The invention still further relates to this transistorized preparation method.
Description
Technical field
The present invention relates to a kind of transistor and preparation method thereof.
Background technology
Show that at present in science and technology, soft electronic is one of trend of future development, but conventional thin film transistorTo make deflection degree limited, and general poly semiconductor due to growth temperature is higher only can be on glass substratePreparation, therefore be used as electronics, electric hole transmission channel if can import monocrystal material, will extremely have competitionPotentiality.
Nano wire has high surface area to volume ratio (surfacetovolumeratio), this dimension knotStructure is compared and is all had spy with two-dimentional conventional films in surface characteristics, engineering properties, photoelectricity and quantum effectOther performance, therefore differently along with material also derive all kinds of related application, such as: gas sensor,Field-effect transistor, light-emitting component. But the bottleneck that utilizes nano wire to make element is how to overcome itDimensional problem in addition contraposition, control, if can be regularly arranged in a large number, will have an opportunity to import smoothly volume productionProcessing procedure.
Summary of the invention
In view of this, providing a kind of transistor that can address the above problem and preparation method thereof real is mustWant.
A kind of transistor, it comprise nano wire, substrate, source electrode, drain electrode, insulating barrier with grid, shouldSource electrode and drain electrode relative being attached on this substrate in interval, this nano wire is overlapped between this source electrode and drain electrode,This insulating barrier is covered in the region between this source electrode, drain electrode and this source electrode and drain electrode, and this grid is stacked atOn this insulating barrier, this source electrode comprises one first electrode, and this drain electrode comprises one second electrode, this first electrodeBe tip-shape design with the opposite end of this second electrode, this nano wire be connected in this this first electrode with shouldBetween the tip of the second electrode and with this substrate contacts.
A kind of preparation method of transistor, it comprises the steps: to provide a substrate; On this substrate, pressDefine the first region territory and the second electrode region according to predetermined pattern; In this first region territory andIn the second electrode region, prepare conductive film to form the first electrode and the second electrode, this first electrode withThe opposite end of this second electrode is tip design; One nanowire suspended liquid is provided, this is nanowire suspendedLiquid is scattered on this substrate; Energising makes to produce inhomogeneous field, mat between this first electrode and the second electrodeMake the nano wire in this nanowire suspended liquid be overlapped in this first electrode and by the effect of this inhomogeneous fieldBetween two electrodes and with this substrate contacts; On this first electrode and the second electrode folded establish conductive film withForm this transistorized source electrode and drain electrode; Be coated with insulating layer coating to cover this source electrode, drain electrode and this source electrodeAnd the region between drain electrode; On this insulating barrier, make this transistorized grid.
Compared with prior art, transistor that the embodiment of the present invention provides and preparation method thereof adopts nanometerLine, as transistorized carrier passage, is compared and is had good carrying with traditional polycrystalline or amorphous silicon transistorTransport factor, and nano wire can carry out high temperature growth on other substrate, and can not affect crystalThe selection of the substrate of pipe, widens the range of choice of transistor base greatly.
Brief description of the drawings
Fig. 1 is the transistorized cross section structure schematic diagram that embodiment of the present invention provides.
Fig. 2 is the transistorized processing procedure schematic diagram that embodiment of the present invention provides.
Main element symbol description
Transistor 100
Substrate 10
Photoresist layer 11
Nano wire 15
The first region territory 20
The first electrode 21
The second electrode region 30
The second electrode 31
Source electrode 40
Drain electrode 50
Insulating barrier 60
Grid 70
Detailed description of the invention
Below in conjunction with accompanying drawing, the present invention is described in further detail.
Refer to Fig. 1, the transistor 100 that embodiment of the present invention provides, it comprises substrate 10, nanometerLine 15, source electrode (source) 40, drain electrode (drain) 50, insulating barrier 60 with grid (gate) 70.
What this source electrode 40 was relative with these drain electrode 50 intervals is attached on this substrate 10, in the present embodiment,This source electrode 40 is laminated by two-layer conducting film with this drain electrode 50, and two of close this substrate 10The opposite end of conductive film layer is all tip design.
Understandable, this source electrode 40 can be also single layer structure with this drain electrode 50.
This nano wire 15 is overlapped between this source electrode 40 and the tip of this drain electrode 50 and is used as this source electrode 40 and is somebody's turn to doElectronics, electric hole transmission channel between drain electrode 50.
This insulating barrier 60 be covered in this source electrode 40, drain electrode 50 and between region. This grid 70 is stacked atOn this insulating barrier 60, preferred, this grid 70 be positioned at this nano wire 15 directly over.
Refer to Fig. 2, the present invention also provides the preparation method of above-mentioned transistor 100, and it comprises following stepSuddenly.
(1) provide a nanowire suspended liquid.
In the present embodiment, the array of the nano wire of first growing up on substrate, then uses solvent to makeThe nano-wire array of getting ready peels off on growth substrate, and adopts the mode of ultrasonic oscillation to enter nano wireRow concussion disperses to form nanowire suspended liquid.
In the present invention, the kind of this nano wire can be decided according to the actual requirements, therefore nanowire suspendedThe processing procedure of liquid also may be different according to different nano wire kind and pattern of growth, need to illustrateBe, no matter adopt which kind of method, as long as finally can obtain nanowire suspended liquid.
(2) provide a substrate 10, the mode of employing exposure imaging defines two and relatively establishes on this substrate 10The first region territory 20 of putting and the second electrode region 30.
Preferably, this substrate 10 is pliability transparent substrates. First on this substrate 10, apply photoresist layer 11,Then use the light shield with predetermined pattern to carry out exposure imaging so that this predetermined pattern is turned to this photoresist layer 11Record is to the first region territory 20 and the second electrode region that are oppositely arranged to define this on this substrate 1030。
In the present embodiment, this first region territory 20 and the second electrode region 30 are respectively pectination and establishMeter, the width of every broach is approximately greater than the diameter of this nano wire, and the end of every broach is all designed toSharp tooth.
Understandable, the shape of this first region territory 20 and the second electrode region 30 can be according to notSame design requirement is determined.
Understandable, can also adopt the modes such as other such as etching of mode to define on this substrate 10This first region territory 20 and the second electrode region 30.
(3) in the first region territory 20 and the interior conductive film of preparing of the second electrode region 30 to form firstElectrode 21 and the second electrode 31, then remove this photoresist layer 11 completely.
Adopt the mode of chemical deposition in this first region territory 20 and the interior deposition of the second electrode region 30This first electrode 21 and the second electrode 31. Preferably, control this first electrode 21 and the second electrode 31Deposit thickness be approximately about radius of nano wire 15 in this nanowire suspended liquid.
Understandable, can also adopt other mode at this first region territory 20 and the second electrodeThis first electrode 21 of the interior preparation in region 30 and the second electrode 31.
(4) this nanowire suspended liquid is scattered on this substrate 10.
Utilize suction pipe by this nanowire suspended drop on this substrate 10, to make the nanometer in this suspensionLine 15 intersperses among between this first electrode 21 and the second electrode 31.
Understandable, can also directly this substrate 10 be soaked and be placed in this nanowire suspended liquid, so that shouldNano wire 15 in suspension intersperses among between this first electrode 21 and the second electrode 31.
(5) energising is so that form inhomogeneous field between this first electrode 21 and the second electrode 31, non-by thisThe effect of uniform electric field is overlapped between this first electrode 21 and the second electrode 31 this nano wire 15.
This first electrode 21 and the second electrode 31 are connected on respectively on the positive and negative polarities of AC power with at thisBetween the first electrode 21 and the second electrode 31, form inhomogeneous field, be suspended in the nano wire in this suspensionAlign spy along the direction of electric field thereby 15 polarization occurs under the effect of this inhomogeneous fieldOther, in the present embodiment, because this first electrode 21 and the second electrode 31 are for pectination designs, andBe sharp tooth by the tip designs of every broach, therefore greatly increased directionality that nano wire 15 arranges withAnd attraction, thereby can make to intersperse among the nano wire 15 between this first electrode 21 and the second electrode 31Can be good at being overlapped between this first electrode 21 and the second electrode 31.
(6) thickness of increasing this first electrode 21 and the second electrode 31 is to define transistorized source electrode(source) 40 and drain electrode (drain) 50.
Repeat above-mentioned exposure imaging and conductive film deposition step, at this first electrode 21 and the second electrodeOn 31, the stacked electrode layer with certain altitude is to define source electrode 40 and the drain electrode 50 of this transistor 100.
(7) clean this substrate 10 to remove the unnecessary nanowire suspended liquid remaining on this substrate 10.
(8) be coated with insulating layer coating 60 to cover between this source electrode 40, drain electrode 50 and this source electrode 40 and drain electrode 50Region.
(9) on this insulating barrier 60, make grid (gate) 70.
Preferably, this grid 70, above the region between this source electrode 40 and drain electrode 50, is kept away with thisExempt from voltage reciprocal effect between electrode and cause reducing the carrier transport factor (mobility) of this transistor 100.
Compared with prior art, transistor 100 provided by the present invention and preparation method thereof adopts nano wireAs transistorized carrier passage, compare and there is good carrier with traditional polycrystalline or amorphous silicon transistorMobility, and nano wire can carry out high temperature growth on other substrate, and can not affect transistorThe selection of substrate, the range of choice of transistor base is widened greatly.
Be understandable that, those skilled in the art also can in spirit of the present invention, do other change wait forDesign of the present invention, as long as it does not depart from technique effect of the present invention and all can. These are according to spirit of the present inventionThe variation of doing, within all should being included in the present invention's scope required for protection.
Claims (7)
1. a transistor, it comprises nano wire, substrate, source electrode, drain electrode, insulating barrier and grid, this source electrode and drain electrode relative being attached on this substrate in interval, this nano wire is overlapped between this source electrode and drain electrode, this insulating barrier is covered in this source electrode, region between drain electrode and this source electrode and drain electrode, this grid is stacked on this insulating barrier, it is characterized in that, this source electrode comprises one first electrode, this drain electrode comprises one second electrode, the opposite end of this first electrode and this second electrode is tip-shape design, this nano wire be connected between this this first electrode and the tip of this second electrode and with this substrate contacts.
2. transistor as claimed in claim 1, is characterized in that: this source electrode and drain electrode are comb electrode.
3. transistor as claimed in claim 1, is characterized in that: this source electrode and drain electrode are sandwich construction, and the opposite end that is attached at the electrode layer on this substrate in this sandwich construction is tip design.
4. a transistorized preparation method, it comprises the steps:
One substrate is provided;
On this substrate, define the first region territory and the second electrode region according to predetermined pattern;
In this first region territory and the second electrode region, prepare conductive film to form the first electrode and the second electrode, the opposite end of this first electrode and this second electrode is tip design;
One nanowire suspended liquid is provided, this nanowire suspended liquid is scattered on this substrate;
Energising makes to produce inhomogeneous field between this first electrode and the second electrode, by the effect of this inhomogeneous field nano wire in this nanowire suspended liquid is overlapped between this first electrode and the second electrode and with this substrate contacts;
On this first electrode and the second electrode, fold and establish conductive film to form this transistorized source electrode and drain electrode;
Be coated with insulating layer coating to cover the region between this source electrode, drain electrode and this source electrode and drain electrode;
On this insulating barrier, make this transistorized grid.
5. transistorized preparation method as claimed in claim 4, is characterized in that: adopt the mode of exposure imaging to define the first region territory and the second electrode region according to predetermined pattern on this substrate.
6. transistorized preparation method as claimed in claim 4, is characterized in that: this first electrode and this second electrode are comb electrode, and its broach is sharp tooth design.
7. transistorized preparation method as claimed in claim 4, is characterized in that: the thickness of this first electrode and this second electrode is less than the diameter of this nano wire.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010524964.8A CN102456733B (en) | 2010-10-29 | 2010-10-29 | Transistor and preparation method thereof |
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| CN201010524964.8A CN102456733B (en) | 2010-10-29 | 2010-10-29 | Transistor and preparation method thereof |
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| CN102456733A CN102456733A (en) | 2012-05-16 |
| CN102456733B true CN102456733B (en) | 2016-05-04 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847581A (en) * | 2009-03-25 | 2010-09-29 | 中国科学院微电子研究所 | Manufacturing method of top gate ZnO multi-nanowire field effect transistor |
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| US7135728B2 (en) * | 2002-09-30 | 2006-11-14 | Nanosys, Inc. | Large-area nanoenabled macroelectronic substrates and uses therefor |
| US7181836B2 (en) * | 2003-12-19 | 2007-02-27 | General Electric Company | Method for making an electrode structure |
| JP2007158119A (en) * | 2005-12-06 | 2007-06-21 | Canon Inc | Electric element having nano wire and its manufacturing method, and electric element assembly |
| KR101069105B1 (en) * | 2009-02-18 | 2011-09-30 | 고려대학교 산학협력단 | Nanostructure, method of manufacturing the same and method of controlling electron beam for manufacturing nanostructure |
| CN101783367B (en) * | 2010-02-11 | 2012-10-17 | 复旦大学 | Nanowire MOS transistor based on III-V element and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101847581A (en) * | 2009-03-25 | 2010-09-29 | 中国科学院微电子研究所 | Manufacturing method of top gate ZnO multi-nanowire field effect transistor |
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