CN106252419B - Thin film transistor (TFT) and its manufacturing method, array substrate and display device - Google Patents
Thin film transistor (TFT) and its manufacturing method, array substrate and display device Download PDFInfo
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- CN106252419B CN106252419B CN201610849607.6A CN201610849607A CN106252419B CN 106252419 B CN106252419 B CN 106252419B CN 201610849607 A CN201610849607 A CN 201610849607A CN 106252419 B CN106252419 B CN 106252419B
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- fixed charge
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- active layer
- film transistor
- drain electrode
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052763 palladium Inorganic materials 0.000 description 2
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention discloses a kind of thin film transistor (TFT) and its manufacturing methods, array substrate and display device, belong to field of display technology.The thin film transistor (TFT) includes: underlay substrate；Fixed charge structure is formed on underlay substrate；Active layer, source electrode, drain and gate are formed on the underlay substrate for being formed with fixed charge structure, active layer is connect with source electrode and drain electrode respectively；Wherein, charge in fixed charge structure is fixed charge, fixed charge structure includes: the first fixed charge block and the second fixed charge block, source electrode is located in the first fixed charge block region in the orthographic projection on the first fixed charge block, drain electrode is located in the second fixed charge block region in the orthographic projection on the second fixed charge block, and fixed charge structure is contacted with active layer.The present invention without using high work function noble metal as source, drain electrode, good Ohmic contact can be formed between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of thin film transistor (TFT) and its manufacturing method, array substrate and
Display device.
Background technique
With the development of field of display technology, carbon nano-tube material is due to its excellent electric property, through frequently as active
The material of layer, is applied to film transistor device.In order to guarantee proper device operation, source, the leakage of film transistor device are needed
Good Ohmic contact is formed between pole and active layer, i.e., has between the source of thin film transistor (TFT), drain electrode and carbon nanotube active layer
There is low metal contact resistance.Therefore, the problem of how forming good Ohmic contact, becoming people's extensive concern.
In the prior art, it generallys use palladium (Pd), the noble metal of the high work functions such as golden (Au) is as film transistor device
Source, drain electrode, to form good Ohmic contact.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
In the prior art, the source using the noble metal of the high work functions such as Pd, Au as film transistor device, drain electrode, come
Good Ohmic contact is formed, cost of manufacture is higher.
Summary of the invention
In order to solve to use the noble metal of high work function as source, drain electrode, caused by the high problem of cost of manufacture, the present invention
Embodiment provides a kind of thin film transistor (TFT) and its manufacturing method, array substrate and display device.The technical solution is as follows:
In a first aspect, providing a kind of thin film transistor (TFT), the thin film transistor (TFT) includes:
Underlay substrate；
Fixed charge structure is formed on the underlay substrate；
Active layer, source electrode, drain and gate are formed on the underlay substrate for being formed with the fixed charge structure, it is described
Active layer is connected with the source electrode and the drain electrode respectively；
Wherein, the charge in the fixed charge structure is fixed charge, and the fixed charge structure includes: first fixed
Charge block and the second fixed charge block, it is fixed that orthographic projection of the source electrode on the first fixed charge block is located at described first
In charge block region, orthographic projection of the drain electrode on the second fixed charge block is located at the second fixed charge block
In region, and the fixed charge structure is contacted with the active layer.
Optionally, the charge in the fixed charge structure is negative electrical charge, and the material of the fixed charge structure is three oxygen
Change two aluminium.
Optionally, the charge in the fixed charge structure is positive charge, and the material of the fixed charge structure is nitridation
Silicon.
Optionally, buffer layer is formed on the underlay substrate；
The first via hole and the second via hole are formed on the buffer layer；
The fixed charge structure, the fixed charge are formed on the underlay substrate for being formed with the buffer layer
Structure is located on the same floor with the buffer layer, wherein and the first fixed charge block is located in first via hole, and described second
Fixed charge block is located in second via hole；
The active layer is formed on the underlay substrate for being formed with the fixed charge structure；
The source electrode and the drain electrode are formed on the underlay substrate for being formed with the active layer；
Gate insulation layer and the grid are sequentially formed on the underlay substrate for being formed with the source electrode and the drain electrode.
Second aspect, provides a kind of array substrate, and the array substrate includes: any film in first aspect
Transistor.
The third aspect, provides a kind of display panel, and the display panel includes: array substrate described in second aspect.
Fourth aspect, provides a kind of manufacturing method of thin film transistor (TFT), and the manufacturing method includes:
Fixed charge structure is formed on underlay substrate；
Active layer, source electrode, drain and gate are formed on the underlay substrate for being formed with the fixed charge structure, it is described to have
Active layer is connected with the source electrode and the drain electrode respectively；
Wherein, the charge in the fixed charge structure is fixed charge, and the fixed charge structure includes: first fixed
Charge block and the second fixed charge block, it is fixed that orthographic projection of the source electrode on the first fixed charge block is located at described first
In charge block region, orthographic projection of the drain electrode on the second fixed charge block is located at the second fixed charge block
In region, and the fixed charge structure is contacted with the active layer.
Optionally, the charge in the fixed charge structure is negative electrical charge, and the material of the fixed charge structure is three oxygen
Change two aluminium.
Optionally, the charge in the fixed charge structure is positive charge, and the material of the fixed charge structure is nitridation
Silicon.
Optionally, the formation fixed charge structure on underlay substrate, it is described to be formed with the fixed charge structure
Underlay substrate on formed active layer, source electrode, drain and gate, the active layer respectively with the source electrode and the drain electrode company
It connects, comprising:
Buffer layer is formed on the underlay substrate；
The first via hole and the second via hole are formed on the buffer layer；
The fixed charge structure, the fixed charge knot are formed on the underlay substrate for being formed with the buffer layer
Structure is located on the same floor with the buffer layer, wherein the first fixed charge block is located in first via hole, and described second is solid
Determine charge block to be located in second via hole；
The active layer is formed on the underlay substrate for being formed with the fixed charge structure；
The source electrode and the drain electrode are formed on the underlay substrate for being formed with the active layer；
Gate insulation layer and the grid are sequentially formed on the underlay substrate for being formed with the source electrode and the drain electrode.
Technical solution provided in an embodiment of the present invention has the benefit that
Thin film transistor (TFT) provided in an embodiment of the present invention and its manufacturing method, array substrate and display device, by serving as a contrast
Fixed charge structure is formed on substrate, it is electrostatically-doped to being carried out with the active layer region in source, drain contact, change active layer
Fermi level height and carrier concentration, so that forming good Ohmic contact between source, drain electrode and active layer.Without using height
The noble metal of work function can form good Ohmic contact between source, drain electrode and active layer, reduce as source, drain electrode
The manufacturing cost of thin film transistor (TFT).
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of thin-film transistor structure schematic diagram that an illustrative examples of the invention provide；
Fig. 2 is another thin-film transistor structure schematic diagram that an illustrative examples of the invention provide；
Fig. 3 is a kind of method for fabricating thin film transistor flow chart that an illustrative examples of the invention provide；
Fig. 4 is another method for fabricating thin film transistor flow chart that an illustrative examples of the invention provide.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Fig. 1 is a kind of structural schematic diagram of thin film transistor (TFT) provided in an embodiment of the present invention, as shown in Figure 1, the film is brilliant
Body pipe includes:
Underlay substrate 11.
Fixed charge structure 12 is formed on underlay substrate 11.
Active layer 13, source electrode 14, drain electrode 15 and grid are formed on the underlay substrate 11 for being formed with fixed charge structure 12
Pole 16, active layer 13 are connect with source electrode 14 and drain electrode 15 respectively.Wherein, active layer 13 can be made of carbon nanotube.
Further, the charge in fixed charge structure 12 is fixed charge, and fixed charge structure 12 includes: first fixed
Charge block 121 and the second fixed charge block 122, it is fixed that orthographic projection of the source electrode 14 on the first fixed charge block 121 is located at first
In 121 region of charge block, orthographic projection of the drain electrode 15 on the second fixed charge block 122 is located at the second fixed charge block 122
In region, and fixed charge structure 12 is contacted with active layer 13.
In conclusion thin film transistor (TFT) provided in an embodiment of the present invention, by forming fixed charge knot on underlay substrate
Structure, electrostatically-doped to carrying out with the active layer region in source, drain contact, fermi level height and the carrier for changing active layer are dense
Degree, so that forming good Ohmic contact between source, drain electrode and active layer.Without using high work function noble metal as source,
Drain electrode, can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
It should be noted that in thin-film transistor structure shown in FIG. 1, grid and gate insulation layer are located at source, on drain electrode,
This structure is known as top gate structure, and in practical applications, grid and gate insulation layer can also be under source, drain electrodes, specifically
Structure is as shown in Figure 2.Other structures can refer to Fig. 1 in Fig. 2, and the embodiment of the present invention does not repeat them here this.
Wherein, the charge in fixed charge structure can be negative electrical charge, and the material of the fixed charge structure can be three oxygen
Change two aluminium；Further, the charge in fixed charge structure may be positive charge, and the material of the fixed charge structure can be
Silicon nitride.Specifically, can will have negative electrical charge when needing to form p-type Ohmic contact between source, drain electrode and active layer
Aluminum oxide be set as fixed charge structure；When needing to form N-type Ohmic contact between source, drain electrode and active layer
It waits, fixed charge structure can be set by the silicon nitride with positive charge.
Fig. 1 is the structure when thin film transistor (TFT) provided in an embodiment of the present invention is the thin film transistor (TFT) using top gate structure
Schematic diagram, as shown in Figure 1, being formed with buffer layer 17 on underlay substrate 11, the material of the buffer layer can be silica
(SiOx)；The first via hole and the second via hole are formed on the buffer layer 17；On the underlay substrate 11 for being formed with buffer layer 17
It is formed with fixed charge structure 12, which is located on the same floor with buffer layer 17, shape after can making in this way
At active layer be flat one layer, be conducive to reduce segment difference.Specifically, the first fixed charge block 121 is located in the first via hole,
Second fixed charge block 122 is located in the second via hole.
Further, active layer 13 is formed on the underlay substrate 11 for being formed with fixed charge structure 12；It is being formed with
Source 14 and drain electrode 15 are formed on the underlay substrate 11 of active layer 13；In the underlay substrate 11 for forming source 14 and drain electrode 15
On be sequentially formed with gate insulation layer 18 and grid 16；Passivation layer 19 is formed on the underlay substrate 11 for being formed with grid 16.
Further, at least one via hole is formed on passivation layer 19, each via hole is filled with metal material, this at least one
A via hole is connected to source electrode 14, drain electrode at least one of 15 and grid 16.That is to say, can be formed on passivation layer 19 one or
Multiple via holes, it is exemplary, it could be formed with 3 via holes on passivation layer, source electrode 14 can be connect by a via hole with data line,
Drain electrode 15 can be connect by a via hole with pixel electrode, and grid 16 can be connect by a via hole with signal wire；It is practical
In, grid and signal wire can be arranged with same layer, and source electrode can be arranged with data line with same layer, at this point, a mistake need to only be arranged
The connection of drain electrode and pixel electrode is realized in hole.
It is exemplary, be provided in thin film transistor (TFT) shown in Fig. 1, on passivation layer metal material and source electrode, drain electrode,
Three via holes that grid is respectively communicated with, wherein be filled in the first via hole 201 metal material pass through passivation layer and gate insulation layer with
Source electrode connection, the metal material for being filled in the second via hole 202 pass through passivation layer and are connected to grid, are filled in third via hole 203
Metal material passes through passivation layer and gate insulation layer and is connected to drain electrode.
In thin film transistor (TFT) shown in Fig. 2, grid and signal wire same layer are arranged, and are provided with metal material on passivation layer
Two via holes that material is respectively communicated with source electrode, drain electrode, the metal material for being filled in the first via hole 201 passes through passivation layer and source electrode connects
Logical, the metal material for being filled in third via hole 203 passes through passivation layer and is connected to drain electrode.Wherein, which can be oxidation
Indium tin (English: Indium Tin Oxide；Referred to as: ITO).
It should be noted that Fig. 1 and thin film transistor (TFT) shown in Fig. 2 only schematically illustrate, all essences in Fig. 1 and Fig. 2
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
In conclusion thin film transistor (TFT) provided in an embodiment of the present invention, by forming fixed charge knot on underlay substrate
Structure, electrostatically-doped to carrying out with the active layer region in source, drain contact, fermi level height and the carrier for changing active layer are dense
Degree, so that forming good Ohmic contact between source, drain electrode and active layer.Without using high work function noble metal as source,
Drain electrode, can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
Fig. 3 is a kind of flow chart of the manufacturing method of thin film transistor (TFT) provided in an embodiment of the present invention, the thin film transistor (TFT)
Manufacturing method can be applied to manufacture thin film transistor (TFT) provided in an embodiment of the present invention.The manufacturing method of the thin film transistor (TFT) can
To comprise the following steps:
Step 301 forms fixed charge structure on underlay substrate.
Step 301 forms active layer, source electrode, drain and gate on the underlay substrate for being formed with fixed charge structure, has
Active layer is connect with source electrode and drain electrode respectively.
Wherein, the charge in fixed charge structure is fixed charge, which includes: the first fixed charge block
With the second fixed charge block, source electrode is located in the first fixed charge block region in the orthographic projection on the first fixed charge block,
Drain electrode is located in the second fixed charge block region in the orthographic projection on the second fixed charge block.
In conclusion method for fabricating thin film transistor provided in an embodiment of the present invention, solid by being formed on underlay substrate
Determine charge structure, it is electrostatically-doped to being carried out with the active layer region in source, drain contact, change active layer fermi level height and
Carrier concentration, so that forming good Ohmic contact between source, drain electrode and active layer.Without using the noble metal of high work function
As source, drain electrode, good Ohmic contact can be formed between source, drain electrode and active layer, reduces the system of thin film transistor (TFT)
Cause this.
Fig. 4 is the flow chart of the manufacturing method of another thin film transistor (TFT) provided in an embodiment of the present invention, the film crystal
The manufacturing method of pipe can be applied to manufacture thin film transistor (TFT) provided in an embodiment of the present invention.The manufacturing method of the thin film transistor (TFT)
May include the following steps:
Step 401 forms fixed charge structure on underlay substrate.
Optionally, the making material of the underlay substrate includes the transparent materials such as glass, silicon wafer, quartz and plastics, preferably
For glass.
It is exemplary, as shown in Figure 1, when thin film transistor (TFT) provided in an embodiment of the present invention is brilliant using the film of top gate structure
When body pipe, buffer layer can be formed on underlay substrate, forms via hole on the buffer layer, the shape on the buffer layer for be formed with via hole
At fixed charge structure.
Specifically, can be heavy by plasma enhanced chemical vapor on underlay substrate under conditions of 350 degrees Celsius
Area method (English: Plasma Enhanced Chemical Vapor Deposition；Buffer layer referred to as: PECVD) is formed, it should
The thickness of buffer layer can be 100 nanometers (nm)；Then through a patterning processes on the buffer layer being located on underlay substrate
Via hole is formed, which may include: photoetching coating, exposure, development, etching and photoresist lift off.Specifically, first
The position of fixed charge structure on the buffer layer is defined by photoetching coating, exposure, development, then passes through etching, photoresist stripping
From formation via hole.Wherein, which can be the dry etching of progress in the environment of carbon tetrafluoride and oxygen；Into one
Step ground is formed fixed charge layer by way of deposition, then passes through a composition work to the fixed charge layer
Skill forms the fixed charge structure being located in buffer layer via hole, which may include: photoetching coating, exposure, shows
Shadow, etching and photoresist lift off.Wherein, which can carve for the dry method carried out in the environment of carbon tetrafluoride and oxygen
Erosion.
It is exemplary, as shown in Fig. 2, when thin film transistor (TFT) provided in an embodiment of the present invention is common thin film transistor (TFT),
Gate metal figure can be formed on underlay substrate, wherein the gate metal figure includes: grid and signal wire.It is being formed
Gate insulation layer is formed on the underlay substrate for having gate metal figure, forms fixed electricity on the underlay substrate for be formed with gate insulation layer
Lotus structure.
Specifically, grid can be formed by the one of which in the various ways such as deposition, coating, sputtering on underlay substrate
Then pole metal layer forms gate metal figure by a patterning processes to the gate metal layer, which can
To include: photoetching coating, exposure, development, etching and photoresist lift off；Further, a variety of by deposition, coating, sputtering etc.
One of formation gate insulation layer film layer in mode, then gate insulation is formed by a patterning processes to the gate insulation layer film layer
Layer, a patterning processes may include: photoetching coating, exposure, development, etching and photoresist lift off；Further, by heavy
Product forms one layer of fixed charge layer, and the thickness range of the fixed charge layer can be 50nm~100nm, this hair
Bright embodiment is illustrated for a thickness of 100nm.Then a patterning processes shape is passed through to the fixed charge layer
At fixed charge structure, which may include: photoetching coating, exposure, development, etching and photoresist lift off.Its
In, which can be the dry etching of progress in the environment of carbon tetrafluoride and oxygen.
Step 402 forms active layer on the underlay substrate for being formed with fixed charge structure.
Specifically, passing through its in the various ways such as dip-coating, spin coating on the underlay substrate for being formed with fixed charge structure
A kind of middle formation active layer film layer, then active layer, a composition work are formed by a patterning processes to the active layer film layer
Skill includes: photoetching coating, exposure, development, etching and photoresist lift off.Wherein, which can be in the environment of oxygen
Reactive ion etching (the English: Reactive Ion Etching of lower progress；Referred to as: RIE).
Step 403 forms source, drain electrode on the underlay substrate for be formed with active layer.
It is exemplary, as shown in Figure 1, when thin film transistor (TFT) provided in an embodiment of the present invention is brilliant using the film of top gate structure
When body pipe, source, drain electrode can be formed on the underlay substrate for be formed with active layer, on forming active, drain electrode underlay substrate
Gate insulation layer is formed, forms grid on the underlay substrate for be formed with gate insulation layer.
Specifically, can be on the underlay substrate for be formed with active layer by the various ways such as deposition, coating, sputtering
Then one of formation source, drain metal layer form source, drain electrode by a patterning processes to the source, drain metal layer, should
Patterning processes may include: photoetching coating, exposure, development, etching and photoresist lift off；Further, pass through PECVD shape
At gate insulation layer, wherein the material of the gate insulation layer can be SiOx, and the thickness of the gate insulation layer can be 100nm；Further
Ground forms gate metal layer by way of sputtering, depositing, wherein the material of the gate metal layer can be molybdenum (Mo), the grid
The thickness of pole metal layer can be 220nm, then form grid, a structure by a patterning processes to the gate metal layer
Figure technique may include: photoetching coating, exposure, development, etching and photoresist lift off.
It is exemplary, as shown in Fig. 2, when thin film transistor (TFT) provided in an embodiment of the present invention is common thin film transistor (TFT),
Source, drain electrode can be formed on the underlay substrate for be formed with active layer.
Specifically, can be on the underlay substrate for be formed with active layer by the various ways such as deposition, coating, sputtering
One of formation source, drain metal layer, wherein the source, drain metal layer material can be copper (Cu) or nickel (Ni), should
Source, drain metal layer thickness can be 100nm, source, leakage then are formed by patterning processes to the source, drain metal layer
Pole, a patterning processes may include: photoetching coating, exposure, development, etching and photoresist lift off.
Step 404 forms passivation layer on forming active, drain electrode underlay substrate.
Specifically, forming passivation layer, the thickness of the passivation layer by PECVD on forming active, drain electrode underlay substrate
It can be 300nm.Wherein, the material of the passivation layer can be silicon nitride (SiNx).
Step 405 forms via hole on the passivation layer being located on underlay substrate.
It is exemplary, as shown in Figure 1, when thin film transistor (TFT) provided in an embodiment of the present invention is brilliant using the film of top gate structure
When body pipe, the first via hole 201 being connected to respectively with source electrode, drain electrode, grid, 203 and of third via hole can be formed on the passivation layer
Second via hole 202.
It is exemplary, as shown in Fig. 2, when thin film transistor (TFT) provided in an embodiment of the present invention is common thin film transistor (TFT),
The first via hole 201 and third via hole 203 being connected to respectively with source electrode, drain electrode can be formed on the passivation layer.
Specifically, via hole is formed on the passivation layer being located on underlay substrate by a patterning processes, a composition
Technique may include: photoetching coating, exposure, development, etching and photoresist lift off.
Step 406 fills metal material in via hole.
Specifically, deposited metal material in via hole by way of sputtering on the passivation layer, wherein the metal material can
Think ITO, the thickness of the metal material can be 135nm.Then a patterning processes are carried out to the metal material of deposition to complete
Manufacturing process, a patterning processes may include: photoetching coating, exposure, development, etching and photoresist lift off.
In conclusion method for fabricating thin film transistor provided in an embodiment of the present invention, solid by being formed on underlay substrate
Determine charge structure, it is electrostatically-doped to being carried out with the active layer region in source, drain contact, change active layer fermi level height and
Carrier concentration, so that forming good Ohmic contact between source, drain electrode and active layer.Without using the noble metal of high work function
As source, drain electrode, good Ohmic contact can be formed between source, drain electrode and active layer, reduces the system of thin film transistor (TFT)
Cause this.
It is apparent to those skilled in the art that for convenience and simplicity of description, the method for foregoing description
Specific steps, can be with reference to the corresponding process in previous embodiment, details are not described herein.
The embodiment of the invention also provides a kind of array substrate, which includes the thin of aforementioned any embodiment offer
Film transistor.Specifically, which includes underlay substrate, wherein underlay substrate and film crystal in the array substrate
The underlay substrate of pipe is same underlay substrate.Signal wire, data line, pixel electrode and aforementioned thin can be equipped on the underlay substrate
The drain electrode of film transistor, the thin film transistor (TFT) can be connect with pixel electrode layer, and the grid of thin film transistor (TFT) can be with signal wire
Connection, the source electrode of thin film transistor (TFT) can be connect with data line.
In conclusion array substrate provided in an embodiment of the present invention, by forming fixed charge structure on underlay substrate,
It is electrostatically-doped to being carried out with the active layer region in source, drain contact, change the fermi level height and carrier concentration of active layer,
So that forming good Ohmic contact between source, drain electrode and active layer.Without using high work function noble metal as source, leakage
Pole can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
Based on identical inventive concept, the embodiment of the invention also provides a kind of display devices, before which includes
The array substrate of embodiment offer is provided.The display device generally includes array substrate and display base plate, exemplary, array substrate and
Display base plate shapes box after adding liquid crystal, combines to form the display device with backlight module etc..
In the specific implementation, display device provided in an embodiment of the present invention can be mobile phone, tablet computer, television set, show
Show any products or components having a display function such as device, laptop, Digital Frame, navigator.
In conclusion display device provided in an embodiment of the present invention, by forming fixed charge structure on underlay substrate,
It is electrostatically-doped to being carried out with the active layer region in source, drain contact, change the fermi level height and carrier concentration of active layer,
So that forming good Ohmic contact between source, drain electrode and active layer.Without using high work function noble metal as source, leakage
Pole can form good Ohmic contact between source, drain electrode and active layer, reduce the manufacturing cost of thin film transistor (TFT).
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of thin film transistor (TFT) characterized by comprising
Underlay substrate；
Fixed charge structure is formed on the underlay substrate；
Active layer, source electrode, drain and gate are formed on the underlay substrate for being formed with the fixed charge structure, it is described active
Layer is connected with the source electrode and the drain electrode respectively；
Wherein, the charge in the fixed charge structure is fixed charge, and the fixed charge structure includes: spaced the
One fixed charge block and the second fixed charge block, orthographic projection of the source electrode on the first fixed charge block are located at described the
In one fixed charge block region, it is fixed that orthographic projection of the drain electrode on the second fixed charge block is located at described second
In charge block region, and the fixed charge structure is contacted with the active layer, the fixed charge structure and the leakage
Pole and the source electrode do not contact.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the charge in the fixed charge structure is negative electricity
Lotus, the material of the fixed charge structure are aluminum oxide.
3. thin film transistor (TFT) according to claim 1, which is characterized in that the charge in the fixed charge structure is positive electricity
Lotus, the material of the fixed charge structure are silicon nitride.
4. thin film transistor (TFT) according to any one of claims 1 to 3, which is characterized in that
Buffer layer is formed on the underlay substrate；
The first via hole and the second via hole are formed on the buffer layer；
The fixed charge structure, the fixed charge structure are formed on the underlay substrate for being formed with the buffer layer
It is located on the same floor with the buffer layer, wherein the first fixed charge block is located in first via hole, and described second is fixed
Charge block is located in second via hole；
The active layer is formed on the underlay substrate for being formed with the fixed charge structure；
The source electrode and the drain electrode are formed on the underlay substrate for being formed with the active layer；
Gate insulation layer and the grid are sequentially formed on the underlay substrate for being formed with the source electrode and the drain electrode.
5. a kind of array substrate characterized by comprising any thin film transistor (TFT) of Claims 1-4.
6. a kind of display device, which is characterized in that the display device includes array substrate described in claim 5.
7. a kind of manufacturing method of thin film transistor (TFT) characterized by comprising
Fixed charge structure is formed on underlay substrate；
Active layer, source electrode, drain and gate, the active layer are formed on the underlay substrate for being formed with the fixed charge structure
It is connected respectively with the source electrode and the drain electrode；
Wherein, the charge in the fixed charge structure is fixed charge, and the fixed charge structure includes: spaced the
One fixed charge block and the second fixed charge block, orthographic projection of the source electrode on the first fixed charge block are located at described the
In one fixed charge block region, it is fixed that orthographic projection of the drain electrode on the second fixed charge block is located at described second
In charge block region, and the fixed charge structure is contacted with the active layer, the fixed charge structure and the leakage
Pole and the source electrode do not contact.
8. manufacturing method according to claim 7, which is characterized in that the charge in the fixed charge structure is negative electricity
Lotus, the material of the fixed charge structure are aluminum oxide.
9. manufacturing method according to claim 7, which is characterized in that the charge in the fixed charge structure is positive electricity
Lotus, the material of the fixed charge structure are silicon nitride.
10. according to any manufacturing method of claim 7 to 9, which is characterized in that described formed on underlay substrate is fixed
Charge structure, it is described that active layer, source electrode, drain and gate are formed on the underlay substrate for being formed with the fixed charge structure,
The active layer is connected with the source electrode and the drain electrode respectively, comprising:
Buffer layer is formed on the underlay substrate；
The first via hole and the second via hole are formed on the buffer layer；
Form the fixed charge structure on the underlay substrate for being formed with the buffer layer, the fixed charge structure with
The buffer layer is located on the same floor, wherein the first fixed charge block is located in first via hole, the described second fixed electricity
Lotus block is located in second via hole；
The active layer is formed on the underlay substrate for being formed with the fixed charge structure；
The source electrode and the drain electrode are formed on the underlay substrate for being formed with the active layer；
Gate insulation layer and the grid are sequentially formed on the underlay substrate for being formed with the source electrode and the drain electrode.
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| CN114068703B (en) * | 2020-07-31 | 2024-03-19 | 北京华碳元芯电子科技有限责任公司 | Transistor and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1906770A (en) * | 2004-01-23 | 2007-01-31 | 惠普开发有限公司 | Transistor including a deposited channel region having a doped portion |
| CN103299445A (en) * | 2011-01-13 | 2013-09-11 | 国际商业机器公司 | Radiation hardened transistors based on graphene and carbon nanotubes |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1906770A (en) * | 2004-01-23 | 2007-01-31 | 惠普开发有限公司 | Transistor including a deposited channel region having a doped portion |
| CN103299445A (en) * | 2011-01-13 | 2013-09-11 | 国际商业机器公司 | Radiation hardened transistors based on graphene and carbon nanotubes |
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