CN102446747A - Method for forming side wall and p-channel metal oxide semiconductor (PMOS) transistor - Google Patents
Method for forming side wall and p-channel metal oxide semiconductor (PMOS) transistor Download PDFInfo
- Publication number
- CN102446747A CN102446747A CN2010105093856A CN201010509385A CN102446747A CN 102446747 A CN102446747 A CN 102446747A CN 2010105093856 A CN2010105093856 A CN 2010105093856A CN 201010509385 A CN201010509385 A CN 201010509385A CN 102446747 A CN102446747 A CN 102446747A
- Authority
- CN
- China
- Prior art keywords
- silicon
- germanium
- grid
- silicon substrate
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a method for forming a side wall and a p-channel metal oxide semiconductor (PMOS) transistor. The method for forming the side wall comprises the following steps that: a silicon substrate is provided, a grid is formed on the silicon substrate, and a germanium-silicon region is formed inside the silicon substrate at two sides of the silicon grid; the silicon substrate, the germanium-silicon region and the surface of the grid are oxidized so as to form an oxidized layer respectively on the silicon substrate, the germanium-silicon region and the surface of the grid; a silicon oxide layer is formed on the surface of the oxidized layer; a silicon nitride layer is formed on the surface of the silicon oxide layer; and the oxidized layer, the silicon oxide layer and the silicon nitride layer are etched to form a side wall on the periphery of the grid. Due to the adoption of the method, the problem that the side wall is easily separated from the silicon substrate because of no silicon oxide layer on the germanium-silicon region can be solved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation side wall and the transistorized method of PMOS.
Background technology
As everyone knows, mechanical stress can change the energy gap and the carrier mobility of silicon materials, and recently, mechanical stress has been played the part of more and more important role influencing the MOSFET aspect of performance.If suitably proof stress has improved charge carrier (electronics in the n-channel transistor, the hole in the p-channel transistor) mobility, just improved drive current, thereby stress can greatly improve transistorized performance.
The stress liner technology forms tensile stress laying (tensile stress liner) on nmos pass transistor; On the PMOS transistor, form compression laying (compressive stress liner); Thereby increased the drive current of PMOS transistor and nmos pass transistor, improved the response speed of circuit.Certificate research, the integrated circuit of the two stress liners technology of use can bring 24% speed lifting.
In existing high performance semiconductor device; At first form the zone formation germanium silicon in source region and drain region at needs; And then mix formation transistorized source region of PMOS and drain region; Forming germanium silicon is in order to introduce the compression that lattice mismatch forms between silicon and the germanium silicon (SiGe), further to improve compression, improving transistorized performance.
In the prior art, adopt in the transistorized forming process of PMOS of germanium silicon (SiGe) at source and drain areas, the method that around grid, forms side wall is: on silicon substrate, form grid; In the silicon substrate of grid both sides, carry out germanium (Ge) ion and inject, the zone that forms source region and drain region at needs forms embedded germanium silicon (embedded SiGe), mixes afterwards to form source region and drain region again; Surface in that silicon substrate, germanium silicon area and grid are formed forms silicon oxide layer; On silicon oxide layer, form silicon nitride layer; Dry back is carved said silicon oxide layer and silicon nitride layer, around said grid, forms side wall.This side wall produces the raceway groove that compression imposes on the grid below, can improve the mobility in hole like this, improves drive current, thereby can greatly improve transistorized performance.
Yet; Pass through transmission electron microscopy image analysis; Finding does not have silicon oxide layer with the side wall of the method formation of prior art on the contact-making surface of germanium silicon area and side wall, this will cause the stress difference between side wall and the germanium silicon to become big, lattice match imbalance; Make side wall easily and silicon substrate peel off, thereby influence the performance of device.
The one Chinese patent application that on December 9th, 2009, disclosed publication number was CN101599429 discloses a kind of method that forms side wall, does not also solve above-described technical problem.
Summary of the invention
The problem that the present invention solves is that method that prior art forms side wall causes on the contact-making surface of germanium silicon area and side wall and do not have silicon oxide layer, and the easy and silicon substrate of side wall is peeled off.
For addressing the above problem, the present invention provides a kind of method that forms side wall, comprising:
Silicon substrate is provided, is formed with grid on the said silicon substrate, be formed with the germanium silicon area in the silicon substrate of said grid both sides;
The surface of the said silicon substrate of oxidation, germanium silicon area and grid forms oxide layer on the surface of said silicon substrate, germanium silicon area and grid;
Form silicon oxide layer on said oxide layer surface;
Form silicon nitride layer on said silicon oxide layer surface;
Return to carve said silicon oxide layer and silicon nitride layer and form side wall on every side at said grid.
Optional, the surface of the said silicon substrate of said oxidation, germanium silicon area and grid is the surface with the said silicon substrate of ozone oxidation, germanium silicon area and grid.
Optional, said surface with the said silicon substrate of ozone oxidation, germanium silicon area and grid comprises:
Form ozone plasma Deng ionization ozone;
Surface with the said silicon substrate of said ozone plasma oxidation, germanium silicon area and grid.
Optional, said surface with the said silicon substrate of ozone oxidation, germanium silicon area and grid comprises:
The said silicon substrate of heating in 400 ℃～580 ℃ scopes;
Flow with 15000～27000sccm feeds ozone in the chamber at said silicon substrate place the surface of the said silicon substrate of oxidation, germanium silicon area and grid.
The present invention also provides a kind of formation PMOS transistorized method, comprising:
Silicon substrate is provided;
On said silicon substrate, form grid;
In the silicon substrate of said grid both sides, form the germanium silicon area;
The germanium silicon area is carried out P type ion inject, form source region and drain region;
The surface of the said silicon substrate of oxidation, germanium silicon area and grid forms oxide layer on the surface of said silicon substrate, germanium silicon area and grid;
Form silicon oxide layer on said oxide layer surface;
Form silicon nitride layer on said silicon oxide layer surface;
Return to carve said silicon oxide layer and silicon nitride layer and form side wall on every side at said grid.
Optional, also comprise:
With said side wall is mask, and said germanium silicon area is carried out P type ion light dope.
Optional, said P type ion is the boron ion.
Compared with prior art, the present invention has the following advantages:
The present invention is before silicon oxide layer deposited; Elder generation is with the surface oxidation of silicon substrate, germanium silicon area and grid; On the surface of silicon substrate, germanium silicon area and grid, form very thin oxide layer; After this forming silicon oxide layer on the oxide layer and be positioned at the silicon nitride layer on the silicon oxide layer, returning then and carve silicon oxide layer and silicon nitride layer formation side wall.Because the adhesiveness of oxide layer and silicon oxide layer is better, can overcome on the germanium silicon area does not have silicon oxide layer, makes the problem that side wall is easy and silicon substrate is peeled off.
Description of drawings
Fig. 1 is the flow chart of the transistorized method of formation PMOS of the specific embodiment of the invention;
Fig. 2 a～Fig. 2 e is the transistorized cross-sectional view of formation PMOS of the specific embodiment of the invention;
Fig. 3 is the schematic flow sheet of the formation side wall of the specific embodiment of the invention.
Embodiment
Side wall with the method for prior art forms does not have silicon oxide layer on the contact-making surface of germanium silicon area and side wall, cause stress difference between side wall and the germanium silicon area to become big, lattice match and lack of proper care, and the easy and silicon substrate of side wall is peeled off, thereby influences the performance of device.The inventor studies intensively through great efforts, finds following reason: form germanium silicon if utilize germanium ion to inject, when forming germanium silicon, the surface of germanium silicon area is damaged owing to the bombardment of germanium ion; When utilizing the germanium and silicon epitaxial growth to form germanium silicon, the surface of germanium silicon area and the adhesiveness of silica are also bad.After in silicon substrate, forming the germanium silicon area; When the germanium silicon area is carried out ion injection formation source region and drain region; Injection face makes the surface of germanium silicon area and the adhesiveness of silica continue variation because ion bombardment further sustains damage, and causes not forming silicon oxide layer on the surface of germanium silicon area.
The method of the formation side wall of the specific embodiment of the invention; With ion inject or germanium and silicon epitaxial be grown in form the germanium silicon area in the silicon substrate after; At first with the surface oxidation of silicon substrate, germanium silicon area and grid; On the surface of silicon substrate, germanium silicon area and grid, form very thin oxide layer, after this forming silicon oxide layer on the oxide layer and be positioned at the silicon nitride layer on the silicon oxide layer, return then and carve silicon oxide layer and silicon nitride layer formation side wall.
Fig. 1 is the flow chart of the transistorized method of formation PMOS of the specific embodiment of the invention, and with reference to figure 1, the transistorized method of formation PMOS of the specific embodiment of the invention comprises:
Step S1 provides silicon substrate;
Step S2 forms grid on said silicon substrate;
Step S3 forms the germanium silicon area in the silicon substrate of said grid both sides;
Step S4 carries out P type ion to the germanium silicon area and injects, and forms source region and drain region;
Step S5, the surface of the said silicon substrate of oxidation, germanium silicon area and grid forms oxide layer on the surface of said silicon substrate, germanium silicon area and grid;
Step S6 forms silicon oxide layer on said oxide layer surface;
Step S7 forms silicon nitride layer on said silicon oxide layer surface;
Step S8 return to carve said silicon oxide layer and silicon nitride layer and forms side wall on every side at said grid.
Fig. 2 a～Fig. 2 e is the formation PMOS transistor cross-sectional view of the specific embodiment of the invention.In order to make those skilled in the art better understand the present invention, below in conjunction with the be elaborated transistorized method of formation PMOS of the specific embodiment of the invention of accompanying drawing and specific embodiment.
In conjunction with reference to figure 1 and Fig. 2 a, execution in step S1 provides silicon substrate, and step S2, on said silicon substrate, forms grid.Be specially:
With reference to figure 2a, silicon substrate 20 is provided, on this silicon substrate, form grid 21.On silicon substrate 20, form grid 21, its concrete grammar is: on silicon substrate 20, form conductive layer, the material of this conductive layer can be polysilicon, also can be metal, perhaps also can be for well known to a person skilled in the art other electric conducting materials.After forming conductive layer, utilize photoetching, etching technics patterned conductive layer to form grid 21.In this specific embodiment of the present invention, grid 21 is a polysilicon gate.
Therefore need to prove that be formed with gate dielectric layer between silicon substrate 20 and the grid 21, this is a techniques well known, its forming process is not elaborated in the text, also do not illustrate gate dielectric layer among the figure.
In conjunction with reference to figure 1 and Fig. 2 b, execution in step S3, formation germanium silicon area 22 the silicon substrate 20 of said grid both sides in.With reference to figure 2b; On the surface of silicon substrate 20 and grid 21 compositions, form the mask layer (not shown); And the pattern mask layer, expose the zone (in forming the technology of metal-oxide-semiconductor, this zone is as source-drain area) of grid 21 both sides; With the mask layer is that mask carries out the germanium and silicon epitaxial growth to silicon substrate 20 or germanium ion injects, and in the silicon substrate 20 of grid 21 both sides, forms germanium silicon area 22.Form germanium silicon area 22 if use germanium ion to inject, in carrying out the germanium ion injection process, because the effect of ion bombardment; When injecting germanium ion, injection face is damaged owing to the germanium ion bombardment, after forming germanium silicon area 22; The surperficial damaged of germanium silicon area 22; Make the adhesiveness variation of itself and silica,, be difficult on the surface of germanium silicon area and form silica if continue to form silica on the surface of germanium silicon area 22; In order to make silica can be formed on the germanium silicon face, need handle the surface of germanium silicon area.In addition, if use germanium and silicon epitaxial to be grown in the interior germanium silicon area that forms of silicon substrate of grid both sides, the surface of germanium silicon area and the adhesiveness of silica neither be fine.
Continue to combine with reference to figure 1 and Fig. 2 b, execution in step S4 carries out P type ion to germanium silicon area 22 and injects, and forms source region and drain region.
After forming germanium silicon area 22, germanium silicon area 22 is carried out P type ion doping, form source region and drain region.In this specific embodiment, carry out the P type ion that P type ion doping uses and be boron (B) ion.Do not illustrate the forming process in source region and drain region among the figure.Form in the process in source region and drain region in the doping of P type, also can further cause damage when injecting, influence the surface of germanium silicon area 22 and the adhesiveness of silica the surface of germanium silicon area 22 owing to ion.
In conjunction with reference to figure 1 and Fig. 2 c, execution in step S5, the surface of the said silicon substrate of oxidation 20, germanium silicon area 22 and grid 21 forms oxide layer 23 on the surface of said silicon substrate 20, germanium silicon area 22 and grid 21.In the specific embodiment of the invention, with the surface of the said silicon substrate of ozone oxidation 20, germanium silicon area 22 and grid 21.Use the concrete grammar on the said silicon substrate of ozone oxidation 20 surfaces to be: to wait ionization ozone to form ozone plasma; Surface with the said silicon substrate of ozone plasma oxidation 20, germanium silicon area 22 and grid 21.Its reaction principle is on germanium silicon area surface: O+SiGe → SiO
2+ GeO
2On silicon substrate 20 surfaces and the reaction principle on grid 21 (using polysilicon gate in this specific embodiment of the present invention) surface be: O+Si → SiO
2The surface of silicon substrate 20, germanium silicon area 22 and the grid of handling through ozone-plasma 21 forms oxide layer 23, and this oxide layer 23 is the oxide layer that comprises silica and germanium oxide.
In other embodiments, also can use the surface of additive method silicon oxide substrate, germanium silicon area and grid, for example the said silicon substrate of heating in 400 ℃～580 ℃ scopes; Ozone is fed in the chamber at said silicon substrate place the surface of the said silicon substrate of oxidation 20, germanium silicon area 22 and grid 21 with the flow of 15000～27000sccm.The silicon on silicon substrate 20 surfaces heats oxidized generation silica in 400 ℃～580 ℃ scopes, reaction principle is: O+Si → SiO
2The germanium silicon on germanium silicon area surface heats oxidized generation silica and germanium oxide in 400 ℃～580 ℃ scopes, its reaction principle is: O+SiGe → SiO
2+ GeO
2The silicon on polysilicon gate surface heats oxidized generation silica in 400 ℃～580 ℃ scopes, reaction principle is: O+Si → SiO
2
Afterwards, in conjunction with Fig. 1 and Fig. 2 d, execution in step S6 forms silicon oxide layer 24 on said oxide layer 23 surfaces; Step S7 forms silicon nitride layer 25 on said silicon oxide layer 24 surfaces.After forming oxide layer 23 among the step S5, form silicon oxide layer 24,, the shortcoming that germanium silicon area top does not have silicon oxide layer therefore can not occur because the adhesiveness of oxide layer 23 and silicon oxide layer 24 is fine on the surface of oxide layer 23.The method that forms silicon oxide layer 24 is chemical vapour deposition (CVD).
After forming silicon oxide layer 24, utilize chemical vapour deposition (CVD) on silicon oxide layer 24, to form silicon nitride layer 25.
After forming silicon oxide layer 24 and silicon nitride layer 25, combine with reference to figure 1 and Fig. 2 e, execution in step S8 returns and carves silicon oxide layer 24 and silicon nitride layer 25 and form side wall on every side at said grid 21.Its concrete formation method is: at whole silicon wafer surface deposition one deck silicon oxide layer 24, and then deposition one deck silicon nitride layer 25 on the silicon oxide layer 24, utilize dry etch process to return subsequently and carve silicon oxide layer 24 and silicon nitride layer 25.Because used anisotropic etching instrument uses ion sputtering to fall most silica and silicon nitride; Die back to carve and do not need mask; After grid exposes, stop back carving, but not all silica and silicon nitride have all been removed; Keep partial oxidation silicon and silicon nitride on the sidewall of grid, thereby around grid, formed side wall.
The transistorized method of formation PMOS of the present invention is when forming side wall; Before silicon oxide layer deposited; Earlier, on the surface of silicon substrate, germanium silicon area and grid, form very thin oxide layer with the surface oxidation of silicon substrate, germanium silicon area and grid, then on the germanium silicon area owing to oxidation has very thin oxide layer; After this forming silicon oxide layer on the oxide layer and be positioned at the silicon nitride layer on the silicon oxide layer, returning then and carve silicon oxide layer and silicon nitride layer formation side wall.Because the adhesiveness of oxide layer and silicon oxide layer is better, can overcome on the germanium silicon area does not have silicon oxide layer, makes the problem that side wall is easy and silicon substrate is peeled off.
In specific embodiment of the present invention, form the transistorized method of PMOS and also comprise: with said side wall is mask, and said germanium silicon area is carried out P type ion light dope, forms the source region and the drain region of LDD structure.The ion that said P type light dope uses is the boron ion.
Afterwards can be at the surface deposition interlayer dielectric layer of silicon chip, interlayer dielectric layer is etched on source region, drain region and the grid forms contact hole, filled conductive material in contact hole; Tungsten for example forms the contact plug, and then on interlayer dielectric layer depositing conducting layer; For example can be aluminum metal layer; The etching conductive layer forms interconnection line, and contact plug and interconnection line have constituted the transistorized interconnection structure of PMOS, and other structures of PMOS transistor AND gate are interconnected.The method that forms interconnection line and contact plug also can use dual-damascene technics to form, and this is those skilled in the art's a known technology, and this does not do detailed description.
The present invention also provides a kind of method that forms side wall, and Fig. 3 is the method for the formation side wall of the specific embodiment of the invention, and with reference to figure 3, the method for the formation side wall of the specific embodiment of the invention comprises:
Step S31 provides silicon substrate, is formed with grid on the said silicon substrate, is formed with the germanium silicon area in the silicon substrate of said grid both sides;
Step S32, the surface of the said silicon substrate of oxidation, germanium silicon area and grid forms oxide layer in said silicon substrate, germanium silicon area and gate surface;
Step S33 forms silicon oxide layer on said oxide layer surface;
Step S34 forms silicon nitride layer on said silicon oxide layer surface;
Step S35 return to carve said silicon oxide layer and silicon nitride layer and forms side wall on every side at said grid
Based on the transistorized method of above-described formation PMOS; The method of formation side wall of the present invention forms in the process of the transistorized method of PMOS in explanation; Done detailed description; Here do not elaborate, those skilled in the art can be known the method that forms side wall according to the above transistorized method of formation PMOS.The corresponding relation of concrete formation step is: step S31 is corresponding to step S1, step S2, step S3, step S4, and step S32 is corresponding to step S5, and step S33 is corresponding to step S6, and step S34 is corresponding to step S7, and step S35 is corresponding to step S8.
The above is merely specific embodiment of the present invention; In order to make those skilled in the art better understand spirit of the present invention; Yet protection scope of the present invention is not a limited range with the specific descriptions of this specific embodiment; Any those skilled in the art can make an amendment specific embodiment of the present invention, and not break away from protection scope of the present invention in the scope that does not break away from spirit of the present invention.
Claims (8)
1. a method that forms side wall is characterized in that, comprising:
Silicon substrate is provided, is formed with grid on the said silicon substrate, be formed with the germanium silicon area in the silicon substrate of said grid both sides;
The surface of the said silicon substrate of oxidation, germanium silicon area and grid forms oxide layer in said silicon substrate, germanium silicon area and gate surface;
Form silicon oxide layer on said oxide layer surface;
Form silicon nitride layer on said silicon oxide layer surface;
Return to carve said silicon oxide layer and silicon nitride layer and form side wall on every side at said grid.
2. the method for formation side wall as claimed in claim 1 is characterized in that, the surface of the said silicon substrate of said oxidation, germanium silicon area and grid is the surface with the said silicon substrate of ozone oxidation, germanium silicon and grid.
3. the method for formation side wall as claimed in claim 2 is characterized in that, said surface with the said silicon substrate of ozone oxidation, germanium silicon area and grid comprises:
Form ozone plasma Deng ionization ozone;
Surface with the said silicon substrate of said ozone plasma oxidation, germanium silicon area and grid.
4. the method for formation side wall as claimed in claim 2 is characterized in that, saidly comprises with the said silicon substrate of ozone oxidation, germanium silicon area and gate surface:
The said silicon substrate of heating in 400 ℃～580 ℃ scopes;
Flow with 15000～27000sccm feeds ozone in the chamber at said silicon substrate place the surface of the said silicon substrate of oxidation, germanium silicon area and grid.
5. one kind forms the transistorized method of PMOS, it is characterized in that, comprising:
Silicon substrate is provided;
On said silicon substrate, form grid;
In the silicon substrate of said grid both sides, form the germanium silicon area;
The germanium silicon area is carried out P type ion inject, form source region and drain region;
The surface of the said silicon substrate of oxidation, germanium silicon area and grid forms oxide layer in said silicon substrate, germanium silicon area and gate surface;
Form silicon oxide layer on said oxide layer surface;
Form silicon nitride layer on said silicon oxide layer surface;
Return to carve said silicon oxide layer and silicon nitride layer and form side wall on every side at said grid.
6. the transistorized method of formation PMOS as claimed in claim 5 is characterized in that also comprise: with said side wall is mask, and said germanium silicon area is carried out P type ion light dope.
7. the transistorized method of formation PMOS as claimed in claim 5 is characterized in that said P type ion is the boron ion.
8. the transistorized method of formation PMOS as claimed in claim 5 is characterized in that, the said method that formation germanium silicon area uses in the silicon substrate of said grid both sides is that germanium and silicon epitaxial growth or germanium ion inject.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105093856A CN102446747A (en) | 2010-10-14 | 2010-10-14 | Method for forming side wall and p-channel metal oxide semiconductor (PMOS) transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105093856A CN102446747A (en) | 2010-10-14 | 2010-10-14 | Method for forming side wall and p-channel metal oxide semiconductor (PMOS) transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102446747A true CN102446747A (en) | 2012-05-09 |
Family
ID=46009142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105093856A Pending CN102446747A (en) | 2010-10-14 | 2010-10-14 | Method for forming side wall and p-channel metal oxide semiconductor (PMOS) transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102446747A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1624870A (en) * | 2003-11-04 | 2005-06-08 | 国际商业机器公司 | Oxidation method for altering a film structure and CMOS transistor structure formed therewith |
| CN101378021A (en) * | 2007-08-29 | 2009-03-04 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| US20090057755A1 (en) * | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Spacer undercut filler, method of manufacture thereof and articles comprising the same |
| CN101490857A (en) * | 2006-06-30 | 2009-07-22 | 飞思卡尔半导体公司 | Method for forming a semiconductor device and structure thereof |
| CN101853813A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating method thereof |
-
2010
- 2010-10-14 CN CN2010105093856A patent/CN102446747A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1624870A (en) * | 2003-11-04 | 2005-06-08 | 国际商业机器公司 | Oxidation method for altering a film structure and CMOS transistor structure formed therewith |
| CN101490857A (en) * | 2006-06-30 | 2009-07-22 | 飞思卡尔半导体公司 | Method for forming a semiconductor device and structure thereof |
| US20090057755A1 (en) * | 2007-08-27 | 2009-03-05 | International Business Machines Corporation | Spacer undercut filler, method of manufacture thereof and articles comprising the same |
| CN101378021A (en) * | 2007-08-29 | 2009-03-04 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN101853813A (en) * | 2009-03-31 | 2010-10-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and fabricating method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7521307B2 (en) | CMOS structures and methods using self-aligned dual stressed layers | |
| JP5324760B2 (en) | MOSFET having source / drain recesses with inclined sidewall surfaces and method for forming the same | |
| TWI511273B (en) | Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions | |
| CN100378901C (en) | Strained FinFET CMOS device structures | |
| CN100428475C (en) | Semiconductor structure having improved carrier mobility and method of manufacture. | |
| KR20090023615A (en) | Improved cmos devices with stressed channel regions, and methods for fabricating the same | |
| CN1838417A (en) | Semiconductor structure and its forming method | |
| KR20110131322A (en) | Isolated tri-gate transistor fabricated on bulk substrate | |
| CN1956221A (en) | Transistor with medium stress generation region and manufacturing method thereof | |
| CN102217050A (en) | CMOS device comprising nmos transistors and pmos transistors having increased strain-inducing sources and closely spaced metal silicide regions | |
| CN101958328B (en) | CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN102903639A (en) | MOS (Metal Oxide Semiconductor) transistor, substrate provided with stress layers and formation method of substrate provided with stress layer | |
| CN103066122A (en) | Metal-oxide-semiconductor field effect transistor (MOSFET) and manufacturing method thereof | |
| CN101894799B (en) | Method for improving electron mobility of NMOS transistor | |
| CN101226900A (en) | Structure and method of fabricating electrical structure having improved charge mobility | |
| CN102364663A (en) | Grid side wall etching method, metal-oxide-semiconductor (MOS) device manufacturing method and MOS device | |
| CN102637601A (en) | Forming method of MOS (metal oxide semiconductor) transistor with buried channel | |
| KR20070101058A (en) | Method of forming a fin field effect transistor | |
| CN103367226B (en) | Method, semi-conductor device manufacturing method | |
| CN102082126B (en) | Method for manufacturing semiconductor device | |
| CN102446747A (en) | Method for forming side wall and p-channel metal oxide semiconductor (PMOS) transistor | |
| CN101197324A (en) | CMOS device and method for forming its stress film | |
| CN101471247A (en) | Method for manufacturing semiconductor device and semiconductor device | |
| CN102593001B (en) | Method for introducing strain to channel and device manufactured by the same | |
| JP2003249648A (en) | Semiconductor device and manufacturing method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121108 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120509 |