JP2003249648A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a strain silicon channel transistor with small gate leakage current and a method for manufacturing it, since, in a strain silicon channel transistor using a buffer film, gate leakage current caused by crystallinity and roughness of the surface of a strain silicon film is generated so that an operation characteristic of the transistor is deteriorated. <P>SOLUTION: A field effect transistor comprises a first semiconductor film that is formed on a principal surface of a semiconductor substrate and acts as a source region, a second semiconductor film laminated on the first semiconductor film, and a third semiconductor film that is laminated on the second semiconductor film and acts as a drain region. A fourth semiconductor film is formed on a side surface of the second semiconductor film. This semiconductor device comprises the fourth semiconductor film as a channel region. By directly forming the fourth semiconductor film which acts as the channel region on the side surface of the second semiconductor film, a strain silicon film with less crystal defect and small roughness of the surface is acquired, and gate leakage current is decreased. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a strained silicon channel field effect transistor which is a field effect transistor using strained silicon as a channel and a method for manufacturing the same.
In particular, the present invention relates to a vertical strained silicon channel field effect transistor structure having a small gate leak current and a manufacturing method thereof.

[0002]

2. Description of the Related Art The structure of a conventionally known field effect transistor using silicon germanium will be described with reference to FIG. A buffer film 202 made of silicon germanium is formed on a substrate 201 of single crystal silicon whose main surface has a crystal plane of (100). Buffer film 202
Is 5 micrometers, for example, and the Ge composition ratio is modulated so that the Ge composition ratio is inclined in the film thickness direction as shown in FIG. When the Ge composition ratio in the silicon germanium film increases, the lattice distance of the crystal lattice of the silicon germanium film increases. When a silicon film is formed on the buffer film 202, the silicon film grows according to the crystal lattice constant of the underlying silicon germanium film, so that the original silicon crystal lattice is parallel to the main surface of the substrate 201. In order to be pulled inside, the strained silicon film 203
Is formed. A gate insulating film 204 is formed on the strained silicon film 203. A gate electrode 205 is formed on the gate insulating film 204.
A side spacer 206 is formed on the side surface of the No. 5.
The channel region under the gate insulating film 204 is formed in the strained silicon film 203. MV Fischetti and SE Laux
Is the Journal of Applied Physics 80th
Volume 15, Pages 2234 to 2252, 1996 (Journal of Applied Physics, vol. 80 No. 15
(1996) pp. 2234-2252), the mobility of electrons and holes in strained silicon increases by several tens% to several hundreds of% as compared with unstrained silicon. Therefore,
Electrons and holes flowing between the source region 207a and the drain region 207b can travel in the channel region under the gate insulating film 204 at high speed, and the transistor can operate at high speed. A device applying such a strained silicon crystal to a channel is, for example, the 2001 BUILS I Symposium Technical Digest page 59 to 60 (2001 Symposium on VLSI Technology).
pp. 59-60).

[0003]

SUMMARY OF THE INVENTION In the above conventional structure,
In order to apply tensile stress to the silicon film forming the channel region, it is necessary to form a lattice-relaxed silicon germanium film. To form a lattice-relaxed silicon germanium film, when forming a silicon germanium film on a silicon substrate, a buffer film (buffer SiGe layer) in which the composition ratio of Si and Ge is gradually increased is formed on the silicon substrate and the relaxed silicon germanium layer ( Membrane). Since this buffer film has poor crystallinity and unevenness occurs on the surface, there is a problem that the crystallinity and surface roughness of the strained silicon film formed on the buffer film deteriorate. When the crystallinity or roughness of the strained silicon film is deteriorated, a leak current (gate leak current) from the gate electrode to the channel region is generated, which deteriorates the operating characteristics of the transistor.

An object of the present invention is to provide a strained silicon transistor having a small gate leak current.

Another object of the present invention is to provide a method of manufacturing a strained silicon transistor having a small gate leak current.

[0006]

For a semiconductor device having a small gate leakage current for the above purpose, a first semiconductor film formed on the main surface of a semiconductor substrate and a first semiconductor film are laminated on the first semiconductor film. A material having a second semiconductor film, a third semiconductor film stacked on the second semiconductor film, and a crystal lattice constant different from a steady-state crystal lattice constant on a side surface of the second semiconductor film on which the second semiconductor film is not stacked. To achieve a semiconductor device having a fourth semiconductor film formed by.

Further, in order to manufacture a semiconductor device having a small gate leakage current, the first surface is formed on the main surface of the semiconductor substrate.
A step of forming an insulating film, a step of forming a second insulating film on the first insulating film, a step of forming a third insulating film on the second insulating film, and a step of forming a third insulating film on the third insulating film. A step of forming a fourth insulating film, a step of forming a fifth insulating film on the fourth insulating film,
Opening the fifth insulating film from the first insulating film to expose the surface of the semiconductor substrate, forming the first semiconductor film in the opening, and forming the second semiconductor film on the first semiconductor film. This is achieved by a manufacturing method including a step and a step of forming a third semiconductor film on the second semiconductor film.

Furthermore, in addition to the above-described manufacturing method, a manufacturing method having a step of forming a fourth semiconductor film on the side surface of the second semiconductor film can be achieved.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The structure of a vertical gate MOS of the present invention will be outlined below with reference to FIG.

In FIG. 36, 3501 is the drain of the MOS transistor, 3505 is the gate, and 3508 is the source. A gate insulating film 3502 is provided under the gate, and strained silicon is formed under the gate insulating film 3502. Furthermore,
The strained silicon is formed on the SiGe layer. 35
Reference numerals 03 and 3507 denote drain and source insulators, for example, phosphorus-doped glass (PSG) or the like is used. Reference numerals 3504 and 3506 are insulators made of SiN or the like for the drain and the source, respectively. According to the present invention, holes can move at high speed in the strained silicon channel under the gate insulating film, and a semiconductor element capable of high-speed switching and signal transmission can be provided.

By thus providing the Si layer on the SiGe layer, the Si layer becomes a strained Si layer and a high-speed channel can be formed. This is because the difference in lattice constant between the strained Si and the SiGe layer causes the vertical direction of Si in FIG.
Becomes

With such a structure, it is possible to eliminate the conventional buffer layer, and it is possible to form a strained silicon layer with low defect generation. Further, by controlling the film pressure, the gate length (vertical direction in the drawing) can be shortened to, for example, 20 nm or less.

Further, since the structure of the present application can be formed in a cylindrical shape or a cubic shape, the cylindrical shape can be a structure in which the gate is taken out from any portion on the circumference or the gate electrode is formed. Further, if it is a cube, it is possible to take out the gate or form the gate electrode from any surface.

(Embodiment 1) An embodiment of the present invention will be described below. In this embodiment, a vertical field effect transistor that operates using a strained silicon film as a channel region without using a buffer film will be described with reference to FIG.

A substrate 101 made of single crystal silicon whose main surface has a crystal plane of (100) has a phosphorus concentration of 10 ¹⁵ to 10 ¹⁶ / cm 3.
^Three n-type wells 102 are formed. n-type well 1
On the upper surface of 02, the concentration of wiring is 10 ¹⁹ to 10 ²⁰ / cm ³
P-type diffusion film 103 is formed. The n-type well 102 is electrically insulated from other regions by the isolation oxide film 104 formed by the trench isolation method. A first silicon film 105 is formed on the p-type diffusion film 103. On the side surface of the first silicon film 105,
A p-type silicon film 106 is formed, and a first oxide film 107 containing boron is formed on the side surface of the first p-type silicon film 106.
And a first nitride film 112 is laminated on the first oxide film 107. A silicon germanium film 108 is stacked on the first silicon film 105.
A strained silicon film 109 is formed on the side surface of the silicon germanium film 108. A gate insulating film 110 is formed on the side surface of the strained silicon film 109, and a gate electrode 111 is formed on the side surface of the gate insulating film 110.
A second silicon film 113 is laminated on the silicon germanium film 108. A second p-type silicon film 114 is formed on the side surface of the second silicon film 113. Second
A second oxide film 115 containing boron and a second nitride film 116 are formed on the side surface of the p-type silicon film 114. A polycrystalline silicon film 117 serving as a source or drain electrode is formed on the second silicon film 113, and a third nitride film 118 is formed on the polycrystalline silicon film 117.

In this structure, the first p-type silicon film 106 and the second p-type silicon film 114 as the source or drain region, the strained silicon film 109 as the channel region, and the gate insulating film 110 and the gate electrode 111 are formed, It constitutes a vertical electric field transistor. As a result of examining the operation measurement of this transistor, it was found that the gate leakage current was 7 × 10 ⁻⁴ Amps / cm ^{2 at a} gate voltage of 1.0 V, which was sufficiently small.

(Embodiment 2) Another embodiment of the present invention will be described below. In this embodiment, a transistor structure forming an inverter circuit will be described.

FIG. 4 is a cross-sectional schematic structural diagram of the produced inverter circuit. A substrate 101 made of single crystal silicon whose main surface has a crystal plane of (100) has a phosphorus concentration of 10 ¹⁵ to 10 ^16.
/ Cm ³ n-type well 102a and boron concentration 10 ¹⁵ -1
A p-type well 102b of 0 ¹⁶ / cm ³ is formed. n
On the upper surface of the mold well 102a, a wiring concentration of 10 ¹⁹ to
A p-type diffusion film 103a having a concentration of 10 ²⁰ / cm ³ is formed, and a concentration of 10 ¹⁹ to 10 10 to be wiring is formed on the upper surface of the p-type well 102b.
An n-type diffusion film 103b of ²⁰ / cm ³ is formed. The n-type well 102a and the p-type well 102b are electrically insulated from other regions by the isolation oxide film 104 formed by the trench isolation method. p-type diffusion film 10
A first silicon film 105a is formed on 3a, and a first silicon film 105b is formed on the n-type diffusion film 103b. The first p film is formed on the side surface of the first silicon film 105a.
The type silicon film 106a is formed, and the first silicon film 10 is formed.
A first n-type silicon film 106b is formed on the side surface of 5b. A first oxide film 107a containing boron is formed on the side surface of the first p-type silicon film 106a, and a first oxide film 107b containing phosphorus is formed on the side surface of the first n-type silicon film 106b.
Are formed. First oxide film 107a, first oxide film 1
A first nitride film 112 is laminated on 07b. A silicon germanium film is formed on the first silicon film 105a.
108a is laminated, and a silicon germanium film 108b is laminated on the first silicon film 105b. The strained silicon film 1 is formed on the side surface of the silicon germanium film 108a.
09a is formed, and a strained silicon film 109b is formed on the side surface of the silicon germanium film 108b. A gate insulating film 110 of a silicon oxide film having a thickness of 2.0 nm is formed on the side surface of the strained silicon film 109a and the strained silicon film 109b. On the side surface of the gate insulating film 110, the gate electrode 111a made of polycrystalline silicon and the gate electrode 1 are formed.
11b is formed. Silicon germanium film 10
The second silicon film 113a is laminated on the silicon 8a and the second silicon film 1a is formed on the silicon germanium film 108b.
13b are stacked. A second p-type silicon film 114a is formed on the side surface of the second silicon film 113a, and a second n-type silicon film 114 is formed on the side surface of the second silicon film 113b.
b is formed. A second oxide film 115a containing boron is formed on the side surface of the second p-type silicon film 114a, and a second oxide film 115b containing phosphorus is formed on the side surface of the second n-type silicon film 114b. Second silicon film 113
A polycrystalline silicon film 117a serving as a source or drain electrode is formed on the upper part of a, and the second silicon film 113b is formed.
A polycrystalline silicon film 117b serving as a source or drain electrode is formed on the upper part of the. Polycrystalline silicon film 11
The third nitride film 1 is formed on the 7a and the polycrystalline silicon film 117b.
18 is formed. A part of the third nitride film 118 is opened, and the copper first electrode 401a and the copper first electrode 40 are formed.
1b is connected. The copper second electrode 402a is connected to part of the p-type diffusion layer 103a, and the copper second electrode 402b is connected to part of the n-type diffusion layer 103b. The first electrode 401a, the first electrode 401b, the second electrode 402a, the second electrode 402b, the gate electrode 111a, and the gate electrode 111b are electrically insulated by the third oxide film 403.

In the structure shown in FIG. 4, the first p-type silicon film 106a serving as the source or drain region and the second p-type silicon film 106a are formed.
Type silicon film 114a, strained silicon film 109a to be a channel region, and gate insulating film 110 and gate electrode 1
A p-type field transistor 11 is constructed.
At the same time, the first as a source or drain region
n-type silicon film 106b and second n-type silicon film 114
b, a strained silicon film 109b serving as a channel region, and an n-type electric field transistor including a gate insulating film 110 and a gate electrode 111 are also formed. Since an n-type transistor and a p-type transistor can be formed, various logic circuits can be formed by connecting two transistors.

As an example, FIG. 5 is a plan view for explaining the wiring condition when an inverter circuit is constructed.

FIG. 37 is an equivalent circuit of the constructed semiconductor device. A potential of + 1.5V was applied to the second electrode 402a, and a potential of -1.5V was applied to the second electrode 402b. Also,
Third electrode 501a connected to gate electrode 111a
And a third electrode 501 connected to the gate electrode 111b
The input signal was given by connecting with b. Then, the first electrode 401a and the first electrode 401b were connected and an output signal was taken out. This inverter circuit worked normally.

FIG. 38 shows the evaluation result of the effective mobility of the n-type transistor. The broken line is the electric field dependence of the mobility which the silicon material originally has. The solid line shows the n-type transistor of the present invention in which silicon is strained. The mobility of electrons in the transistor of the present invention is higher than that of general silicon, which shows that high-speed circuit operation is possible.

Further, according to the graph of FIG. 38, the effective electron mobility of the present invention is 0.75 M (V / c) with respect to the effective mobility of silicon having a normal crystal lattice constant.
In the range of m) to 1.4 M (V / cm), an improvement in execution mobility of 1.35 times to 1.70 times is recognized.

(Embodiment 3) Another embodiment of the present invention will be described below. In this embodiment, a method of manufacturing a transistor that forms an inverter circuit will be described.

6 to 35 are schematic sectional structural views for explaining the manufacturing method of the manufactured inverter circuit. As shown in FIG. 6, an element isolation oxide film 104 was formed on a substrate 101 of single crystal silicon whose main surface has a crystal plane of (100) by dry etching to form a shallow groove and bury an oxide film.

Next, as shown in FIG. 7, after applying a resist 601 and patterning, an n-type well 102a having a phosphorus concentration of 10 ¹⁵ to 10 ¹⁶ / cm ³ is formed by an ion implantation method, and further, an ion implantation method is used. A p-type diffusion film 103a having a boron concentration of 10 ¹⁹ to 10 ²⁰ / cm ³ for wiring.
Was formed.

Next, as shown in FIG. 8, after the resist 601 is applied and patterned, the p-type well 102b having a boron concentration of 10 ¹⁵ to 10 ¹⁶ / cm ³ is formed by ion implantation.
And an n-type diffusion film 103b having a phosphorus concentration of 10 ¹⁹ to 10 ²⁰ / cm ³ to form wiring by ion implantation.
Was formed.

Next, as shown in FIG. 9, a 50 nm-thick first oxide film 104 for element isolation, a p-type diffusion film 103a and an n-type diffusion film 103b are formed by a chemical vapor deposition (CVD) method. The 1-oxide film 107 was formed.

Next, as shown in FIG. 10, a resist 601.
After coating and patterning, phosphorus is implanted into the first oxide film 107 by an ion implantation method so that the phosphorus concentration is 10 ²⁰ / cm 2.
^{A third} first oxide film 107b was formed.

Next, as shown in FIG. 11, a resist 601.
After coating and patterning, boron is implanted into the first oxide film 107 by an ion implantation method so that the boron concentration is 10 ²⁰
/ Cm ³ of the first oxide film 107a was formed.

Next, as shown in FIG. 12, a resist 601.
After peeling off the first nitride film 11 having a thickness of 10 nm
2 was deposited by the CVD method, and further a first sacrificial oxide film 1201 having a thickness of 20 nanometers was formed by the CVD method. Then, the second nitride film 116 having a thickness of 10 nm is formed by CVD.
Formed by the method.

Next, as shown in FIG. 13, the second nitride film 11 is formed.
A second oxide film 115 having a thickness of 50 nm is formed on
After forming by the VD method, a resist 601 was applied and patterned. Then, the second oxide film 1 is formed by the ion implantation method.
Phosphorus was implanted into 15 to form a second oxide film 115b having a phosphorus concentration of 10 ²⁰ / cm ³ .

Next, as shown in FIG. 14, a resist 601.
After coating and patterning, boron is ion-implanted to form a second oxide film with a boron concentration of 10 ²⁰ / cm ³ .
Formed 115a.

Next, as shown in FIG. 15, a resist 601.
After coating and patterning, a first opening 1501 was formed by dry etching.

Next, as shown in FIG. 16, the first opening 15
01 from the bottom to a first silicon film 105b and a silicon germanium film by a selective epitaxial growth method.
108b and the second silicon film 113b were formed.

Next, as shown in FIG. 17, the second silicon film 11 protruding from the surface of the second oxide film 115a or the second oxide film 115b is formed by the chemical mechanical polishing (CMP) method.
3b was removed and the second silicon film 113b was flattened.

Next, as shown in FIG. 18, a resist 601.
After coating and patterning, a second opening 1801 was formed by dry etching.

Next, as shown in FIG. 19, the second opening 18
01 from the bottom to a first silicon film 105a and a silicon germanium film by a selective epitaxial growth method.
108a and the 2nd silicon film 113a were formed.

Next, as shown in FIG. 20, the second silicon film 113a protruding from the surfaces of the second oxide film 115a and the second oxide film 115b is removed by CMP to planarize the second silicon film 113a. did.

Next, as shown in FIG. 21, a polycrystalline silicon film 117 having a thickness of 50 nm was formed by the CVD method, and a resist 601 was applied and patterned. Then, phosphorus was implanted into the polycrystalline silicon film 117 by the ion implantation method to form a polycrystalline silicon film 117b having a phosphorus concentration of 10 ²⁰ / cm ³ .

Next, as shown in FIG. 22, a resist 601.
Was applied and patterned. Then, boron is implanted into the polycrystalline silicon film 117 by the ion implantation method,
A polycrystalline silicon film 117a having a boron concentration of 10 ²⁰ / cm ³ was formed.

Next, as shown in FIG. 23, a resist 601.
And then the third nitride film 11 having a thickness of 40 nm is peeled off.
8 was deposited by the CVD method.

Next, as shown in FIG. 24, a resist 601.
After coating and patterning, using the resist 601 as a mask, the third nitride film 118, the polycrystalline silicon film 117a and the polycrystalline silicon film 117b, the second oxide film 115a and the second
The oxide film 115b was removed by a dry etching method.

Next, as shown in FIG. 25, a fourth nitride film 2501 having a thickness of 30 nm was formed by the CVD method. Since the fourth nitride film 2501 is formed on the second nitride film 116 and the third nitride film 118, they cannot be separated from each other. In the following description, the fourth nitride film 2501
The third nitride film 118 is regarded as a part of the second nitride film 116.

Next, as shown in FIG. 26, the polycrystalline silicon film 117a and the polycrystalline silicon film 117b, the second oxide film 115a and the second oxide film are anisotropically dry-etched.
The second nitride film 116 was left on the side surface of 115b.

Next, as shown in FIG. 27, the first sacrificial oxide film 1201 is formed by wet etching with hydrofluoric acid water.
Was removed.

Next, as shown in FIG. 28, the second sacrificial oxide film 2801 was formed by oxidizing the side surfaces of the silicon germanium film 108a and the silicon germanium film 108b by a thermal oxidation method.

Next, as shown in FIG. 29, the second sacrificial oxide film 2801 is formed by wet etching with hydrofluoric acid water.
Was removed to form an etch back region 2901.

Next, as shown in FIG. 30, the strained silicon film 109a and the strained silicon film 109 having a thickness of 15 nm are formed on the side surfaces of the silicon germanium film 108a and the silicon germanium film 108b by the selective epitaxial growth method.
b was formed.

Next, as shown in FIG. 31, the strained silicon film 1
An oxide film having a thickness of 2.0 nm was formed on the sidewalls of the 09a and the strained silicon film 109b by a thermal oxidation method, and then heat-treated in an ammonia atmosphere to form a gate insulating film 110.

Next, as shown in FIG. 32, the gate electrode 111 of a polycrystalline silicon film having a thickness of 50 nm is formed around the second nitride film 116 and the gate insulating film 1 by the thermal CVD method.
It was formed on the side surface of 10 and the upper surface of the first nitride film 112.

Next, as shown in FIG. 33, the gate electrode 111 was etched by the dry etching method to form the gate electrode 111a and the gate electrode 111b using the fourth nitride film 2501 as a mask.

Next, as shown in FIG. 34, the third oxide film 40
After forming 3 by the CVD method, the surface was flattened by the CMP method.

Next, as shown in FIG. 35, the first electrode 401
a and the first electrode 401b were connected to the polycrystalline silicon film 117a and the polycrystalline silicon film 117b, respectively. Similarly, the second electrode 402a and the second electrode 402b were connected to the p-type diffusion layer 103a and the n-type diffusion layer 103b, respectively.

As described above, the p-type transistor and the n-type transistor can be formed on the same substrate 101.

For convenience of description, the vertical and horizontal dimensions of the drawings used are appropriately reduced or enlarged for easy viewing. Also,
Boron or phosphorus was injected into the oxide film by the ion implantation method. For example, phosphine gas (PH
_An oxide film containing phosphorus or boron may be formed by mixing ₃ ) or diborane gas (B ₂ H ₆ ).

[0057]

According to the present invention, the first semiconductor film serving as the source region formed on the main surface of the semiconductor substrate, the second semiconductor film laminated on the first semiconductor film, and the second semiconductor film formed on the second semiconductor film. In the field-effect transistor having the stacked third semiconductor film which becomes the drain region, crystal defects are reduced by forming the fourth semiconductor film which becomes the channel region on the side surface of the second semiconductor film without the buffer film. A strained silicon film having a small surface roughness was obtained. Since the crystal defects and the surface roughness of the strained silicon film can be suppressed, the effect of reducing the gate leak current, which has been a problem so far, was obtained.

Further, in the present invention, the step of forming the first insulating film on the main surface of the semiconductor substrate, the step of forming the second insulating film on the first insulating film, and the step of forming the second insulating film on the second insulating film. A step of forming a third insulating film on the first insulating film, a step of forming a fourth insulating film on the third insulating film, a step of forming a fifth insulating film on the fourth insulating film, and In a method of manufacturing a semiconductor device, which includes a step of exposing a surface of a semiconductor substrate by opening a fifth insulating film, a step of forming a first semiconductor film to be a source region in the opening, and a step of forming a first semiconductor film on the first semiconductor film. The step of forming the second semiconductor film, the step of forming the third semiconductor film to be the drain region on the second semiconductor film, and the step of forming the fourth semiconductor film to be the channel region on the side surface of the second semiconductor film. A strained silicon film having few crystal defects and small surface roughness could be manufactured. Then, with this manufacturing method, the crystal defects and surface roughness of the strained silicon film can be suppressed, and the effect of reducing the gate leakage current can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional semiconductor device.

FIG. 3 is a diagram illustrating a germanium composition ratio in a buffer film of a conventional semiconductor device.

FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the invention.

FIG. 5 is a plan view of a semiconductor device according to a second embodiment of the invention.

FIG. 6 is a sectional view of the semiconductor device for explaining the manufacturing process of the semiconductor device according to the third embodiment of the invention.

FIG. 7 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 6 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 8 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 7 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 8 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 9 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 10 in the process of manufacturing the semiconductor device according to the third embodiment of the invention.

FIG. 12 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 11 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 13 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 12 in the process of manufacturing the semiconductor device according to the third embodiment of the invention.

FIG. 14 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 13 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 14 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 15 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 17 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 16 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 18 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 17 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 18 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 20 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 19 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 21 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 20 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

22 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 21 in the process of manufacturing the semiconductor device according to the third embodiment of the invention. FIG.

FIG. 23 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 22 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 24 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 23 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 25 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 24 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 26 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 25 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 27 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 26 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 28 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 27 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 29 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 28 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 30 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 29 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 31 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 30 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention.

32 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 31 in the manufacturing process of the semiconductor device according to Working Example 3 of the invention. FIG.

FIG. 33 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 32 in the manufacturing process of the semiconductor device according to Working Example 3 of the invention.

34 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 33 in the process of manufacturing the semiconductor device according to the third embodiment of the present invention. FIG.

FIG. 35 is a cross-sectional view of the semiconductor device for explaining a step that follows the step shown in FIG. 34 in the process for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 36 is a structural example of a semiconductor device according to an embodiment of the present invention.

FIG. 37 is an equivalent circuit of the semiconductor device according to the embodiment of the present invention.

FIG. 38 is an example of measurement data of the semiconductor device according to the embodiment of the invention.

[Explanation of symbols]

101 ... Substrate, 102 ... N-type well, 103 ... P-type diffusion film, 104 ... Isolation oxide film, 105 ... First silicon film,
106 ... First p-type silicon film, 107 ... First oxide film, 1
08 ... Silicon germanium film, 109 ... Strained silicon film, 110 ... Gate insulating film, 111 ... Gate electrode, 11
2 ... First nitride film, 113 ... Second silicon film, 114 ... Second p-type silicon film, 115 ... Second oxide film, 116 ... Second
Nitride film, 117 ... Polycrystalline silicon film, 118 ... Third nitride film, 401, 401a, 401b ... First electrode, 402,
402a, 402b ... Second electrode, 501, 501a, 50
1b ... third electrode, 1201 ... first sacrificial oxide film, 1501
... first opening, 1801 ... second opening, 2501 ... fourth
Nitride film, 2801 ... Second sacrificial oxide film, 2901 ... Etch back region, 3501 ... Drain, 3502 ... Gate insulating film (SiON), 3503, 3507 ... Insulator (PS
G: phosphorus-doped glass), 3504, 3506 ... Insulator (SiN), 3505 ... Gate, 3508 ... Source.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Satoshi Yamamoto             2 shares of 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F-term (reference) 5F048 AA07 AB04 AC03 BA05 BA14                       BB01 BB05 BC01 BC03 BD01                       BD07 BD09 BE03 BG14                 5F140 AA01 AA24 AB03 AC23 AC28                       BA01 BA05 BA16 BA17 BB04                       BC13 BE07 BE16 BF01 BF04                       BG08 BG14 BG28 BG38 BH02                       BH05 BJ01 BJ04 BJ27 BK13                       CB04 CC03 CC12 CE07 CE20

Claims (10)

[Claims] 1. A first semiconductor film formed on a main surface of a semiconductor substrate, a second semiconductor film laminated on the first semiconductor film, and a third semiconductor laminated on the second semiconductor film. And a fourth semiconductor film formed on a side surface of the second semiconductor film on which the second semiconductor film is not laminated, the fourth semiconductor film being formed of a substance having a crystal lattice constant different from a steady state crystal lattice constant. Semiconductor device. 2. A source region having a first semiconductor film formed on a main surface of a semiconductor substrate, and a second semiconductor laminated on the first semiconductor film and containing silicon and a substance having a lattice constant different from silicon. A film, a drain region having a third semiconductor film stacked on the second semiconductor film, and a fourth semiconductor film formed of strained silicon on a side surface of the second semiconductor film. A semiconductor device comprising: a gate electrode formed on the film via an insulating film. 3. The semiconductor device according to claim 1 or 2, wherein the crystal lattice constant of the second semiconductor film is larger than the crystal lattice constant of the fourth semiconductor film. 4. The method according to claim 1 or 2, wherein the second semiconductor film is a silicon germanium alloy.
A semiconductor device, wherein the semiconductor film is silicon. 5. A step of forming a first insulating film on the main surface of a semiconductor substrate, a step of forming a second insulating film on the first insulating film, and a third step on the second insulating film. A step of forming an insulating film, a step of forming a fourth insulating film on the third insulating film, a step of forming a fifth insulating film on the fourth insulating film, and A step of opening a fifth insulating film to expose the surface of the semiconductor substrate; a step of forming a first semiconductor film in the opening; and a step of forming a second semiconductor film on the first semiconductor film. A method of manufacturing a semiconductor device, comprising: forming a third semiconductor film on the second semiconductor film. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming a fourth semiconductor film on a side surface of the second semiconductor film. 7. The oxide film according to claim 5, wherein an oxide film is formed on a side surface of the second semiconductor film exposed by removing the second insulating film, and the oxide film is removed on the second semiconductor film. A method of manufacturing a semiconductor device, comprising the step of forming strained silicon. 8. The semiconductor device according to claim 5, further comprising a step of forming the first semiconductor film, the second semiconductor film, and the third semiconductor film by epitaxial growth. Manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 5, wherein the first semiconductor film contains silicon, and the second semiconductor film contains a silicon germanium alloy. 10. The method according to claim 7, further comprising the step of oxidizing the side surface of the second semiconductor film and then removing the oxide film on the side surface of the second semiconductor film with an etching solution containing hydrofluoric acid water. Of manufacturing a semiconductor device.