CN102436788B - Grid driving module and control method of scan line - Google Patents
Grid driving module and control method of scan line Download PDFInfo
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- CN102436788B CN102436788B CN201110412030.XA CN201110412030A CN102436788B CN 102436788 B CN102436788 B CN 102436788B CN 201110412030 A CN201110412030 A CN 201110412030A CN 102436788 B CN102436788 B CN 102436788B
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Abstract
The invention provides a grid driving module which is applied to generate a scan signal to a scan line in order to couple to a plurality of pixels on the scan line. The grid driving module comprises an output stage circuit and a comparison feedback unit. According to a frequency signal, the output stage circuit generates the scan signal to an input terminal of the scan line. According to a waveform of a scan signal on a scan line output terminal, the comparison feedback unit modulates the waveform of the scan signal, thus time from enablement to forbidden of the pixels is substantially same. Thereby, scintillation noise of a display panel can be reduced, and image quality of an LCD is raised.
Description
The present invention is dividing an application of application number is 200810201478.5, the applying date is on October 21st, 2008, denomination of invention is " control method of output-stage circuit, grid electrode drive module and sweep trace " Chinese invention patent application.
Technical field
The present invention relates to the control method of a kind of output-stage circuit, grid electrode drive module and sweep trace, the output-stage circuit that especially relates to a kind of sweep signal waveform that can modulation sweep trace with use the grid electrode drive module of this circuit and the control method of sweep trace.
Background technology
Along with the improvement of semiconductor technology, make that liquid crystal display (Liquid Crystal Display, LCD) has low power consumption, slim amount is light, resolution is high, color saturation is high, the life-span is long ... etc. advantage.Therefore, liquid crystal display is widely used in recent years, and replacement cathode-ray tube display (Cathode Ray Tube, CRT) becomes one of main flow of display of future generation.
Fig. 1 is the pixel structure figure of existing Thin Film Transistor-LCD.Please refer to Fig. 1, pixel structure 100 comprises thin film transistor (TFT) 101, liquid crystal capacitance C
lC, storage capacitors Cs, shared electrode CE, and stray capacitance C
gd.Wherein, in Fig. 1, the electric connection of pixel structure 100 is closed and can obviously be found out, storage capacitors Cs is the design of on shared electrode CE (Cs on Common).Fig. 2 is another pixel structure figure of existing Thin Film Transistor-LCD.Referring to Fig. 1 and Fig. 2, it is the design of on grid (Cs on Gate) that the maximum difference of pixel structure 200 and pixel structure 100 is in the storage capacitors Cs of pixel structure 200.
And no matter adopt above-mentioned any pixel structure, the scanning voltage (V exporting when gate drivers (gate driver does not illustrate)
g) by high levle voltage (HV
g) be promptly down to low level voltage (LV
g), and while causing thin film transistor (TFT) 101 to be closed, because of stray capacitance C
gdthe coupling effect causing (coupling effect), makes the voltage of drain electrode end of thin film transistor (TFT) 101 with a time voltage quasi position (the Δ V that also can decline
d), its value can be expressed as:
Wherein, the Δ V of formula (1)
gfor high levle scanning voltage HV
gdeduct low level scanning voltage LV
g, that is Δ V
g=HV
g-LV
g.The voltage quasi position of this change (Δ V
d) be called feed-trough voltage (feed-through voltage), and be not a constant.
Yet, because of the physical characteristics of liquid crystal molecule, therefore cause liquid crystal capacitance C
lCcan there is different capacitances along with different GTGs (gray level) cross-pressure.Hence one can see that, the pixel of each different GTG (pixel), its feed-trough voltage (Δ V
d) value also can be different.In addition, each sweep trace in display panel (not illustrating) has the existence of stray capacitance (parasitic capacitance) and dead resistance (parasitic resistance), therefore above-mentioned Δ V
gcan be subject to the impact of sweep trace stray capacitance and dead resistance, namely so-called RC postpones (RCdelay), and causes Δ V
gdisplay panel from scanning voltage input end the position away from more, its value can be less.In addition, in display panel, the RC of each sweep trace postpones to be not quite similar again, therefore feed-trough voltage (the Δ V of same a line (column) pixel in display panel
d) value also likely can be different.
By above-mentioned mentioned feed-trough voltage (the Δ V that causes
d) being worth two different factors, its which factor all can promote the flicker noise (flicker noise) of display panel, and the film flicker that causes TFT-LCD to present.In order to alleviate above-mentioned feed-trough voltage (Δ V
d) and the problem of flicker noise, the also corresponding correlation technique that develops solution, as follows:
1. according to feed-trough voltage (Δ V
d) value, and share voltage (common voltage, the V of the interior pixel of adjustment display panel
com).
2. use the Driving technique of the scanning voltage on 3 rank or 4 rank.
Above-mentioned technology 1 is applicable to above-mentioned disclosed pixel structure 100 and pixel structure 200, and it utilizes the measurement of optics by deviser, observes and adjust the share voltage V of pixel in display panel
com, so that the flicker noise of display panel central part is down to is minimum.Then, by above-mentioned share voltage V
comafter fixing, then the gamma (gamma) of finely tuning source electrode driver (source driver) outside revises voltage, to compensate because of different GTG cross-pressures, causes liquid crystal capacitance C
lCvalue changes and feed-trough voltage (Δ V
d) drift.And it is worth mentioning that, though that above-mentioned technology 1 has made the flicker noise of display panel central part be down to is minimum, the flicker noise of display panel both sides is not resolved completely.
Fig. 3 is the analog waveform figure of above-mentioned technology 1.Referring to Fig. 1～Fig. 3, the simulation waveform figure of Fig. 3 comprises scanning voltage V
gwaveform, data voltage V
swaveform (that is the source terminal s reception sources driver of thin film transistor (TFT) 101 provide data voltage), show voltage V
dwaveform (that is demonstration voltage of the drain electrode end d of thin film transistor (TFT) 101) and share voltage V
comwaveform.Wherein, by showing voltage V
dwaveform in can obviously find out stray capacitance C
gdthe coupling effect causing, and the feed-trough voltage Δ V producing
d.
As mentioned above, apply above-mentioned technology 1 and alleviate feed-trough voltage Δ V
dproblem time, must carry out complicated manual measurement, to find the best to provide to the share voltage V of pixel in display panel
com.In addition, the characteristic of every a slice display panel is not quite similar, therefore above-mentioned determined best share voltage V
comgamma correction voltage with fine setting source electrode driver outside, might not meet every a slice display panel completely.
In addition, in above-mentioned technology 2, be only applicable to above-mentioned pixel structure 200.Fig. 4 illustrates the analog waveform figure (adopting the Driving technique of 3 rank scanning voltages) for above-mentioned technology 2.Referring to Fig. 2 and Fig. 4, technology 2 is by last sweep trace G
m-1scanning voltage V
gfor low level, be also low level scanning voltage LV
g1 (m-1), and at sweep trace G
mscanning voltage V
gthere is feed-trough voltage Δ V
dafter, at sweep trace G
m-1low level scanning voltage LV
g1 (m-1)promote a voltage quasi position V
pto low level scanning voltage LV
g2 (m-1).In addition, see through storage capacitors C
svoltage coupling effect, add sweep trace G
mthis is in low level scanning voltage LV
g1 (m)a voltage quasi position V who promotes
pto low level scanning voltage LV
g2 (m), and see through stray capacitance C
gdvoltage coupling effect compensate feed-trough voltage Δ V simultaneously
ddrifting problem.
About the mentioned lifting one voltage quasi position V of above-mentioned technology 2
p, can calculate generation according to formula in theory, its formula is as follows:
Yet deviser wants to design above-mentioned technology 2 can produce following problem:
1. for example, when deviser wants to design the Driving technique of multistage (being 3 rank or 4 rank) scanning voltage of above-mentioned technology 2, well imagine, the design complexities of gate drivers will increase.
2. when gate drivers can accurately not produce above-mentioned boosted voltage level V
ptime, feed-trough voltage Δ V
dwill be compensated or overcompensation by deficiency the uncertainty that has so more increased design and measured.
3. above-mentioned technology 2 also must coordinate the gamma correction voltage of finely tuning source electrode driver outside, to compensate because of different GTG cross-pressures, causes liquid crystal capacitance C
lCthe change of value, the feed-trough voltage that causes (the Δ V of institute
d) drift.
4. in above-mentioned technology 2, not by sweep trace because the RC of stray capacitance and dead resistance postpones feed-trough voltage (the Δ V causing
d) drift includes consideration in.
Summary of the invention
The invention provides a kind of output-stage circuit and use the grid electrode drive module of this circuit and the control method of sweep trace, waveform by sweep signal in modulation sweep trace, reduce the flicker noise of whole picture, and then promote the quality of picture that liquid crystal display presents.
The present invention proposes a kind of output-stage circuit, and it has an output terminal, and this output-stage circuit comprises the first transistor, transistor seconds, the 3rd transistor and the 4th transistor.The the first source/drain electrode end of the first transistor couples the first voltage, and its second source/drain electrode end couples the output terminal of output-stage circuit, and its gate terminal receiving frequency signals.The the first source/drain electrode end of transistor seconds couples the output terminal of output-stage circuit, its gate terminal receiving frequency signals.The the first source/drain electrode end of the 3rd transistor couples the first voltage, its gate terminal receiving frequency signals, and the second source/drain electrode end is coupled to the second source/drain electrode end of transistor seconds.The the first source/drain electrode end of the 4th transistor couples the second source/drain electrode end of transistor seconds, and the 4th transistorized gate terminal and the second source/drain electrode end be received current control signal and couple second voltage respectively, and wherein second voltage is less than the first voltage.
A kind of grid electrode drive module of the another proposition of the present invention, is applicable to produce sweep signal to sweep trace, to enable to be coupled to several pixels on sweep trace.This grid electrode drive module comprises output-stage circuit and relatively feedbacks unit.Output-stage circuit couples the input end of this sweep trace, and according to frequency signal, produces sweep signal to sweep trace.Relatively feedback the output terminal that unit couples sweep trace, with the waveform at the output terminal of sweep trace according to sweep signal, and produce a current controling signal to output-stage circuit, with the waveform of modulation sweep signal, make each pixel identical haply from enabling forbidden energy institute elapsed time.
The present invention reintroduces a kind of control method of sweep trace, is applicable to the majority pixel that gated sweep is online coupled.This control method comprises: from the input end input scan signal of sweep trace, to enable respectively a plurality of pixels; Detecting sweep signal is at the waveform of the output terminal of sweep trace; According to sweep signal, at the waveform of the output terminal of sweep trace, carry out modulation sweep signal, make each pixel identical haply from enabling forbidden energy institute elapsed time.
The present invention, by grid electrode drive module, adjusts the waveform of sweep signal in sweep trace, makes sweep trace input end identical haply with the voltage waveform of output terminal, to reduce because of RC, postpones the flicker noise being produced.Again by scan enable unit to produce new enable signal, to avoid the problem that has Data duplication (overlapping) to write between adjacent scanning lines.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the pixel structure figure of existing Thin Film Transistor-LCD;
Fig. 2 is another pixel structure figure of existing Thin Film Transistor-LCD;
Fig. 3 is the analog waveform figure of above-mentioned technology 1;
Fig. 4 is the analog waveform figure (adopting the Driving technique of 3 rank scanning voltages) of above-mentioned technology 2;
Fig. 5 is the calcspar of the liquid crystal display of the embodiment of the present invention;
Fig. 6 is the circuit diagram according to embodiment of the present invention key diagram 5 liquid crystal display;
Fig. 7 A is the reference voltage oscillogram of the embodiment of the present invention;
Fig. 7 B is the oscillogram after the sweep trace voltage modulation of the embodiment of the present invention;
Fig. 8 A is the voltage oscillogram of the first electric capacity of the embodiment of the present invention;
Fig. 8 B is the voltage oscillogram of the 3rd electric capacity of the embodiment of the present invention;
Fig. 9 A is the voltage oscillogram of the second electric capacity of the embodiment of the present invention;
Fig. 9 B is the voltage oscillogram of the 4th electric capacity of the embodiment of the present invention;
Figure 10 is the sequential chart of the output-stage circuit of the embodiment of the present invention;
Figure 11 is the circuit diagram of the scan enable unit of the embodiment of the present invention;
Figure 12 is the process flow diagram of the sweep trace control method of the embodiment of the present invention.
Embodiment
Fig. 5 is the calcspar of the liquid crystal display of the embodiment of the present invention.Please refer to Fig. 5, liquid crystal display 500 provided by the invention comprises several grid electrode drive module 510_1～510_n and panel 520, and panel 520 still comprises multi-strip scanning line 530_1～530_n.Wherein, each grid electrode drive module produces respectively sweep signal to corresponding sweep trace, to enable to be coupled in the several pixels on sweep trace.
And for convenience of description, take in the present embodiment grid electrode drive module 510_1 and sweep trace 530_1 is example, as shown in Figure 6.Fig. 6 is the circuit diagram according to embodiment of the present invention key diagram 5 liquid crystal display.Please refer to Fig. 6, this circuit comprises grid electrode drive module 510_1 and sweep trace 530_1 (not illustrating the image element circuit that it couples).
Continue referring to Fig. 6, grid electrode drive module 510_1 comprises output-stage circuit 630 and relatively feedbacks unit 650.Output-stage circuit 630 comprises the first transistor M1, transistor seconds M2, the 3rd transistor M3 and the 4th transistor M4, and according to frequency signal V
tC1and produce sweep signal to sweep trace 530_1.In the present embodiment, the first transistor M1 and the 3rd transistor M3 are for example PMOS transistors, and transistor seconds M2 and the 4th transistor M4 can be nmos pass transistors.
In addition, the first source/drain electrode end of the first transistor M1 couples the first voltage V
dD, its second source/drain electrode end couples the input end of sweep trace 530_1, and its gate terminal receiving frequency signals V
tC1.The first source/drain electrode end of transistor seconds M2 couples the input end of sweep trace 530_1, its gate terminal receiving frequency signals V
tC1.The first source/drain electrode end of the 3rd transistor M3 couples the first voltage V
dD, its gate terminal receiving frequency signals V
tC1, and its second source/drain electrode end is coupled to the second source/drain electrode end of transistor seconds M2.The first source/drain electrode end of the 4th transistor M4 couples the second source/drain electrode end of transistor seconds M2, its gate terminal received current control signal, and its second source/drain electrode end couples second voltage V
eE.Wherein, second voltage V
eEmagnitude of voltage be less than the first voltage V
dDmagnitude of voltage.
In the present embodiment, relatively feedbacking unit 650 comprises the first comparer 651, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the single gain amplifier 652 of the first capacitor C 1, first, the 8th transistor M8, the second capacitor C 2 and high-gain amplifier 655.Wherein, the positive input terminal of the first comparer 651 receives reference signal V
ref, its negative input end receives the critical voltage V of pixel
th.And the first source/drain electrode end of the 5th transistor M5 couples the first current source I1, its gate terminal couples the output terminal of the first comparer 651.The first source/drain electrode end of the 6th transistor M6 couples tertiary voltage V3, and its second source/drain electrode end couples the first current source I1, and its gate terminal couples the output terminal of the first comparer 651.
In addition, the first source/drain electrode end of the 7th transistor M7 couples tertiary voltage V3, and its gate terminal couples the output terminal of the first comparer 651.The first capacitor C 1 is in order to by the second source/drain electrode end ground connection of the 5th transistor M5 and the 7th transistor M7.The positive input terminal of first single gain amplifier 652 couples the second source/drain electrode end of the 7th transistor M7, and negative input end and output terminal are coupled to each other, and usings as an impact damper (buffer).
And the first source/drain electrode end of the 8th transistor M8 and gate terminal couple respectively the output terminal of first single gain amplifier 652 and the first comparer 651.The second capacitor C 2 is in order to by the second source of the 8th transistor M8/drain electrode end ground connection.The negative input end of high-gain amplifier 655 couples the second source/drain electrode end of the 8th transistor M8.
Continue referring to Fig. 6, relatively feedback unit 650 and still comprise the second comparer 653, the 9th transistor M9, the tenth transistor M10, the 11 transistor M11, the single gain amplifier 654 of the 3rd capacitor C 3, second, the tenth two-transistor M12 and the 4th capacitor C 4.Wherein, the positive input terminal of the second comparer 653 is coupled to the output terminal of sweep trace 530_1, and its negative input end couples critical voltage V
th.The first source/drain electrode end of the 9th transistor M9 couples the second current source I2, and its gate terminal couples the output terminal of the second comparer 653.
In addition, the first source/drain electrode end of the tenth transistor M10 couples tertiary voltage V3, and its second source/drain electrode end couples the second current source I2, and its gate terminal coupling is received the output terminal of the second comparer 653.The first source/drain electrode end of the 11 transistor M11 couples tertiary voltage V3, and its gate terminal couples the output terminal of the second comparer 653.The 3rd capacitor C 3 is in order to by the second source/drain electrode end ground connection of the 9th transistor M9 and the 11 transistor M11.The positive input terminal of second single gain amplifier 654 couples the second source/drain electrode end of the 11 transistor M11, and negative input end and output terminal are coupled to each other, and usings as an impact damper.
And the first source/drain electrode end of the tenth two-transistor M12 and gate terminal are coupled to respectively the input end of the second comparer 653 and second single gain amplifier 654.One end ground connection of the 4th capacitor C 4, the other end is coupled to the second source/drain electrode end of the tenth two-transistor M12 and the positive input terminal of high-gain amplifier 655.In the present embodiment, the 5th transistor M5, the 8th transistor M8, the 9th transistor M9 and the tenth two-transistor M12 are for example nmos pass transistors, the 6th transistor M6, the 7th transistor M7, the tenth transistor M10 and the 11 transistor M11 can be PMOS transistors, and the first current source I1 is identical with the current value size of the second current source I2.
Then, set reference voltage V
refvoltage waveform as shown in Figure 7 A, be the square-wave waveform of the output terminal distortion of sweep trace 530_1.Wherein, time T 1 is reference voltage V
refcurrent potential be greater than critical voltage V
thtime, be also that pixel enables forbidden energy institute elapsed time.And the voltage waveform that the second comparer 653 positive input terminals receive is as shown in Figure 7 B, the waveform while being delivered to sweep trace 530_1 end for sweep signal after via grid electrode drive module 510_1 modulation.Wherein, time T 2 is greater than critical voltage V for the current potential of sweep signal
thtime, that is pixel enables the forbidden energy time.And the Output rusults of the first comparer 651 and the second comparer 653 will be controlled respectively conducting or the cut-off of the 5th transistor M5 and the 9th transistor M9.
In addition, when the first comparer 651 and the second comparer 653 are output as low level voltage, the 5th transistor M5, the 8th transistor M8, the 9th transistor M9 and the tenth two-transistor M12 be in closed condition, and the 6th transistor M6, the 7th transistor M7, the tenth transistor M10 and the 11 transistor M11 are all conducting state.Now the electric current on the 6th transistor M6 and the tenth transistor M10 is respectively the electric current that the first current source I1 and the second current source I2 provide.The 7th transistor M7 and the 11 transistor M11 charge to the first capacitor C 1 and the 3rd capacitor C 3 respectively the voltage quasi position of tertiary voltage V3.
Yet, when the first comparer 651 and the second comparer 653 are output as high levle voltage, the 5th transistor M5, the 8th transistor M8, the 9th transistor M9 and the tenth two-transistor M12 are all conducting state, and the 6th transistor M6, the 7th transistor M7, the tenth transistor M10 and the 11 transistor M11 are closed condition.Now the first capacitor C 1 and the 3rd capacitor C 3 will be charged with the first current source I1 and the second current source I2 respectively, and the voltage increasing is respectively I1*T1/C1 and I2*T2/C3, and rise with the form of linear-charging, as shown in Figure 8 A and 8 B.Due to the 8th transistor M8 and the tenth two-transistor M12 conducting, therefore the pressure drop in the first capacitor C 1 and the 3rd capacitor C 3, to via first and second single gain amplifiers 652,654, be sent to the second capacitor C 2 and the 4th capacitor C 4 respectively, its voltage waveform is respectively as shown in Fig. 9 A and 9B.
In addition, when low level voltage is got back to again in the output of the first and second comparers 651,653, the pressure drop on the first and the 3rd capacitor C 1, C3 will be got back to the voltage quasi position of tertiary voltage V3.Voltage on the second and the 4th capacitor C 2, C4 is maintained respectively V3+ (I1*T1/C1) and V3+ (I2*T2/C3), and inputs respectively negative input end and the positive input terminal of high-gain amplifier 655.Because the gain of high-gain amplifier 655 is very large, so the positive and negative input end of high-gain amplifier 655 has imaginary short effect, causes the voltage of positive and negative input end identical haply.By this, the time T 2 that in Fig. 7 B, pixel enables forbidden energy by with Fig. 7 A in pixel to enable the time T 1 of forbidden energy identical haply.
And high-gain amplifier 655 output currents control signal to the gate terminal of the 4th transistor M4 of output-stage circuit 630, to control the 4th transistor M4, become a constant current source, while making sweep trace 530_1 electric discharge, be a linear relationship.Therefore, during sweep trace 530_1 electric discharge, the slope of the waveform of each point electric discharge is all identical, so can suppress feed-trough voltage (Δ V
d) inconsistent situation generation, to reduce the flicker noise of whole picture.
Figure 10 is the sequential chart of the output-stage circuit of the embodiment of the present invention.Referring to Fig. 6 and Figure 10, in time T C, as frequency signal V
tC1during for low level voltage, the first transistor M1 and the 3rd transistor M3 conducting, makes the voltage on sweep trace 530_1 be charged to the first voltage V
dD.And transistor seconds M2 closes, the 4th transistor M4 conducting, an electric current is via the first voltage V
dDflow through the 3rd transistor M3, the 4th transistor M4 to second voltage V
eE, as frequency signal V
tC1while being converted to high levle voltage, the first transistor M1 and the 3rd transistor M3 close, and transistor seconds M2 and the 4th transistor M4 conducting, sweep trace 530_1 electric discharge via transistor seconds M2, the 4th transistor M4 to second voltage V
eE, wherein, the 4th transistor M4 is a constant current source.
In the present embodiment, for fear of adjacent two sweep traces, when the voltage linear of sweep trace 530_1 declines and it is closed, the voltage of sweep trace 530_2 just rises to the first voltage V
dD, and repeat the situation that (overlapping) writes.Therefore, grid electrode drive module 510_1～510_n also comprises scan enable unit 1100, as shown in figure 11, to produce new enable signal, avoids the problem that repeats to write.
Figure 11 is the circuit diagram of the scan enable unit of the embodiment of the present invention.Please refer to Figure 11, this scan enable unit 1100 comprise the 3rd comparer 1110, the 4th comparer 1120, phase inverter 1130 and with door 1140, in order to the waveform of the sweep signal of sweep trace 530_2 input end and sweep trace 5301 output terminals relatively, produce enable signal, with the time that determines that sweep signal is enabled.Wherein, the positive input terminal of the 3rd comparer 1110 is coupled to the output terminal of sweep trace 5301, and negative input end couples the critical voltage V of pixel
th.The positive input terminal of the 4th comparer 1120 is coupled to the input end of sweep trace 530_2, and negative input end couples critical voltage V
th.Phase inverter 1130 receives the output of the 4th comparer 1120.With the output of door 1140 reception the 3rd comparers 1110 and phase inverter 1130, to produce enable signal OE.
Continue referring to Figure 11, first, the voltage waveform VS1 that upper last pixel of sweep trace 530_1 is enabled to the time inputs to the positive input terminal of the 3rd comparer 1110, and at the critical voltage V with its negative input end reception
threlatively, to obtain very first time value signal X1.Again upper first pixel of sweep trace 530_2 is enabled to the positive input terminal that temporal voltage waveform VS2 inputs to the 4th comparer 1120, and at the critical voltage V with its negative input end reception
threlatively, to obtain the second time value signal X2.
In addition, voltage waveform VS1, VS2 are cut into four interval I, II, III, IV (as shown in figure 11), and the first and second time value signal X1, X2 are divided into four identical intervals too.Then, analyze the voltage waveform of VS1 and VS2, can find out that III district must insert enable signal OE, otherwise will have the situation that repeats to write.Therefore, by the second time value signal X2 via the signal obtaining after phase inverter 1130 and very first time value signal X1 input to simultaneously with door 1140 in carry out " with " computing after, can be created in the enable signal OE that III district occurs.And this enable signal OE can control the frequency signal of output-stage circuit, whether to determine the sweep signal of enable scans line.
In narration above, can arrange out preferably operation workflow of the present embodiment, it is described below.Figure 12 is the process flow diagram of the sweep trace control method of the embodiment of the present invention.Please refer to Figure 12, in step S1201, from the input end input scan signal of sweep trace, to enable respectively pixel.In step S1202, detecting sweep signal is at the waveform of the output terminal of sweep trace.In step S1203, according to sweep signal, at the waveform of the output terminal of sweep trace, carry out modulation sweep signal, make each pixel identical haply from enabling forbidden energy institute elapsed time.
In step S1204, the time that online last pixel of detecting scanning enables, and obtain very first time value signal.In step S1205, the time that online first pixel of detecting scanning enables, and obtain the second time value signal.In step S1206, by the second time value signal inversion.In step S1207, very first time value signal and anti-phase the second time value signal are carried out to the computing of logical “and”, to produce enable signal.In step S1208, whether according to enable signal, determine enable scans signal.
Then, the art has knows the knowledgeable conventionally, can pass through above-mentioned process flow diagram and corresponding circuit, can solve the flicker noise producing because RC postpones the inconsistent of the feed-trough voltage that causes in display and the problem that repeats to write, and then promote the quality of picture that liquid crystal display presents.
In sum, the present invention is by grid electrode drive module, and suitably adjusts the waveform of sweep signal in sweep trace, to reduce because RC postpones the problem of institute's inconsistent situation of the feed-trough voltage that caused and elimination flicker noise.By enable scans unit, produce new enable signal again, with the situation of avoiding repeating between sweep trace writing.Therefore, can effectively promote the quality of the whole picture of display.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when doing some, change and retouching, so protection scope of the present invention is worked as with being as the criterion that claim was defined.
Claims (11)
1. a grid electrode drive module, is suitable for producing one scan signal to one scan line, to enable to be coupled to several pixels on this sweep trace, it is characterized in that, described grid electrode drive module comprises:
One output-stage circuit, couples the input end of this sweep trace, and according to a frequency signal, produces one scan signal to the input end of described sweep trace; And
One relatively feedbacks unit, couple the output terminal of described sweep trace, with the waveform at described sweep trace output terminal according to described sweep signal, and produce a current controling signal to described output-stage circuit, with the waveform of sweep signal described in modulation, make each those pixel identical haply from enabling forbidden energy institute elapsed time;
The described unit of relatively feedbacking comprises:
One first comparer, its positive input terminal receives a reference signal, and its negative input end receives the critical voltage of those pixels;
One the 5th transistor, its source electrode couples one first current source with the utmost point in drain electrode, and its gate terminal receives the output terminal of described the first comparer;
One the 6th transistor, its source electrode couples a tertiary voltage with the utmost point in drain electrode, and its source electrode couples described the first current source with another utmost point in drain electrode, and its gate terminal couples the output terminal of described the first comparer;
One the 7th transistor, its source electrode couples described tertiary voltage with the utmost point in drain electrode, and its gate terminal receives the output terminal of described the first comparer;
One first electric capacity, in order to another utmost point ground connection by described the 5th transistor and described the 7th transistorized source electrode and in draining;
One first single gain amplifier, its positive input terminal couples the source electrode of described the 7th transistor and another utmost point in drain electrode, and its negative input end and output terminal are coupled to each other;
One the 8th transistor, the output terminal that the utmost point in its source electrode and drain electrode and gate terminal receive respectively described first single gain amplifier and described the first comparer;
One second electric capacity, in order to another utmost point ground connection by the source electrode of described the 8th transistor and in draining; And
One high-gain amplifier, another utmost point during its negative input end couples described the 8th transistorized source electrode and drains;
One second comparer, its positive input terminal is coupled to the output terminal of described sweep trace, and its negative input end couples described critical voltage;
One the 9th transistor, its source electrode couples one second current source with the utmost point in drain electrode, and its gate terminal receives the output terminal of described the second comparer;
The tenth transistor, its source electrode couples described tertiary voltage with the utmost point in drain electrode, and its source electrode couples described the second current source with another utmost point in drain electrode, and its gate terminal receives the output terminal of described the second comparer;
The 11 transistor, its source electrode couples described tertiary voltage with the utmost point in drain electrode, and its gate terminal receives the output terminal of described the second comparer;
One the 3rd electric capacity, in order to another utmost point ground connection by described the 9th transistor and described the 11 transistorized source electrode and in draining;
One second single gain amplifier, another utmost point during its positive input terminal couples described the 11 transistorized source electrode and drains, its negative input end and output terminal are coupled to each other;
The tenth two-transistor, the input end that the utmost point in its source electrode and drain electrode and gate terminal are coupled to respectively described the second comparer and described second single gain amplifier; And
One the 4th electric capacity, one end ground connection wherein, another utmost point in the source electrode that the other end is coupled to described the tenth two-transistor and drain electrode and the positive input terminal of described high-gain amplifier.
2. grid electrode drive module as claimed in claim 1, is characterized in that, described output-stage circuit comprises:
One the first transistor, its source electrode couples one first voltage with the utmost point in drain electrode, and another utmost point in its source electrode and drain electrode couples the input end of described sweep trace, and its gate terminal receives described frequency signal;
One transistor seconds, the utmost point in its source electrode and drain electrode couples the input end of described sweep trace, and its gate terminal receives described frequency signal;
One the 3rd transistor, its source electrode couples described the first voltage with the utmost point in drain electrode, and its gate terminal receives described frequency signal, and this source electrode is coupled to the source electrode of described transistor seconds and another utmost point in drain electrode with another utmost point in drain electrode; And
One the 4th transistor, its source electrode couples the source electrode of described transistor seconds and another utmost point in drain electrode with the utmost point in drain electrode, another utmost point in described the 4th transistorized gate terminal and source electrode and drain electrode receives respectively described current controling signal and couples a second voltage, and wherein said second voltage is less than described the first voltage.
3. grid electrode drive module as claimed in claim 2, is characterized in that, described the first transistor and described the 3rd transistor are PMOS transistor.
4. grid electrode drive module as claimed in claim 2, is characterized in that, described transistor seconds and described the 4th transistor are nmos pass transistor.
5. grid electrode drive module as claimed in claim 1, is characterized in that, described the 5th transistor, the 8th transistor, the 9th transistor and the tenth two-transistor are all nmos pass transistor.
6. grid electrode drive module as claimed in claim 1, is characterized in that, described the 6th transistor, the 7th transistor, the tenth transistor and the 11 transistor are all PMOS transistor.
7. grid electrode drive module as claimed in claim 1, it is characterized in that, also comprise that one scan enables unit, in order to the waveform of the sweep signal of more described sweep trace input end and output terminal and produce an enable signal, with the time that determines that described sweep signal is enabled.
8. grid electrode drive module as claimed in claim 7, is characterized in that, described scan enable unit comprises:
One the 3rd comparer, its positive input terminal is coupled to the output terminal of described sweep trace, and its negative input end couples the critical voltage of those pixels;
One the 4th comparer, its positive input terminal is coupled to the input end of this sweep trace, and its negative input end couples described critical voltage;
One phase inverter, couples the output terminal of described the 4th comparer; And
One with door, couple the output terminal of described the 3rd comparer and described phase inverter, to produce described enable signal.
9. a control method for sweep trace, it utilizes a kind of grid electrode drive module as claimed in claim 1, is suitable for controlling described sweep trace and is coupled to several pixels, it is characterized in that, and this control method comprises:
From the input end of this sweep trace, input described output-stage circuit and produce one scan signal according to a frequency signal, to enable respectively those pixels;
By described, relatively feedback the output terminal that unit couples described sweep trace, to detect this sweep signal at the waveform of described sweep trace output terminal; And
Waveform according to described sweep signal at described sweep trace output terminal, by the described unit of relatively feedbacking, produce a current controling signal to described output-stage circuit, with the waveform of sweep signal described in modulation, make each those pixel identical haply from enabling forbidden energy institute elapsed time.
10. the control method of sweep trace as claimed in claim 9, is characterized in that, also comprises:
Produce an enable signal; And
According to described enable signal, determine whether enable described sweep signal.
The control method of 11. sweep traces as claimed in claim 10, is characterized in that, the step that produces described enable signal comprises:
Detect the time that last pixel of described sweep trace enables, and obtain a very first time value signal;
Detect the time that first pixel of described sweep trace enables, and obtain one second time value signal;
By described the second time value signal inversion; And
Described very first time value signal and anti-phase the second time value signal are carried out to the computing of logical “and”, to produce described enable signal.
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| CN201110412030.XA CN102436788B (en) | 2008-10-21 | 2008-10-21 | Grid driving module and control method of scan line |
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| CN102436788B true CN102436788B (en) | 2014-02-05 |
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| CN1470929A (en) * | 2002-07-11 | 2004-01-28 | ������������ʽ���� | Photoelectric device and its driving device, driving method and electronic apparatus |
| CN1650226A (en) * | 2002-07-05 | 2005-08-03 | 三星电子株式会社 | Liquid crystal display and driving method thereof |
| TW200609879A (en) * | 2004-09-03 | 2006-03-16 | Himax Tech Inc | Output equipment and its driver |
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| US8674949B2 (en) * | 2007-02-20 | 2014-03-18 | Japan Displays Inc. | Liquid crystal display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1650226A (en) * | 2002-07-05 | 2005-08-03 | 三星电子株式会社 | Liquid crystal display and driving method thereof |
| CN1470929A (en) * | 2002-07-11 | 2004-01-28 | ������������ʽ���� | Photoelectric device and its driving device, driving method and electronic apparatus |
| TW200609879A (en) * | 2004-09-03 | 2006-03-16 | Himax Tech Inc | Output equipment and its driver |
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