CN102436788A - Grid driving module and control method of scan line - Google Patents
Grid driving module and control method of scan line Download PDFInfo
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- CN102436788A CN102436788A CN201110412030XA CN201110412030A CN102436788A CN 102436788 A CN102436788 A CN 102436788A CN 201110412030X A CN201110412030X A CN 201110412030XA CN 201110412030 A CN201110412030 A CN 201110412030A CN 102436788 A CN102436788 A CN 102436788A
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Abstract
The invention provides a grid driving module which is applied to generate a scan signal to a scan line in order to couple to a plurality of pixels on the scan line. The grid driving module comprises an output stage circuit and a comparison feedback unit. According to a frequency signal, the output stage circuit generates the scan signal to an input terminal of the scan line. According to a waveform of a scan signal on a scan line output terminal, the comparison feedback unit modulates the waveform of the scan signal, thus time from enablement to forbidden of the pixels is substantially same. Thereby, scintillation noise of a display panel can be reduced, and image quality of an LCD is raised.
Description
The present invention is that application number is 200810201478.5, the applying date is on October 21st, 2008, denomination of invention is divided an application for the Chinese invention patent application of " control method of output-stage circuit, grid electrode drive module and sweep trace ".
Technical field
The present invention relates to the control method of a kind of output-stage circuit, grid electrode drive module and sweep trace, but especially relate to a kind of output-stage circuit and the grid electrode drive module that uses this circuit and the control method of sweep trace of sweep signal waveform of modulation sweep trace.
Background technology
Along with the improvement of semiconductor technology, make LCD (Liquid Crystal Display, LCD) have low power consumption, slim amount is light, resolution is high, color saturation is high, the life-span is long ... etc. advantage.Therefore, LCD is widely used in recent years, and (Cathode Ray Tube CRT) becomes one of the main flow of display of future generation to replace cathode-ray tube display.
Fig. 1 is the pixel structure figure of existing Thin Film Transistor-LCD.Please with reference to Fig. 1, pixel structure 100 comprises thin film transistor (TFT) 101, liquid crystal capacitance C
LC, storage capacitors Cs, shared electrode CE, and stray capacitance C
GdWherein, can find out obviously that by the electric connection pass of pixel structure among Fig. 1 100 storage capacitors Cs is the design of on shared electrode CE (Cs on Common).Fig. 2 is another pixel structure figure of existing Thin Film Transistor-LCD.Please be simultaneously with reference to Fig. 1 and Fig. 2, it is the design of on grid (Cs on Gate) that pixel structure 200 and pixel structure 100 maximum different are in the storage capacitors Cs of pixel structure 200.
And no matter adopt above-mentioned any pixel structure, the scanning voltage (V that is exported when gate drivers (gate driver does not illustrate)
G) by high levle voltage (HV
G) promptly reduce to low level voltage (LV
G), and when causing thin film transistor (TFT) 101 to be closed, because of stray capacitance C
GdThe coupling effect that is caused (coupling effect) makes the voltage of drain electrode end of thin film transistor (TFT) 101 with a time voltage quasi position (the Δ V that also can descend
D), its value can be expressed as:
Wherein, the Δ V of formula (1)
GBe high levle scanning voltage HV
GDeduct low level scanning voltage LV
G, that is Δ V
G=HV
G-LV
GThe voltage quasi position of this change (Δ V
D) be called feed-trough voltage (feed-through voltage), and be not a constant.
Yet, because of the physical characteristics of liquid crystal molecule, so cause liquid crystal capacitance C
LCCan different capacitances be arranged along with different GTGs (gray level) cross-pressure.Hence one can see that, the pixel of each different GTG (pixel), its feed-trough voltage (Δ V
D) value also can be different.In addition, each the bar sweep trace in the display panel (not illustrating) has the existence of stray capacitance (parasitic capacitance) and dead resistance (parasitic resistance), so above-mentioned Δ V
GCan receive the influence of sweep trace stray capacitance and dead resistance, just so-called RC postpones (RCdelay), and causes Δ V
GFrom scanning voltage input end position far away more, its value can be more little at display panel.In addition, the RC of each bar sweep trace postpones to be not quite similar again in the display panel, so feed-trough voltage (the Δ V of same delegation (column) pixel in the display panel
D) value also might be different.
By above-mentioned mentioned feed-trough voltage (the Δ V that causes
D) being worth two different factors, its which factor all can promote the flicker noise (flicker noise) of display panel, and the film flicker that causes TFT-LCD to appear.In order to alleviate above-mentioned feed-trough voltage (Δ V
D) and the problem of flicker noise, the correlation technique that also corresponding development goes out to solve, as follows:
1. according to feed-trough voltage (Δ V
D) value, and share voltage (common voltage, the V of adjustment display panel interior pixel
Com).
2. use the actuation techniques of the scanning voltage on 3 rank or 4 rank.
Above-mentioned technology 1 is applicable to above-mentioned pixel structure that discloses 100 and pixel structure 200, and it utilizes the measurement of optics through the deviser, observes and the share voltage V of adjustment display panel interior pixel
Com, so that the flicker noise of display panel central part is reduced to is minimum.Then, with above-mentioned share voltage V
ComAfter fixing, finely tune the gamma (gamma) of source electrode driver (source driver) outside again and revise voltage, cause liquid crystal capacitance C because of different GTG cross-pressures with compensation
LCValue changes and feed-trough voltage (Δ V
D) drift.And what deserves to be mentioned is that though that above-mentioned technology 1 has made the flicker noise of display panel central part reduce to is minimum, the flicker noise of display panel both sides is not resolved fully.
Fig. 3 is above-mentioned technological 1 analog waveform figure.Please be simultaneously with reference to Fig. 1～Fig. 3, the simulation waveform figure of Fig. 3 comprises scanning voltage V
GWaveform, data voltage V
SWaveform (that is the source terminal s reception sources driver of thin film transistor (TFT) 101 provided data voltage), display voltage V
DWaveform (that is display voltage of the drain electrode end d of thin film transistor (TFT) 101) and share voltage V
ComWaveform.Wherein, by display voltage V
DWaveform in can obviously find out stray capacitance C
GdThe coupling effect that is caused, and the feed-trough voltage Δ V that produces
D
As stated, use above-mentioned technology 1 and alleviate feed-trough voltage Δ V
DProblem the time, must carry out complicated manual measurement, provide to the share voltage V of display panel interior pixel to find the best
ComIn addition, the characteristic of each sheet display panel is not quite similar, so the above-mentioned best share voltage V that determines
ComWith the outside gamma correction voltage of fine setting source electrode driver, might not meet each sheet display panel fully.
In addition, be only applicable to above-mentioned pixel structure 200 in above-mentioned technology 2.Fig. 4 illustrates the analog waveform figure (adopting the actuation techniques of 3 rank scanning voltages) for above-mentioned technological 2.Please be simultaneously with reference to Fig. 2 and Fig. 4, technology 2 is by at last sweep trace G
M-1Scanning voltage V
GBe low level, also be low level scanning voltage LV
G1 (m-1), and at sweep trace G
mScanning voltage V
GFeed-trough voltage Δ V takes place
DAfter, at sweep trace G
M-1Low level scanning voltage LV
G1 (m-1)Promote a voltage quasi position V
pTo low level scanning voltage LV
G2 (m-1)In addition, see through storage capacitors C
SThe voltage coupling effect, add sweep trace G
mThis is in low level scanning voltage LV
G1 (m)A voltage quasi position V who is promoted
pTo low level scanning voltage LV
G2 (m), and see through stray capacitance C
GdThe voltage coupling effect come to compensate simultaneously feed-trough voltage Δ V
DDrifting problem.
About the mentioned lifting one voltage quasi position V of above-mentioned technology 2
p, can calculate generation according to formula in theory, its formula is as follows:
Yet the deviser wants to design above-mentioned technological 2 can produce following problem:
1. when the deviser wanted to design the actuation techniques of multistage (for example being 3 rank or 4 rank) scanning voltage of above-mentioned technological 2, what well imagine was that the design complexities of gate drivers will increase.
2. work as gate drivers and can accurately not produce the accurate position of above-mentioned boosted voltage V
pThe time, feed-trough voltage Δ V then
DWill be by deficiency compensation or overcompensation, the uncertainty that has so more increased design and measured.
3. above-mentioned technology 2 also must cooperate the outside gamma correction voltage of fine setting source electrode driver, causes liquid crystal capacitance C with compensation because of different GTG cross-pressures
LCThe change of value, the feed-trough voltage that causes (the Δ V of institute
D) drift.
4. in the above-mentioned technology 2, not with sweep trace because feed-trough voltage (the Δ V that the RC of stray capacitance and dead resistance delay causes
D) drift includes consideration in.
Summary of the invention
The present invention provides a kind of output-stage circuit and the grid electrode drive module that uses this circuit and the control method of sweep trace; Waveform by sweep signal in the modulation sweep trace; Reduce the flicker noise of whole picture, and then promote the quality of picture that LCD appears.
The present invention proposes a kind of output-stage circuit, and it has an output terminal, and this output-stage circuit comprises the first transistor, transistor seconds, the 3rd transistor and the 4th transistor.First source of the first transistor/drain electrode end couples first voltage, and its second source/drain electrode end couples the output terminal of output-stage circuit, and its gate terminal receiving frequency signals.First source of transistor seconds/drain electrode end couples the output terminal of output-stage circuit, its gate terminal receiving frequency signals.First source of the 3rd transistor/drain electrode end couples first voltage, its gate terminal receiving frequency signals, and second source/drain electrode end is coupled to the second source/drain electrode end of transistor seconds.First source of the 4th transistor/drain electrode end couples the second source/drain electrode end of transistor seconds, the 4th transistorized gate terminal and second source/drain electrode end then respectively the received current control signal with couple second voltage, wherein second voltage is less than first voltage.
The present invention proposes a kind of grid electrode drive module in addition, is applicable to produce sweep signal to sweep trace, to enable to be coupled to several pixels on the sweep trace.This grid electrode drive module comprises output-stage circuit and relatively feedbacks the unit.Output-stage circuit couples the input end of this sweep trace, and produces sweep signal to sweep trace according to frequency signal.Relatively feedback the output terminal that the unit couples sweep trace; With according to the waveform of sweep signal at the output terminal of sweep trace; And produce a current controling signal to output-stage circuit, with the waveform of modulation sweep signal, make each pixel identical haply from enabling forbidden energy institute elapsed time.
The present invention reintroduces a kind of control method of sweep trace, is applicable to online most the pixels that couple of gated sweep.This control method comprises: from the input end input scan signal of sweep trace, to enable a plurality of pixels respectively; The detecting sweep signal is at the waveform of the output terminal of sweep trace; Come the modulation sweep signal according to sweep signal at the waveform of the output terminal of sweep trace, make each pixel identical haply from enabling forbidden energy institute elapsed time.
The present invention adjusts the waveform of sweep signal in the sweep trace by grid electrode drive module, makes the sweep trace input end identical haply with the voltage waveform of output terminal, to reduce the flicker noise that is produced because of the RC delay.Again by the scan enable unit producing new enable signal, to avoid having data to repeat the problem that (overlapping) writes between the adjacent scanning lines.
For let above and other objects of the present invention, feature and advantage can be more obviously understandable, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows.
Description of drawings
Fig. 1 is the pixel structure figure of existing Thin Film Transistor-LCD;
Fig. 2 is another pixel structure figure of existing Thin Film Transistor-LCD;
Fig. 3 is above-mentioned technological 1 analog waveform figure;
Fig. 4 is above-mentioned technological 2 analog waveform figure (adopting the actuation techniques of 3 rank scanning voltages);
Fig. 5 is the calcspar of the LCD of the embodiment of the invention;
Fig. 6 is the circuit diagram according to embodiment of the invention key diagram 5 LCDs;
Fig. 7 A is the reference voltage oscillogram of the embodiment of the invention;
Fig. 7 B is the oscillogram behind the sweep trace voltage modulation of the embodiment of the invention;
Fig. 8 A is the voltage oscillogram of first electric capacity of the embodiment of the invention;
Fig. 8 B is the voltage oscillogram of the 3rd electric capacity of the embodiment of the invention;
Fig. 9 A is the voltage oscillogram of second electric capacity of the embodiment of the invention;
Fig. 9 B is the voltage oscillogram of the 4th electric capacity of the embodiment of the invention;
Figure 10 is the sequential chart of the output-stage circuit of the embodiment of the invention;
Figure 11 is the circuit diagram of the scan enable unit of the embodiment of the invention;
Figure 12 is the process flow diagram of the sweep trace control method of the embodiment of the invention.
Embodiment
Fig. 5 is the calcspar of the LCD of the embodiment of the invention.Please with reference to Fig. 5, LCD 500 provided by the invention comprises several grid electrode drive modules 510_1～510_n and panel 520, and panel 520 still comprises multi-strip scanning line 530_1～530_n.Wherein, each grid electrode drive module produces sweep signal respectively to corresponding scanning line, to enable to be coupled in several pixels on the sweep trace.
And explanation for ease is an example with grid electrode drive module 510_1 and sweep trace 530_1 in the present embodiment, and is as shown in Figure 6.Fig. 6 is the circuit diagram according to embodiment of the invention key diagram 5 LCDs.Please with reference to Fig. 6, this circuit comprises grid electrode drive module 510_1 and sweep trace 530_1 (not illustrating the image element circuit that it couples).
Please continue with reference to Fig. 6, grid electrode drive module 510_1 comprises output-stage circuit 630 and relatively feedbacks unit 650.Output-stage circuit 630 comprises the first transistor M1, transistor seconds M2, the 3rd transistor M3 and the 4th transistor M4, and according to frequency signal V
TC1And produce sweep signal to sweep trace 530_1.In the present embodiment, the first transistor M1 and the 3rd transistor M3 for example are the PMOS transistors, and transistor seconds M2 and the 4th transistor M4 then can be nmos pass transistors.
In addition, first source of the first transistor M1/drain electrode end couples the first voltage V
DD, its second source/drain electrode end couples the input end of sweep trace 530_1, and its gate terminal receiving frequency signals V
TC1First source of transistor seconds M2/drain electrode end couples the input end of sweep trace 530_1, its gate terminal receiving frequency signals V
TC1First source of the 3rd transistor M3/drain electrode end couples the first voltage V
DD, its gate terminal receiving frequency signals V
TC1, and its second source/drain electrode end is coupled to second source/drain electrode end of transistor seconds M2.First source of the 4th transistor M4/drain electrode end couples second source/drain electrode end of transistor seconds M2, its gate terminal received current control signal, and its second source/drain electrode end couples the second voltage V
EEWherein, the second voltage V
EEMagnitude of voltage less than the first voltage V
DDMagnitude of voltage.
In the present embodiment, relatively feedbacking unit 650 comprises the single gain amplifier of first comparer 651, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, first capacitor C 1, first 652, the 8th transistor M8, second capacitor C 2 and high-gain amplifier 655.Wherein, the positive input terminal of first comparer 651 receives reference signal V
Ref, its negative input end then receives the critical voltage V of pixel
ThAnd first source of the 5th transistor M5/drain electrode end couples the first current source I1, and its gate terminal couples the output terminal of first comparer 651.First source of the 6th transistor M6/drain electrode end couples tertiary voltage V3, and its second source/drain electrode end couples the first current source I1, and its gate terminal then couples the output terminal of first comparer 651.
In addition, first source of the 7th transistor M7/drain electrode end couples tertiary voltage V3, and its gate terminal couples the output terminal of first comparer 651.First capacitor C 1 is in order to the second source/drain electrode end ground connection with the 5th transistor M5 and the 7th transistor M7.The positive input terminal of first single gain amplifier 652 couples second source/drain electrode end of the 7th transistor M7, and negative input end and output terminal are coupled to each other, with as an impact damper (buffer).
And first source of the 8th transistor M8/drain electrode end and gate terminal couple the output terminal of the first single gain amplifier 652 and first comparer 651 respectively.Second capacitor C 2 is in order to the second source/drain electrode end ground connection with the 8th transistor M8.The negative input end of high-gain amplifier 655 couples second source/drain electrode end of the 8th transistor M8.
Please continue with reference to Fig. 6, relatively feedback unit 650 and still comprise the single gain amplifier of second comparer 653, the 9th transistor M9, the tenth transistor M10, the 11 transistor M11, the 3rd capacitor C 3, second 654, the tenth two-transistor M12 and the 4th capacitor C 4.Wherein, the positive input terminal of second comparer 653 is coupled to the output terminal of sweep trace 530_1, and its negative input end then couples critical voltage V
ThFirst source of the 9th transistor M9/drain electrode end couples the second current source I2, and its gate terminal couples the output terminal of second comparer 653.
In addition, first source of the tenth transistor M10/drain electrode end couples tertiary voltage V3, and its second source/drain electrode end couples the second current source I2, and its gate terminal coupling is received the output terminal of second comparer 653.First source of the 11 transistor M11/drain electrode end couples tertiary voltage V3, and its gate terminal couples the output terminal of second comparer 653.The 3rd capacitor C 3 is in order to the second source/drain electrode end ground connection with the 9th transistor M9 and the 11 transistor M11.The positive input terminal of second single gain amplifier 654 couples second source/drain electrode end of the 11 transistor M11, and negative input end and output terminal then are coupled to each other, with as an impact damper.
And first source of the tenth two-transistor M12/drain electrode end and gate terminal are coupled to the input end of second comparer 653 and second single gain amplifier 654 respectively.One end ground connection of the 4th capacitor C 4, the other end are coupled to the second source/drain electrode end of the tenth two-transistor M12 and the positive input terminal of high-gain amplifier 655.In the present embodiment; The 5th transistor M5, the 8th transistor M8, the 9th transistor M9 and the tenth two-transistor M12 for example are nmos pass transistors; The 6th transistor M6, the 7th transistor M7, the tenth transistor M10 and the 11 transistor M11 then can be the PMOS transistors, and the first current source I1 is identical with the current value size of the second current source I2.
Then, set reference voltage V
RefVoltage waveform shown in Fig. 7 A, be the square-wave waveform of the output terminal distortion of sweep trace 530_1.Wherein, time T 1 is reference voltage V
RefCurrent potential greater than critical voltage V
ThTime, also be that pixel enables forbidden energy institute elapsed time.And the voltage waveform that second comparer, 653 positive input terminals receive is shown in Fig. 7 B, for sweep signal is delivered to the waveform of sweep trace 530_1 when terminal after via grid electrode drive module 510_1 modulation.Wherein, time T 2 is that the current potential of sweep signal is greater than critical voltage V
ThTime, that is pixel enables the forbidden energy time.And the output result of first comparer 651 and second comparer 653 will control the conducting of the 5th transistor M5 and the 9th transistor M9 respectively or end.
In addition; When first comparer 651 and second comparer 653 are output as low level voltage; Then the 5th transistor M5, the 8th transistor M8, the 9th transistor M9 and the tenth two-transistor M12 are in closed condition, and the 6th transistor M6, the 7th transistor M7, the tenth transistor M10 and the 11 transistor M11 are all conducting state.Electric current on this moment the 6th transistor M6 and the tenth transistor M10 is respectively the electric current that the first current source I1 and the second current source I2 are provided.The 7th transistor M7 and the 11 transistor M11 then charge to first capacitor C 1 and the 3rd capacitor C 3 voltage quasi position of tertiary voltage V3 respectively.
Yet; When first comparer 651 and second comparer 653 are output as high levle voltage; Then the 5th transistor M5, the 8th transistor M8, the 9th transistor M9 and the tenth two-transistor M12 are all conducting state, and the 6th transistor M6, the 7th transistor M7, the tenth transistor M10 and the 11 transistor M11 are closed condition.First capacitor C 1 and the 3rd capacitor C 3 will be charged with the first current source I1 and the second current source I2 respectively this moment, and the voltage that increases is respectively I1*T1/C1 and I2*T2/C3, and rise with the form of linear-charging, then shown in Fig. 8 A and Fig. 8 B.Because the 8th transistor M8 and the tenth two-transistor M12 conducting; Therefore the pressure drop on first capacitor C 1 and the 3rd capacitor C 3; To be sent to second capacitor C 2 and the 4th capacitor C 4 via first and second single gain amplifiers 652,654 respectively, its voltage waveform is respectively shown in Fig. 9 A and 9B.
In addition, when low level voltage is got back in the output of first and second comparers 651,653 again, then the first and the 3rd capacitor C 1, the last pressure drop of C3 will be got back to the voltage quasi position of tertiary voltage V3.The second and the 4th capacitor C 2, the last voltage of C4 then are maintained V3+ (I1*T1/C1) and V3+ (I2*T2/C3) respectively, and import the negative input end and the positive input terminal of high-gain amplifier 655 respectively.Because the gain of high-gain amplifier 655 is very big, so the positive and negative input end of high-gain amplifier 655 has the imaginary short effect, causes the voltage of positive and negative input end identical haply.By this, among Fig. 7 B pixel enable forbidden energy time T 2 will to enable the time T 1 of forbidden energy identical haply with pixel among Fig. 7 A.
And high-gain amplifier 655 output currents control signal to the gate terminal of the 4th transistor M4 of output-stage circuit 630, become a constant current source to control the 4th transistor M4, are a linear relationship when making sweep trace 530_1 discharge.Therefore, the slope of the waveform of each point discharge is all identical during sweep trace 530_1 discharge, so can suppress feed-trough voltage (Δ V
D) inconsistent situation generation, to reduce the flicker noise of whole picture.
Figure 10 is the sequential chart of the output-stage circuit of the embodiment of the invention.Please be simultaneously with reference to Fig. 6 and Figure 10, in time T C, as frequency signal V
TC1During for low level voltage, then the first transistor M1 and the 3rd transistor M3 conducting makes that the voltage on the sweep trace 530_1 is recharged to the first voltage V
DDAnd transistor seconds M2 closes, the 4th transistor M4 conducting, and then an electric current is via the first voltage V
DDFlow through the 3rd transistor M3, the 4th transistor M4 to the second voltage V
EE, as frequency signal V
TC1When converting high levle voltage into, then the first transistor M1 and the 3rd transistor M3 close, and transistor seconds M2 and the 4th transistor M4 conducting, sweep trace 530_1 discharges then via transistor seconds M2, the 4th transistor M4 to the second voltage V
EE, wherein, the 4th transistor M4 is a constant current source.
In the present embodiment, for fear of adjacent two sweep traces, when the voltage linear of sweep trace 530_1 descended and it is closed, the voltage of sweep trace 530_2 just rose to the first voltage V
DD, and the situation that repetition (overlapping) writes takes place.Therefore, grid electrode drive module 510_1～510_n also comprises scan enable unit 1100, and is shown in figure 11, avoids the problem that repeats to write to produce new enable signal.
Figure 11 is the circuit diagram of the scan enable unit of the embodiment of the invention.Please with reference to Figure 11; This scan enable unit 1100 comprise the 3rd comparer 1110, the 4th comparer 1120, phase inverter 1130 and with door 1140; Produce enable signal in order to the waveform of the sweep signal of sweep trace 530_2 input end and sweep trace 5301 output terminals relatively, with the time that determines that sweep signal is enabled.Wherein, the positive input terminal of the 3rd comparer 1110 is coupled to the output terminal of sweep trace 5301, and negative input end couples the critical voltage V of pixel
ThThe positive input terminal of the 4th comparer 1120 is coupled to the input end of sweep trace 530_2, and negative input end couples critical voltage V
ThPhase inverter 1130 receives the output of the 4th comparer 1120.With the output of door 1140 receptions the 3rd comparer 1110 and phase inverter 1130, to produce enable signal OE.
Please continue with reference to Figure 11, at first, sweep trace 530_1 gone up the positive input terminal that voltage waveform VS1 that last pixel enables the time inputs to the 3rd comparer 1110, and at the critical voltage V that receives with its negative input end
ThRelatively, to obtain very first time value signal X1.Again sweep trace 530_2 is gone up first pixel and enable the positive input terminal that temporal voltage waveform VS2 inputs to the 4th comparer 1120, and at the critical voltage V that receives with its negative input end
ThRelatively, to obtain the second time value signal X2.
In addition, voltage waveform VS1, VS2 are cut into four interval I, II, III, IV (shown in figure 11), and the first and second time value signal X1, X2 are divided into four identical intervals too.Then, analyze the voltage waveform of VS1 and VS2, can find out in the III district and must insert enable signal OE, otherwise will have the situation that repeats to write.Therefore, with the second time value signal X2 via the signal that obtains after the phase inverter 1130 and very first time value signal X1 input to simultaneously with 1140 in carry out " with " computing after, can be created in the enable signal OE that the III district is occurred.And this enable signal OE is the frequency signal of may command output-stage circuit, whether to determine the sweep signal of enable scans line.
In top narration, can put out the preferable operation workflow of present embodiment in order, it is described below.Figure 12 is the process flow diagram of the sweep trace control method of the embodiment of the invention.Please with reference to Figure 12, in step S1201, from the input end input scan signal of sweep trace, to enable pixel respectively.In step S1202, the detecting sweep signal is at the waveform of the output terminal of sweep trace.In step S1203, come the modulation sweep signal according to sweep signal at the waveform of the output terminal of sweep trace, make each pixel identical haply from enabling forbidden energy institute elapsed time.
In step S1204, the time that online last pixel of detecting scanning enables, and obtain very first time value signal.In step S1205, the time that online first pixel of detecting scanning enables, and obtain the second time value signal.In step S1206, with the second time value signal inversion.In step S1207, the second time value signal of very first time value signal and anti-phase is carried out the computing of logical, to produce enable signal.In step S1208, whether determine the enable scans signal according to enable signal.
Then; The present technique field has common knowledge the knowledgeable; Can solve flicker noise that produces because RC postpones the inconsistent of the feed-trough voltage that causes in the display and the problem that repeats to write through above-mentioned process flow diagram and corresponding electrical circuits, and then promote the quality of picture that LCD appears.
In sum, the present invention is through grid electrode drive module, and suitably adjusts the waveform of sweep signal in the sweep trace, to reduce because RC postpones the problem of institute's inconsistent situation of the feed-trough voltage that caused and elimination flicker noise.Produce new enable signal by the enable scans unit again, with the situation of avoiding repeating between the sweep trace writing.Therefore, can promote the quality of the whole picture of display effectively.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limiting the present invention, anyly has the knack of this art, do not breaking away from the spirit and scope of the present invention; Change and retouching when doing some, so protection scope of the present invention is when being as the criterion with what claim defined.
Claims (13)
1. a grid electrode drive module is suitable for producing one scan signal to one scan line,, it is characterized in that said grid electrode drive module comprises to enable to be coupled to several pixels on this sweep trace:
One output-stage circuit couples the input end of this sweep trace, and produces the input end of one scan signal to said sweep trace according to a frequency signal; And
One relatively feedbacks the unit; Couple the output terminal of said sweep trace; With the waveform of the said sweep signal of foundation at said sweep trace output terminal; And produce a current controling signal to said output-stage circuit, with the waveform of the said sweep signal of modulation, make each those pixel identical haply from enabling forbidden energy institute elapsed time.
2. grid electrode drive module as claimed in claim 1 is characterized in that, said output-stage circuit comprises:
One the first transistor, its first source/drain electrode end couple one first voltage, and its second source/drain electrode end couples the input end of said sweep trace, and its gate terminal receives said frequency signal;
One transistor seconds, its first source/drain electrode end couples the input end of said sweep trace, and its gate terminal receives said frequency signal;
One the 3rd transistor, its first source/drain electrode end couple said first voltage, and its gate terminal receives said frequency signal, and this second source/drain electrode end is coupled to the second source/drain electrode end of said transistor seconds; And
One the 4th transistor; Its first source/drain electrode end couples the second source/drain electrode end of said transistor seconds; The said the 4th transistorized gate terminal and second source/drain electrode end then receive said current controling signal respectively and couple one second voltage, and wherein said second voltage is less than said first voltage.
3. grid electrode drive module as claimed in claim 2 is characterized in that, said the first transistor and said the 3rd transistor are the PMOS transistor.
4. grid electrode drive module as claimed in claim 2 is characterized in that, said transistor seconds and said the 4th transistor are nmos pass transistor.
5. grid electrode drive module as claimed in claim 1 is characterized in that, the said unit of relatively feedbacking comprises:
One first comparer, its positive input terminal receives a reference signal, and its negative input end then receives the critical voltage of those pixels;
One the 5th transistor, its first source/drain electrode end couple one first current source, and its gate terminal receives the output terminal of said first comparer;
One the 6th transistor, its first source/drain electrode end couples a tertiary voltage, and its second source/drain electrode end couples said first current source, and its gate terminal then couples the output terminal of said first comparer;
One the 7th transistor, its first source/drain electrode end couples said tertiary voltage, and its gate terminal receives the output terminal of said first comparer;
One first electric capacity is in order to said the 5th transistor and the said the 7th transistorized second source/drain electrode end ground connection;
One first single gain amplifier, its positive input terminal couple the second source/drain electrode end of said the 7th transistor, and its negative input end and output terminal are coupled to each other;
One the 8th transistor, its first source/drain electrode end and gate terminal receive the output terminal of said first single gain amplifier and said first comparer respectively;
One second electric capacity is in order to the second source/drain electrode end ground connection with said the 8th transistor; And
One high-gain amplifier, its negative input end couple the said the 8th transistorized second source/drain electrode end.
6. grid electrode drive module as claimed in claim 5 is characterized in that, the said unit of relatively feedbacking also comprises:
One second comparer, its positive input terminal is coupled to the output terminal of said sweep trace, and its negative input end then couples said critical voltage;
One the 9th transistor, its first source/drain electrode end couple one second current source, and its gate terminal receives the output terminal of said second comparer;
The tenth transistor, its first source/drain electrode end couples said tertiary voltage, and its second source/drain electrode end couples said second current source, and its gate terminal receives the output terminal of said second comparer;
The 11 transistor, its first source/drain electrode end couples said tertiary voltage, and its gate terminal receives the output terminal of said second comparer;
One the 3rd electric capacity is in order to said the 9th transistor and the said the 11 transistorized second source/drain electrode end ground connection;
One second single gain amplifier, its positive input terminal couples the said the 11 transistorized second source/drain electrode end, and its negative input end and output terminal then are coupled to each other;
The tenth two-transistor, its first source/drain electrode end and gate terminal are coupled to the input end of said second comparer and said second single gain amplifier respectively; And
One the 4th electric capacity, an end ground connection wherein, the other end is coupled to the second source/drain electrode end of said the tenth two-transistor and the positive input terminal of said high-gain amplifier.
7. grid electrode drive module as claimed in claim 6 is characterized in that, said the 5th transistor, the 8th transistor, the 9th transistor and the tenth two-transistor all are nmos pass transistor.
8. grid electrode drive module as claimed in claim 6 is characterized in that, said the 6th transistor, the 7th transistor, the tenth transistor and the 11 transistor all are the PMOS transistor.
9. grid electrode drive module as claimed in claim 1; It is characterized in that; Comprise that also one scan enables the unit, in order to the waveform of the sweep signal of more said sweep trace input end and output terminal and produce an enable signal, with the time that determines that said sweep signal is enabled.
10. grid electrode drive module as claimed in claim 9 is characterized in that, said scan enable unit comprises:
One the 3rd comparer, its positive input terminal is coupled to the output terminal of said sweep trace, and its negative input end couples the critical voltage of those pixels;
One the 4th comparer, its positive input terminal is coupled to the input end of this sweep trace, and its negative input end couples said critical voltage;
One phase inverter couples the output terminal of said the 4th comparer; And
One with door, couple the output terminal of said the 3rd comparer and said phase inverter, to produce said enable signal.
11. the control method of a sweep trace is suitable for controlling said sweep trace and is coupled to several pixels, it is characterized in that this control method comprises:
From the input end input one scan signal of this sweep trace, to enable those pixels respectively;
Detect the waveform of this sweep signal at said sweep trace output terminal; And
Come the said sweep signal of modulation according to this sweep signal at the waveform of said sweep trace output terminal, make each those pixel identical haply from enabling forbidden energy institute elapsed time.
12. the control method of sweep trace as claimed in claim 11 is characterized in that, also comprises:
Produce an enable signal; And
Determine whether enable said sweep signal according to said enable signal.
13. the control method of sweep trace as claimed in claim 12 is characterized in that, the step that produces said enable signal comprises:
Detect the time that last pixel of said sweep trace enables, and obtain a very first time value signal;
Detect the time that first pixel of said sweep trace enables, and obtain one second time value signal;
With the said second time value signal inversion; And
The second time value signal of said very first time value signal and anti-phase is carried out the computing of logical, to produce said enable signal.
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| CN201110412030.XA CN102436788B (en) | 2008-10-21 | 2008-10-21 | Grid driving module and control method of scan line |
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| CN2008102014785A Division CN101727854B (en) | 2008-10-21 | 2008-10-21 | Output stage circuit, grid electrode drive module and control method of scanning line |
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| CN102436788A true CN102436788A (en) | 2012-05-02 |
| CN102436788B CN102436788B (en) | 2014-02-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109767716A (en) * | 2019-03-12 | 2019-05-17 | 京东方科技集团股份有限公司 | A kind of array substrate, display device and driving method |
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| US20080211787A1 (en) * | 2007-02-20 | 2008-09-04 | Kenji Nakao | Liquid crystal display apparatus |
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| CN1650226A (en) * | 2002-07-05 | 2005-08-03 | 三星电子株式会社 | Liquid crystal display and driving method thereof |
| CN1470929A (en) * | 2002-07-11 | 2004-01-28 | ������������ʽ���� | Photoelectric device and its driving device, driving method and electronic apparatus |
| TW200609879A (en) * | 2004-09-03 | 2006-03-16 | Himax Tech Inc | Output equipment and its driver |
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| CN109767716A (en) * | 2019-03-12 | 2019-05-17 | 京东方科技集团股份有限公司 | A kind of array substrate, display device and driving method |
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| CN102436788B (en) | 2014-02-05 |
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