KR100486292B1 - Output buffer having high slew rate in source driver of liquid crystal display - Google Patents

Abstract

An output buffer having a high slew rate in a source driver of a liquid crystal display is disclosed. In the source driving unit according to the present invention, the output buffer differentially inputs an input signal and a feedbacked output signal to generate a pull-up (down) signal having an inverted characteristic with the input signal and a first control signal differentially amplifying the input signal. The amplifier is driven in response to a predetermined bias voltage and the first control signal, and generates a second control signal having an inverted characteristic to the first control signal, and a response to the pull-up (down) signal and the second control signal. It is characterized in that it comprises an output unit for generating an output signal that follows the input signal while being charged to the power supply level or discharged to the ground power level, and even if the output buffer is configured by using the chopping method can obtain a high slew rate characteristics.

Description

Output buffer having high slew rate in source driver of liquid crystal display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to an output buffer for outputting a signal for controlling charging or discharging of a load capacitor of a liquid crystal panel in a source driver of the liquid crystal display.

In general, the liquid crystal display may be classified into a liquid crystal panel unit and a driver unit.

The liquid crystal panel unit includes a lower glass substrate in which pixel electrodes and thin film transistors are arranged in a matrix, an upper glass substrate formed of a common electrode and a color filter layer, and a liquid crystal layer filled between upper and lower glass substrates.

The driving unit processes a video signal input from the outside and outputs a composite synchronizing signal, and receives a complex synchronizing signal output from the image signal processing unit and separates and outputs a horizontal synchronizing signal and a vertical synchronizing signal according to the mode selection signal. And a gate driver and a source driver for sequentially applying a driving voltage to the scan line and the signal line of the liquid crystal panel unit by the output signal of the controller.

 In the liquid crystal display device configured as described above, the offset between the channels of the source driver plays a very important role in the characteristics of the liquid crystal display device. On the other hand, inducing the offset between the channels in the source driver is due to the output buffer configured in the source driver.

1 is a block diagram schematically illustrating a liquid crystal display device.

In the liquid crystal display illustrated in FIG. 1, a liquid crystal panel 30 having a plurality of pixels at intersections of a plurality of gate lines GL and a plurality of source lines SL, and a source line SL of the liquid crystal panel, respectively, may be used. And a source driver 20 for providing an image signal to a pixel of the gate driver, and a gate driver 10 for turning on a plurality of pixels by selecting the gate line GL of the liquid crystal panel. In this case, each pixel includes a plurality of thin film transistors TR connected with a gate line GL and a drain line connected to a source line SL, and a storage capacitor Cs and a liquid crystal capacitor connected in parallel with the sources of the thin film transistor TR, respectively. (Clc).

FIG. 2 is a block diagram schematically illustrating a source driver of FIG. 1. Digital R, G, and B data input to the source driver are sampled for each pixel (3 pixels = 1 dot) according to the latch enable signal output from the shift register 40, and the latch unit 50 Is latched). The data latch unit 60 inputs and latches the digital R, G, and B data sampled by the latch unit 50 in response to the clock signal clk1. The D / A converter 70 converts the digital R, G, and B data stored in the data latch unit 60 into analog R, G, and B data, and the output buffer 80 is analog in the D / A converter 70. A signal corresponding to the R, G, B data converted into a signal is amplified and output to the data line of the liquid crystal panel.

At this time, in the conventional output buffer, when the output fluctuation is displayed from the output buffer by the supply power supply (Vdd) and the black image is displayed in the normally-white mode liquid crystal, the common output is common every horizontal period. ) Since it is inverted to voltage (Vcom = Vdd / 2) and changes from positive to negative and negative to positive, a large voltage value is required.

Meanwhile, as described above, an offset is generated by a voltage follower amplifier constituting the output buffer, thereby causing a voltage deviation in the output signal. Such a voltage deviation causes the screen quality to deteriorate, such as streaking on the screen in a TFT LCD panel having multiple output characteristics. One of the methods for reducing the random offset is to use a chopping method (Chopping Method), and to drive a different amplifier by dividing the high voltage part and the low voltage part. In this case, the area-side gains are much higher than those using a rail-to-rail voltage follower, but are weak in terms of slew rate. Here, the slew rate is a numerical value indicating how fast the output signal follows the input signal.

FIG. 3 is a circuit diagram showing a conventional high voltage part voltage follower output buffer, and FIG. 4 shows an input signal 90 and an output signal 92 of the output buffer shown in FIG. 3, respectively.

As shown in FIG. 3, in the case of a high voltage part using a normal differential amplifier, there is no problem in the slew rate in the pull-up operation in which the output signal 92 rises, but the N- of the output stage in the pull-down operation in which the output signal 92 rises. The input of the transistor N-TR gate is controlled by the bias voltage BIAS1 having a constant voltage. As described above, the bias voltage BIAS1 having a constant voltage does not have the ability to extract the charge filled in the load capacitor of the TFT-LCD panel connected to the output terminal OUTPUT, and thus the output signal 92 may fall. The slew rate at the time becomes small as shown in FIG.

FIG. 5 is a circuit diagram showing a conventional low voltage part voltage follower output buffer, and FIG. 6 shows an input signal 94 and an output signal 96 of the output buffer shown in FIG. 5, respectively.

Similarly, in the case of the low voltage part shown in FIG. 5, there is no abnormality in the slew rate during the pull-down operation in which the output signal 96 falls as shown in FIG. However, the gate input of the P-TR of the output terminal OUTPUT performing the pull-up operation during the rising operation is fixed to the bias voltage BIAS1 having a constant voltage, thereby raising the output signal 96. The slew rate at becomes small as shown in FIG.

An object of the present invention is to provide an output buffer having a high slew rate in a source driver of a liquid crystal display.

In order to achieve the above object, in the source driving unit according to the present invention, the output buffer differentially inputs an input signal and a feedbacked output signal, a pull-up (down) signal having an inverted characteristic with the input signal, and a first amplified input signal differentially. A differential amplifier for generating a control signal, a control unit for driving a second biased signal having a characteristic inverted to a first control signal, driven in response to a predetermined bias voltage and the first control signal, and the pull-up (down) signal; In response to the second control signal, it is preferable to include an output unit for generating an output signal that follows the input signal while charging to the supply power level or discharged to the ground power level.

In order to achieve the above object, the source buffer in the source driving unit according to the present invention differentially inputs the input signal and the feedback output signal, the pull-up (down) signal having the characteristics inverted from the input signal, and the first signal differentially amplified the input signal A differential amplifier for generating a control signal, an inverter for inverting a first control signal, an inverter for generating a second control signal, and a discharge at a supply power level or a ground power level in response to a second control signal. It is preferable to include an output unit for generating the output signal to follow the input signal.

Hereinafter, an output buffer having a high slew rate in a source driver of a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

7 is a circuit diagram illustrating a first embodiment of an output buffer having a high slew rate in a source driver according to the present invention. The output buffer according to the present invention shown in FIG. 7 is for the output buffer of the high voltage part in the chopper method as described above, and includes a differential amplifier 100, a controller 110, and an output unit 120. .

Referring to FIG. 7, the differential amplifier 100 includes a general differential amplifier, and responds to the switching signal SW and the inverted switching signal SWB by the input signal INPUT and the feedback output signal OUTPUT. A first control signal inputted and differentially amplified in response to the pull-up signal PU having characteristics inverted from the input signal INPUT and the input signal INPUT in response to the switching signal SW and the inverted switching signal SWB. (VHO1) occurs.

The control unit 110 is driven in response to the first bias voltage BIAS1 having the predetermined voltage level and the first control signal VHO1 and has a second control signal having the inverted characteristic to the first control signal VHO1. VHO2). Preferably, the controller 110 includes first and second control transistors IVP1 and IVN1.

The first control transistor IVP1 has a second control signal (Vdd) connected to the source and turned on in response to the level of the first control signal VHO1 input to the gate and having a supply voltage level as a drain. VHO2).

The second control transistor IVN1 is connected in series with the first control transistor IVP1 and has a predetermined voltage input to the gate when the first control transistor IVP1 is turned off in response to the first control signal VHO1. The second control signal VHO2 is turned on in response to the bias voltage BIAS1 to have a ground voltage level connected to the source.

Subsequently, the output unit 120 is driven according to the pull-up signal PU and the second control signal VHO2 to generate an output signal OUTPUT having a supply power supply Vdd or a ground power supply level. In detail, the output unit 120 includes first and second output transistors P1 and N1 and a stabilizing capacitor C1.

When the first output transistor P1 is turned on / off in response to the pull-up signal PU input to the gate, the first output transistor P1 generates an output signal OUTPUT having a level of a power supply connected to a source when turned on.

The second output transistor N1 is connected in series with the first output transistor P1 and, when the first output transistor P1 is turned off in response to the pull-up signal PU, the second control signal VHO2 input to the gate. The output signal OUTPUT having the ground voltage level connected to the source is turned on in response to

The stabilization capacitor C1 is connected between the gate and the output terminal of the first output transistor P1 to stabilize the output signal OUTPUT.

The operation of the apparatus shown in FIG. 7 will now be described. For convenience of explanation, the input signal INPUT is assumed to be the input signal 90 shown in FIG. 4.

When the input signal INPUT is at the high logic level, the pull-up signal PU is at the low logic level by the differential amplification operation to turn on the first output transistor P1. The output signal OUTPUT is at a high logic level by the first output transistor P1 that is turned on. In the rising operation of the output signal OUTPUT, the voltage level of the pull-up signal PU applied to the gate of the first output transistor P1 is Vdd-ΔV (where ΔV is the drain and the source of the first output transistor P1). VDD * 2/3 changes from Vdd * 2/3 to a large VGSp1 (voltage between the gate and the source of the first output transistor P1), thereby driving the load of the TFT LCD panel connected to the output terminal OUTPUT. There is no problem.

When the input signal INPUT becomes the low logic level, the pull-up signal PU becomes the high logic level by the differential amplification operation, and the first control signal VHO1 becomes the low logic level. The first control transistor IVP1 is turned on by the first control signal VHO1 having a low logic level, and the second control signal VHO2 becomes a high logic level. In the output unit 120, the first output transistor P1 is turned off by the pull-up signal PU having a high logic level, and the second output transistor N1 is turned on by the second control signal VHO2 having a high logic level. To output the low logic level output signal OUTPUT. During the falling operation of the output signal OUTPUT, the bias voltage BIAS1 is connected to the gate of the second control transistor IVN1 to receive a constant current and serve as a current load of the first control transistor IVP1. When the output signal OUTPUT falls, the first control signal VHO1 is lowered, and the voltage level of the second control signal VHO2 is increased by the operation of the first control transistor IVP1, and the output signal is lowered. The slew rate characteristic of (OUTPUT) is improved. That is, in the falling operation of the output signal OUTPUT, the gate voltage of the second output transistor N2 is not fixed to the bias voltage as shown in the related art (see FIG. 3), and the first and second control transistors IVP1 and IVN1 are applied. As the level is adjusted, the slew rate is increased.

8 is a circuit diagram illustrating a second embodiment of an output buffer having a high slew rate in a source driver according to the present invention. The output buffer according to the present invention shown in FIG. 8 is for the output buffer of the low voltage part in the chopper method as described above, and includes a differential amplifier 130, a controller 140, and an output unit 150. .

Referring to FIG. 8, the differential amplifier 130 includes a general differential amplifier, and responds to the switching signal SW and the inverted switching signal SWB by the input signal INPUT and the feedback output signal OUTPUT. A third control signal inputted and differentially amplified in response to the switching signal SW and the inverted switching signal SWB in response to the switching signal SW and the inverted switching signal SWB having a pull-down signal PD having a characteristic inverted from the input signal INPUT. VLO1).

The controller 140 is driven in response to the second bias voltage BIAS2 having the predetermined voltage and the third control signal VLO1, and has a fourth control signal VLO2 having an inverted characteristic with the third control signal VLO1. ) Preferably, the controller 140 includes third and fourth control transistors IVP2 and IVN2.

The third control transistor IVP2 is connected in series with the fourth control transistor IVN2 and has a predetermined voltage input to the gate when the fourth control transistor IVN2 is turned off in response to the third control signal VLO1. The fourth control signal VLO2 is turned on in response to the second bias voltage BIAS2 to have a supply voltage level connected to the source.

The fourth control transistor IVN2 has a ground voltage Vdd connected to the source and is turned on in response to the level of the third control signal VLO1 input to the gate and has a ground voltage level as a drain. VLO2).

Subsequently, the output unit 150 is driven according to the pull-down signal PD and the fourth control signal VLO2 to generate an output signal OUTPUT having a supply power supply Vdd or a ground power supply level. In detail, the output unit 150 includes third and fourth output transistors P2 and N2 and a stabilizing capacitor C2.

The third output transistor P2 is connected in series with the fourth output transistor N2 and, when the fourth output transistor N2 is turned off in response to the pull-down signal PD, the fourth control signal VLO2 input to the gate. The output signal OUTPUT having a supply voltage level connected to the source is turned on in response to

The fourth output transistor N2 is controlled on / off in response to the pull-down signal PD input to the gate, and outputs the output signal OUTPUT having a level of ground power connected to the source when the fourth output transistor N2 is turned on in response to the pull-down signal PD. Occurs.

The stabilization capacitor C2 is connected between the gate and the output terminal of the fourth output transistor N2 to stabilize the output signal OUTPUT.

The operation of the apparatus shown in FIG. 8 will now be described. For convenience of explanation, the input signal INPUT is assumed to be the input signal 94 shown in FIG. 6.

When the input signal INPUT is at the low logic level, the pull-down signal PD is at the high logic level by the differential amplification operation to turn on the fourth output transistor N2. The output signal OUTPUT is brought to a low logic level by the fourth output transistor N2 that is turned on. VGSn2 of the fourth output transistor N2 (voltage between the gate and the source of the fourth output transistor) by the pull-down signal PD applied to the gate of the fourth output transistor N2 during the falling operation of the output signal OUTPUT. The value is large enough, so it is not unreasonable to drive the load of the TFT LCD panel connected to the output terminal OUTPUT.

In addition, when the input signal INPUT becomes the high logic level, the pull-down signal PD becomes the low logic level by the differential amplification operation and the third control signal VLO1 becomes the high logic level. The fourth control transistor IVN2 is turned on by the third control signal VLO1 having the high logic level, and the fourth control signal VLO2 becomes the low logic level. The output unit 150 is turned off by the pull-down signal PD having a low logic level, and the third output transistor N2 is turned off, and the third output transistor P2 is turned on by the fourth control signal VLO2 having a low logic level. The output signal OUTPUT of high logic level is output. In the rising operation of the output signal OUTPUT, the bias voltage BIAS2 is connected to the gate of the third control transistor IVP2 to receive a constant current and serve as a current load of the third control transistor IVP2. When the output signal OUTPUT rises, the third control signal VLO1 increases, and the voltage level of the fourth control signal VLO2 decreases due to the operation of the fourth control transistor IVN2. The characteristic of the slew rate of OUTPUT) is improved. That is, the gate voltage of the third output transistor P2 is not fixed to a predetermined bias voltage in the rising operation of the output signal OUTPUT as in the related art (see FIG. 5), and the third and fourth control transistors IVP2 and IVN2 are not fixed. By adjusting the level, the slew rate is increased.

9 is a circuit diagram illustrating a third embodiment of an output buffer having a high slew rate in the source driver according to the present invention. The output buffer according to the present invention shown in FIG. 9 is for the output buffer of the high voltage part in the chopper method as described above, and the control unit 110 of the output buffer shown in FIG. 7 is implemented by the inverter 210. Meanwhile, operations of the amplifier 200 and the output unit 220 shown in FIG. 9 perform the same operations as those described with reference to FIG. 7, and thus detailed description thereof will be omitted.

10 is a circuit diagram illustrating a fourth embodiment of an output buffer having a high slew rate in the source driver according to the present invention. The output buffer according to the present invention shown in FIG. 10 is for the output buffer of the low voltage part in the chopper method as described above, and the controller 140 of the output buffer shown in FIG. 8 is implemented by the inverter 240. Meanwhile, the operations of the amplifier 230 and the output unit 250 shown in FIG. 10 perform the same operations as those described with reference to FIG. 8, and thus detailed description thereof will be omitted.

As described above, the output buffer for the high voltage part of the source driver according to the present invention is not controlled by a constant bias voltage during the falling operation of the output signal, but is controlled by the control transistors IVP1 and IVN1 or an inverter. By controlling the level, the driving ability can be improved. Therefore, it is possible to improve the slew rate characteristic during the falling operation of the output signal OUTPUT. In addition, in the case of the output buffer for the low voltage part of the source driver according to the present invention, the voltage level is not controlled by the constant bias voltage during the rising operation of the output signal OUTPUT, but by the control transistors IVP2 and IVN2 or the inverter. By controlling, the driving ability can be improved, and therefore, the slew rate characteristic can be improved during the falling operation of the output signal OUTPUT.

11A and 11B illustrate slew rate characteristics of a conventional high voltage part output buffer and a low voltage part output buffer. Referring to FIG. 11A, in the conventional high voltage part output buffer, the slew rate characteristic of the output signal OUT1 when falling is lower than the slew rate characteristic of the output signal OUT1 when rising. In addition, referring to FIG. 11B, in the conventional low voltage part output buffer, the slew rate characteristic of the output signal OUT2 when rising is lower than that of the output signal OUT2 when falling.

12A and 12B are diagrams illustrating slew rate characteristics in the high voltage part output buffer and the low voltage part output buffer according to the present invention, respectively. Referring to FIG. 12A, it is shown that the slew rate characteristic of the output signal OUT3 when the high voltage part output buffer is lower than the slew rate characteristic of the output signal OUT3 when falling is illustrated in FIG. 11A. 12B, the slew rate characteristic of the output signal OUT4 when the low voltage part output buffer is raised in accordance with the present invention is improved than the slew rate characteristic of the output signal OUT2 when the rise is shown in FIG. 11B.

13A and 13B show gain and phase waveforms obtained by AC simulation in the high voltage part output buffer and the low voltage part output buffer according to the present invention, respectively. 13A shows a gain waveform GAIN1 and a phase waveform PHASE1 in the high voltage part amplifier. Referring to Figure 13A, it is shown that the phase is about -150 ° when the gain is zero. In general, when the gain is zero, oscillation occurs when the phase is 180 ° or more. Therefore, when the gain is zero, the phase must be less than 180 ° so that the output signal can be generated stably. On the other hand, in Fig. 13A, when the gain is 0, the phase is about -150 °, so a phase margin of about 30 ° can be obtained, and thus a stable output signal can be obtained.

13B also shows a gain waveform GAIN2 and a phase waveform PHASE2 in the low voltage part output buffer. Similarly in FIG. 13B, when the gain is zero, the phase is about -150 °, so a phase margin of about 30 ° can be obtained. Therefore, it can be seen that a stable output signal can be obtained even in the case of the low voltage part output buffer.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the output buffer in the source driver of the liquid crystal display according to the present invention, the voltage level is controlled by control transistors or inverters without being controlled by a constant bias voltage during the falling or rising operation of the output signal. By improving the driving capability, the slew rate characteristic can be improved. Therefore, even if the output buffer is configured using the chopping method, high slew rate characteristics can be obtained.

1 is a block diagram schematically illustrating a liquid crystal display device.

FIG. 2 is a block diagram schematically illustrating a source driver in FIG. 1.

3 is a circuit diagram illustrating a conventional high voltage part voltage follower output buffer.

4 shows an input signal and an output signal of the output buffer shown in FIG. 3, respectively.

5 is a circuit diagram illustrating a conventional low voltage part voltage follower output buffer.

FIG. 6 shows an input signal and an output signal of the output buffer shown in FIG. 5, respectively.

7 is a circuit diagram illustrating a first embodiment of an output buffer having a high slew rate in a source driver according to the present invention.

8 is a circuit diagram illustrating a second embodiment of an output buffer having a high slew rate in a source driver according to the present invention.

9 is a circuit diagram illustrating a third embodiment of an output buffer having a high slew rate in the source driver according to the present invention.

10 is a circuit diagram illustrating a fourth embodiment of an output buffer having a high slew rate in the source driver according to the present invention.

11A and 11B illustrate slew rate characteristics of a conventional high voltage part output buffer and a low voltage part output buffer.

12A and 12B are diagrams illustrating slew rate characteristics in the high voltage part output buffer and the low voltage part output buffer according to the present invention, respectively.

13A and 13B show gain and phase waveforms obtained by AC simulation in the high voltage part output buffer and the low voltage part output buffer according to the present invention, respectively.

Claims (12)

A differential amplifier for differentially inputting an input signal and a feedbacked output signal to generate a pull-up signal having a characteristic inverted from the input signal and a first control signal differentially amplifying the input signal; A control unit which is driven in response to a predetermined bias voltage and the first control signal and generates a second control signal having an inverted characteristic to the first control signal; And And an output unit configured to generate the output signal following the input signal while being charged to a supply power level or discharged to a ground power level in response to the pull-up (down) signal and the second control signal. Output buffer. The method of claim 1, wherein the control unit A first source including a source connected to the supply voltage, a gate connected to the first control signal, and a drain configured to generate a second control signal having the supply voltage level when turned on in response to a first control signal input to the gate; Control transistors; And A gate connected to a bias voltage having a predetermined voltage, a source connected to the ground power source, and a drain connected to a drain of the first control transistor, wherein the first control transistor is turned off in response to the first control signal. And a second control transistor which is turned on by the bias voltage and generates a second control signal having a ground voltage level through the drain. The method of claim 1, wherein the control unit A second control signal including a source connected to a ground voltage and a gate connected to the first control signal, the second control signal having a ground voltage level connected to the source through a drain by being turned on in response to the level of the first control signal input to the gate; A third control transistor for generating a; And A drain connected to the drain of the third control transistor, a gate connected to the bias voltage and a source connected to a supply voltage, and when the third control transistor is turned off in response to the first control signal, And a fourth control transistor configured to generate a second control signal having a supply voltage level connected to the source and connected to the source through a drain. The method of claim 1, wherein the output unit A first output transistor including a gate connected to the pull-up signal and a source connected to the supply power, and when the output signal is turned on in response to the pull-up signal, the output signal having a level of supply power connected to the source through a drain; And A drain connected to the drain of the first output transistor, a gate connected to the second control signal, and a source connected to a ground power source, and when the first output transistor is turned off in response to the pull-up signal, the second control signal And a second output transistor configured to generate an output signal having a ground voltage level connected to the source and connected to the source through a drain. The method of claim 4, wherein the output unit And a stabilizing capacitor connected between the gate and the drain of the first output transistor to stabilize the output signal. The method of claim 1, wherein the output unit A third output transistor having a gate connected to the pull-down signal and a source connected to ground power, and generating an output signal having a level of ground power connected to the source through a drain when turned on in response to the pull-down signal; And A drain connected to the drain of the third output transistor, a gate connected to the second control signal, and a source connected to a supply voltage, and the third output transistor is turned off in response to the pull-down signal; And a fourth output transistor responsive to generate an output signal having a supply voltage level coupled to the source through a drain. The method of claim 6, wherein the output unit And a stabilizing capacitor connected between the gate and the drain of the third output transistor to stabilize the output signal. A differential amplifier for differentially inputting an input signal and a feedbacked output signal to generate a pull-up signal having a characteristic inverted from the input signal and a first control signal differentially amplifying the input signal; A first inverter inverting the first control signal to generate a second control signal; And And an output unit configured to generate the output signal following the input signal while being charged to a supply power level or discharged to a ground power level in response to the pull-up (down) signal and the second control signal. Output buffer. The method of claim 8, wherein the output unit A first output transistor including a gate connected to the pull-up signal and a source connected to the supply power, and when the output signal is turned on in response to the pull-up signal, the output signal having a level of supply power connected to the source through a drain; And A drain connected to the drain of the first output transistor, a gate connected to the second control signal, and a source connected to a ground power source, and when the first output transistor is turned off in response to the pull-up signal, the second control signal And a second output transistor configured to generate an output signal having a ground voltage level connected to the source and connected to the source through a drain. The method of claim 9, wherein the output unit And a stabilizing capacitor connected between the gate and the drain of the first output transistor to stabilize the output signal. The method of claim 8, wherein the output unit A third output transistor having a gate connected to the pull-down signal and a source connected to ground power, and generating an output signal having a level of ground power connected to the source through a drain when turned on in response to the pull-down signal; And A drain connected to the drain of the third output transistor, a gate connected to the second control signal, and a source connected to a supply voltage, and the third output transistor is turned off in response to the pull-down signal; And a fourth output transistor responsive to generate an output signal having a supply voltage level coupled to the source through a drain. The method of claim 11, wherein the output unit And a stabilizing capacitor connected between the gate and the drain of the third output transistor to stabilize the output signal.