CN102436781B - Microprocessor order split device based on implicit relevance and implicit bypass - Google Patents
Microprocessor order split device based on implicit relevance and implicit bypass Download PDFInfo
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- CN102436781B CN102436781B CN201110346810.9A CN201110346810A CN102436781B CN 102436781 B CN102436781 B CN 102436781B CN 201110346810 A CN201110346810 A CN 201110346810A CN 102436781 B CN102436781 B CN 102436781B
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Abstract
The invention discloses a microprocessor order split device based on implicit relevance and an implicit bypass, comprising a detecting and splitting unit required to split order, which is used for judging whether the coded order entering the microprocessor order split device is the order required to split and splitting the order required to split into two atom orders; a split order processing unit, which is used for receiving at least two atom orders split from the order required to split by the split unit required to split order, structuring the implicit relevance for these atom orders and outputting the processed atom order; the other processing unit, which is used for receiving the order judged to not require to split by the detecting and processing unit of the order required to split and the atom order finally generated by the split order processing unit, finishing the order subsequent process and executing work. When the complex operation order with front and rear data relevance is split, the invention can effectively reduce the occupied hardware resource, expand the range of the order to be split and improve the performance of the processor.
Description
Technical field:
The present invention relates to flush bonding processor field, especially a kind of microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass.
Background technology:
Deepening continuously and expanding of the development embedded microprocessor application of modern integrated circuits technology, makes storer become the key factor of restriction microprocessor cost and power consumption.Under specific hardware resource prerequisite, how to strengthen instruction set function, improve code density and instruction execution efficiency, be the problem that a lot of processor designers must face.A lot of flush bonding processors are for application-specific, and the removable complex operations instruction that is divided into several atomic operations while carrying out by introduce several in instruction set has proposed the solution of this problem.Consider the implementation complexity that processor hardware resource, power consumption and instruction split, general processor is only to having the complex operations instruction of good concurrency to split between each operation, as loaded data from Coutinuous store region to general working storage, or the data of a plurality of general working storages are stored into storer.
The complex operations instruction of data dependence before and after fractionation has, should solve the data dependence between atomic instructions after splitting, and eliminates as early as possible again this correlativity, needs larger hardware resource support, and its realization has larger difficulty.Thereby this has limited by splitting complex operations instruction and has improved the ability that processor code density strengthens instruction set function.
With a 32-bit microprocessor, the relation between processor hardware resource and instruction set function is described.This processor always has 16 general working storage R0-R15, there are the performance elements such as arithmetic operator unit and memory read/write unit, wherein each cycle of arithmetic operator unit can only complete once add, subtract, the atomic operation such as multiplication and division, displacement, memory read/write unit each cycle can only complete primary memory and read or write atomic operation, and each performance element has 2 working storage read ports.Under such hardware design, if the data of working storage Rk need to be deposited and be take working storage Ri and Rj data and be the storage area of address, need two instructions: first use " ADD RiRj " instruction that Ri and Rj data are added, result is deposited in Ri; With store Rk Ri, complete final operation again; In like manner, if need to jump to two code regions that register data sum is indicated, also need two instructions to cooperate.
Summary of the invention
In order to overcome existing microprocessor, before and after fractionation has, need to consume great amount of hardware resources during the complex operations instruction of data dependence, limited detachable instruction scope, limited the deficiency of processor performance, the invention provides a kind of scope that takies hardware resource, expands its detachable instruction, microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass that promotes processor performance of effectively reducing during the complex operations instruction of data dependence before and after fractionation has.
The technical solution adopted for the present invention to solve the technical problems is:
A microprocessor instruction detachment device for implicit expression correlativity and implicit expression bypass, described microprocessor instruction detachment device comprises:
Need to split command detection and split cells, whether the translation instruction that enters this microprocessor instruction detachment device in order to judgement is to need to split instruction, and need are split to instruction is split as at least two atomic instructions;
Split instruction process unit, be connected in and need to split instruction fractionation and detecting unit output terminal, in order to reception, from this, need split instruction split cells this need be split at least two atomic instructions that instruction splits into, to these atomic instructions structure implicit expression correlativitys, and introduce implicit expression bypass technology, export processed atomic instructions;
Other processing units, be connected in the output terminal that needs to split the output terminal of command detection and split cells and split instruction process unit, in order to receive, needed fractionation command detection and processing unit are judged as without the instruction splitting and have split the final atomic instructions generating of instruction process unit, and completed instruction subsequent treatment, execution work.
Further, this atomic instructions that has split the final generation of instruction process unit is processed according to stereotyped command in this microprocessor.
Preferably, described need fractionation in command detection and split cells, is safeguarded with splitting two states by idle, and wherein, while entering this command detection and split cells without fractionation instruction, this command detection and split cells, in Idle state, occur without splitting action; When need splitting instruction and entering this command detection and detachment device, this command detection and split cells enter fractionation state, return to Idle state after instruction is split into some atomic instructions.
Further again, the described instruction process unit that split comprises:
Structure implicit expression correlation module, in order to indicate and to safeguard that this need split correlativity between several atomic instructions of the split one-tenth of instruction, in this structure implicit expression correlation module and this microprocessor, correlativity maintenance module is independent mutually;
Implicit expression bypass module, is responsible for the bypass of data, in order to this need be split to several atomic instructions execution results with data dependence of the split one-tenth of instruction, carries out bypass, and in this implicit expression bypass module and this microprocessor, explicit bypass module is independent mutually.
Further, this need split instruction and be split as at least two and split atomic instructions, wherein having two of data dependence has split atomic instructions and is defined as first and has split instruction and second and split instruction, second has split director data is relevant to first and has split instruction, implicit expression bypass module has split instruction instruction sequence number in particular module in microprocessor to first and has processed, make second to split after instruction bypass to the first split director data, first has split instruction just can carry out end.
The technical conceive of this device is: microprocessor instruction set is the direct interphase of microprocessor hardware and software, user notifies microprocessor hardware to complete related work amount by microprocessor instruction, and microprocessor instruction set is one of effective tool improving microprocessor efficiency.The widely used risc instruction set of microprocessor, although can very effectively be suitable for adopting the architecture of streamline, super pipeline and superscale technology, improves a lot to processor performance at present.Yet because every instruction practical function of risc instruction set is limited, during programming, user need to be subdivided into workload the accessible atomic operation of each RISC instruction.In some particular application, as the read-write of storer mass data, frequent redirect etc., user need to reuse several functionally similar instructions.These have all increased the code operation amount of writing undoubtedly.Therefore, most of processors have been introduced some complex operations instructions, and reduction instruction is write, and improve instruction execution efficiency and code density.In order to increase these complex operations instructions saving hardware cost and do not affect under the prerequisite of performance, most of microprocessors have all been introduced instruction and have been split mechanism, yet these instructions split mechanism, can only split the complex operations instruction with higher concurrency, very difficult processing has the complex operations instruction of data dependence.
In order to expand the scope of detachable instruction, this microprocessor has been introduced a kind of microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass technology, in microprocessor, all translation instructions all will be delivered to need fractionation command detection and the split cells of this microprocessor instruction detachment device, needing to split command detection and split cells needs the instruction splitting to split to detecting, and the instruction having split is delivered to and split instruction process unit, one splits instruction process unit builds implicit expression correlativity and implicit expression bypass to these instructions, several atomic instructions that can successively process separately for this microprocessor of final generation.
Beneficial effect of the present invention is mainly manifested in: expanded the detachable instruction type of microprocessor and scope, reduced microprocessor programming complicacy, effectively improved code density, saved hardware resource.
Accompanying drawing explanation
Fig. 1 is for introducing the moving direction of microprocessor instruction of microprocessor instruction detachment device.
Fig. 2 is microprocessor instruction decoding information after introducing microprocessor instruction detachment device.
Fig. 3 is microprocessor instruction detachment device instruction disassembled form machine.
Embodiment
Below in conjunction with accompanying drawing, the invention will be further described.
With reference to Fig. 1～Fig. 3, a kind of microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass, the wall scroll of decoding complex operations instruction that cannot disposable independent processing by microprocessor splits into the atomic instructions that several these microprocessors can successively be processed, and this microprocessor instruction detachment device comprises:
Need to split command detection and split cells, whether the translation instruction that enters this microprocessor instruction detachment device in order to judgement is to need to split instruction, and need are split to instruction be split as at least two atomic instructions, be the input end of this microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass technology; And
Split instruction process unit, be connected in and need to split instruction fractionation and detecting unit output terminal, in order to reception, from this, need split instruction split cells this need be split at least two atomic instructions that instruction splits into, to these atomic instructions structure implicit expression correlativitys, and introduce implicit expression bypass technology, export processed atomic instructions.
Other processing units, be connected in the output terminal that needs to split the output terminal of command detection and split cells and split instruction process unit, in order to receive, needed fractionation command detection and processing unit are judged as without the instruction splitting and have split the final atomic instructions generating of instruction process unit, and completed instruction subsequent treatment, execution work.
Shown in Fig. 1, without the instruction splitting through the flow direction of this microprocessor instruction detachment device as shown in black arrow in way, need to split instruction through the flow direction of this device as shown in red arrow in way.Microprocessor is got the instruction got unit, location after decoding, all will be by needing to split command detection and split cells in this device, need fractionation command detection and split cells to determine by the fractionation zone bit of reading command decoding information whether this instruction needs to split: if without fractionation, other processing units are directly delivered in instruction, complete instruction and carry out; If needed, split, need to split command detection and split cells by detecting instruction operation code, determine that this instruction need to be split as the instruction of several what types, according to these instructions, split information, need to split command detection and split cells state machine and split by completing instruction at Idle state with the switching that splits state.
The atomic instructions having split is sent to and splits instruction process unit, adds correlation information; Suppose that first has split instruction A and second and split instruction B and split instruction, second has split instruction B data is relevant to first and has split instruction A.Split instruction process unit, second, split in the operational code of instruction B, added specific implicit expression correlation information, indicated second to split instruction B and be relevant to first and split instruction A.In order to accelerate the first execution speed that has split instruction A, B, prevent that first has split instruction A and cross early retirement and cause second to split instruction B and cannot obtain its data simultaneously, implicit expression bypass technology, by the first data that split instruction A, give second in advance and split instruction B, only have second to split after instruction B acquisition data, just allow first to split instruction A retirement.After these are processed, the atomic instructions having split is sent to other processing units, completes instruction carry out according to general instruction.These atomic instructions are all carried out end, represent that this complex operations instruction execution finishes.
Shown in Fig. 2, during Instruction decoding, in the decoding information of instruction, added split position, in order to characterize this instruction, whether need to split.The instruction type splitting into and number of instructions, decided by instruction operation code.
Shown in Fig. 3, do not need to split instruction and enter while needing to split instruction split cells, the state machine of this unit, in Idle state, characterizes minimum power consumption expense; When need fractionation instruction enters need fractionation instruction split cells, its state machine jumps to fractionation state, and the atomic instructions number that each machine cycle splits out is determined by microprocessor hardware resource.If this microprocessor is single transmit, each cycle splits out an atomic instructions; Two sending out or multi-emitting, splits out two or many atomic instructions if.After fractionation finishes, state machine returns to Idle state.
At 32-bit microprocessor mentioned above, introduce after microprocessor instruction detachment device, again analyze its instruction set and code density.Now, first in instruction set, increase corresponding complex operations instruction storea Ri, Rj, Rk, take working storage Ri and Rj data and be the storage area of address for the data of working storage Rk are deposited.When processor is carried out, this instruction is split as " ADD RiRj " and " store Ri, Rk ", and ADD Ri Rj is in order to the value of Ri and Rj is added, and result is deposited in Ri; Store Ri, Rk, stores the data in Rk into Ri indicated storage address.In this way, with a complex operations instruction, realize the function of two atomic instructions, increased code density; And only need to carry out a decoding, saved decoding time.Not only reduce cost, also improved instruction execution efficiency simultaneously.
Claims (5)
1. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass, is characterized in that, described microprocessor instruction detachment device comprises:
Need to split command detection and split cells, whether the translation instruction that enters this microprocessor instruction detachment device in order to judgement is to need to split instruction, and need are split to instruction is split as at least two atomic instructions;
Split instruction process unit, be connected in and need to split instruction fractionation and detecting unit output terminal, in order to reception, from this, need split instruction split cells this need be split at least two atomic instructions that instruction splits into, to these atomic instructions structure implicit expression correlativitys, and introduce implicit expression bypass technology by implicit expression bypass module, export processed atomic instructions;
Other processing units, be connected in the output terminal that needs to split the output terminal of command detection and split cells and split instruction process unit, in order to receive, needed fractionation command detection and split cells are judged as without the instruction splitting and have split the final atomic instructions generating of instruction process unit, and completed instruction subsequent treatment, execution work.
2. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 1, is characterized in that, this has split the final atomic instructions generating of instruction process unit and according to stereotyped command, has processed in this microprocessor.
3. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 1 and 2, it is characterized in that, described need in fractionation command detection and split cells, by idle, safeguarded with fractionation two states, wherein, without splitting instruction, enter while needing to split command detection with split cells, need to split command detection with split cells in Idle state, without splitting, move generation; Need to split instruction and enter while needing to split command detection with split cells, need fractionation command detection and split cells to enter fractionation state, return to Idle state after instruction is split into some atomic instructions.
4. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 1 and 2, is characterized in that, the described instruction process unit that split comprises:
Structure implicit expression correlation module, in order to indicate and to safeguard that this need split correlativity between several atomic instructions of the split one-tenth of instruction, in this structure implicit expression correlation module and this microprocessor, correlativity maintenance module is independent mutually;
Implicit expression bypass module, is responsible for the bypass of data, in order to this need be split to several atomic instructions execution results with data dependence of the split one-tenth of instruction, carries out bypass, and in this implicit expression bypass module and this microprocessor, explicit bypass module is independent mutually.
5. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 4, it is characterized in that, this need split instruction and be split as at least two and split atomic instructions, wherein having two of data dependence has split atomic instructions and is defined as first and has split instruction and second and split instruction, second has split director data is relevant to first and has split instruction, implicit expression bypass module has split instruction instruction sequence number in particular module in microprocessor to first and has processed, make second to split after instruction bypass to the first split director data, first has split instruction just can carry out end.
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| CN111090465B (en) * | 2019-12-19 | 2022-08-19 | 四川长虹电器股份有限公司 | Decoding system and decoding method for RV32IC instruction set |
| CN114401298B (en) * | 2021-12-16 | 2023-03-21 | 荣耀终端有限公司 | Data transmission method, router, device, system and storage medium |
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