CN109918130A - A kind of four level production line RISC-V processors with rapid data bypass structure - Google Patents
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Abstract
The present invention provides a kind of four level production line RISC-V processors with rapid data bypass structure, has four stage pipeline structures, when executing the operation other than non-Load instruction, is directly bypassed, valid data assembly line becomes three-level, to accelerate arithmetic speed.Above structure reduces the frequency of the instruction cycle largely instructed and data hazard appearance, substantially increases the performance of processor compared to four traditional level production lines.Four stage pipeline structures are respectively fetching module, decoding module, execution module and write back module.Fetching module can generate the PC of next instruction according to the instruction and external control signal that current period is fetched from command memory；Decoding module is used to extract operation code, function code, source register, destination register and the immediate of instruction, and the value from general register；Execution module is responsible for executing various arithmetic operators；Module is write back for recording the information of access instruction and general register being written in the data read from memory.
Description
Technical field
The present invention relates to Design of Digital Integrated Circuit fields, have rapid data bypass structure more particularly, to one kind
Four level production line RISC-V processors.
Background technique
In recent years, with the fast development of technology of Internet of things, market on intelligent terminal low-power consumption, at high-performance
It is increasing to manage device demand.How in the performance requirement for reducing cost with meeting intelligent terminal to processor while power consumption, it is
One more popular research direction.RISC-V instruction set is that the open source established based on reduced instruction set computing (RISC) principle is referred to
Enable collection framework (ISA).Compared to ARM the and x86 instruction set of mainstream, RISC-V is had the advantage that
Any authorization expense is not collected in 1.RISC-V foundation, and RISC-V instruction set itself is increased income completely, uses BSD agreement.
This point largely reduces the cost of processor.
2. having abandoned some unreasonable ISA design philosophys in eighties of last century using succinctly with advanced design concept, having made
Pass through the technology and theory of the comparative maturity that years development is accumulated with Computer Architecture, and does not bear simultaneous backward
The historical burden of appearance.
3. have the RISC-V processor much increased income realization, and ARM and x86 processor otherwise not open source or not
Allow to modify it, this makes RISC-V have lower learning cost.
4.RISC-V foundation is responsible for safeguarding tools chain, and all tools chains are also open source.Therefore hard
Exploitation and compatibility issue of the part designer without having to worry about tools chain only need to be absorbed in hardware design, this also mitigates significantly
The cost of processor.
China only has a small amount of patent and is related to the architecture design of RISC CPU at present.Authorization Notice No. is CN 102221991
The patent of invention of A discloses a kind of 4 digit RISC micro controllers；Authorization Notice No. is that the patent of invention of 101221494 A of CN discloses
A kind of 8 novel digit RISC micro controllers；Authorization Notice No. is that the patent of invention of 102262611 B of CN discloses one kind 16
The RISC cpu system structure of position.These are past when handling the arithmetical operation of 32 common bit variables lower than 32 microprocessors
Toward a plurality of instruction is needed, performance is difficult to reach demand.
32-bit microprocessor has the function of powerful numerical operation and addressing, it can cover 8 and the microprocessor of 16 bit
Institute it is functional, therefore shared share in Intelligent terminal for Internet of things is increasing.Authorization Notice No. is CN 101256546
The patent of invention of A discloses a kind of 32-bit microprocessor, but its instruction set used is inventor oneself definition, is not had
Versatility, and supported without matched tools chain.
In conclusion enhance its versatility to reduce the design of microprocessor on intelligent terminal and research and development cost,
Need to design a kind of novel 32 bit CPUs based on RISC-V instruction set.
Summary of the invention
For deficiency existing for existing microprocessor architecture and this specific application scenarios of Internet of Things, the present invention is proposed
A kind of four level production line RISC-V processors with rapid data bypass structure.The present invention is by combining RISC-V instruction set
Characteristic, the internal structures of pipelined units at different levels and control signal are improved, has reached and has met performance requirement
Under the premise of reduce the purpose of chip power-consumption and area as far as possible.
The present invention proposes a kind of four level production line RISC-V processors with rapid data bypass structure, and the present invention uses
Technical solution be:
A kind of four level production line RISC-V processors with rapid data bypass structure proposed by the present invention, feature exist
In including that can be four stage pipeline structures of level Four, memory access unit, exception/interrupt according to the overall length of instruction type dynamic adjustment
Processing unit, several registers, memory,
The memory includes command memory and data storage；
The register includes general register, for temporal data and transmission data；
The memory access unit is connected directly with command memory, data storage, is stored to command memory and data
Device sends read write command, and the feedback signal that command memory and data storage transmit is sent to and writes back module；
The exception/interrupt processing unit is for detecting outside the exception and reception that CPU is encountered when executing instruction
Then the interrupt signal transmitted to CPU determines the exception/interrupt service of CPU execution according to different abnormal causes and interrupt source
Function；
Four stage pipeline structures are respectively fetching module, decoding module, execution module and write back module, fetching mould
Block can generate the PC of next instruction according to the instruction and external control signal that current period is fetched from command memory；It translates
Code module is used to extract operation code, function code, source register, destination register and the immediate of instruction, and from general deposit
Value in device；Execution module is responsible for executing various arithmetic operators；Write back module for record access instruction information and will be from depositing
The data write-in general register read in reservoir.
Data/address bus and address-bus width between memory and CPU are 32.
The first order of assembly line be fetching module, including PC register, instruction temporary storage location, compression instruction extension unit,
Return address line and inch prediction unit store command memory in current period in the PC register and are transmitted to fetching mould
The corresponding PC of the instruction of block；The instruction temporary storage location is used to store high 16 of 32 data of taking-up and by itself and taking-up
32 data 32 data of low 16 compositions be transmitted to compression instruction extension unit；
The compression instruction extension unit is transmitted through low 16 of 32 data come for decision instruction temporary storage location
No is a compression instruction, if compression instruction is then extended to 32 ordinary instructions；Otherwise without any processing；
The return-address stack is for storing the return address that program is used when calling function；
The inch prediction unit is used for when the instruction that fetching module is fetched from command memory is jump instruction,
Inch prediction unit can predict next instruction PC of jump instruction.Fetching module can be deposited according to current period from instruction
The instruction and external control signal fetched in reservoir generate next instruction program counter (Program Counter,
PC PC and the fetching order for), and in current period to command memory sending next instruction, refer within the next period in this way
Enable memory that can export next instruction.If the instruction that current period takes out is jump instruction, the branch in fetching module
Predicting unit can predict the PC value of next instruction according to the partial information in jump instruction, rather than simply pass PC
Increase.
The second level of assembly line is decoding module, including decoding module includes at command information extraction unit and jump instruction
Manage unit.Decoding module is used to extract operation code, function code, source register, destination register and the immediate of instruction, and
Jump instruction is handled.Source register used in instruction in decoding module is equally likely to execute or write back in module
Destination register used in instructing, such case are RAW conflict；Destination register used in instruction in decoding module can
Destination register used in the instruction for executing or writing back in module can be equal to, such case is WAW conflict.Therefore decoding module
It also to determine to take forwarding strategy or pause part assembly line as the case may be.
The third level of assembly line is execution module.In execution module include adder, barrel shifter, logical-arithmetic unit,
Hardware multiplier and division controller.When the instruction in execution module will calculate multiplication and division, can not calculate in one cycle
It finishes, pause signal must be sent to the first order of assembly line and the second level in this case, prevent next article of instruction from entering the
Three-level.For not needing the instruction of memory access, just has been carried out and finish when running to the assembly line third level, do not need to enter stream
The waterline fourth stage.
The fourth stage of assembly line is to write back module.Module is write back for recording the information of access instruction and reading memory access unit
The data got write back general register.
Memory access unit is connected directly with instruction and data memory, sends read write command to memory, memory is transmitted
Feedback signal be sent to and write back module.
Preferably, the jump instruction includes unconditional directly jump instruction jal, unconditional indirect jump instruction
Jalr, have ready conditions direct jump instruction bxx.
Preferably, the execution module has used the write port 1 of general register that general post is written in the data of needs
Storage needs the instruction of memory access that can enter fourth stage assembly line.
Preferably, the module that writes back is read the instruction of LOAD type using the write port 2 of general register from memory
The data write-in general register taken.
Preferably, the various peripheral hardwares that the interrupt signal is controlled from CPU, including but not limited to timer, modulus/
Digital analog converter, general purpose I/O, universal asynchronous receiving-transmitting transmitter and serial device interfaces.
Preferably, in processor operational process, whether the coding for checking instruction is met the rule of RISC-V by decoding module
It is fixed, exception is reminded if not meeting；Execution module will test whether divisor is 0 before calculating division, if 0 remind it is different
Often；Memory access unit will test whether the address to be accessed is aligned before sending read/write command to memory, remind if being misaligned
It is abnormal；Exception/interrupt processing unit record causes abnormal instruction and PC, and selects abnormality processing function.In outside is transmitted
When break signal, in order to achieve the purpose that respond rapidly to interruption, exception/interrupt processing unit, which will record, writes back module or execution module
In instruction PC, and according to the number of external interrupt selection jump to some interrupt processing function.
Compared with prior art, the beneficial effect of technical solution of the present invention is:
(1) the four level production line RISC-V processors provided by the invention with rapid data bypass structure not needing
The instruction of memory access has only used the preceding three-level of assembly line without entering the assembly line fourth stage, and the calculated result instructed in this way can be more
Early is written into general register.Compared to four traditional stage pipeline structures, pipeline organization proposed by the present invention is simplified
The control logic of data forwarding, and reduce the transmitting of the information between the third level and the fourth stage.
(2) for read-after-write (Read After Write, RAW) or write after write are not present between subsequent instructions
The access instruction of (WriteAfter Write, WAW) conflict will not be temporary when it, which needs multiple periods that can just be performed, finishes
Stop preceding three class pipeline, substantially increases processor performance.
(3) characteristic for combining RISC-V instruction set and compiler, has used the very simple inch prediction unit of structure,
The prediction accuracy with higher while being not take up excessive hardware resource reduces the frequency that control venture occurs.
Detailed description of the invention
Fig. 1 is in the CPU of the four level production line RISC-V processors provided by the invention with rapid data bypass structure
The total block architecture diagram of core；
Fig. 2 is the fetching mould of the four level production line RISC-V processors provided by the invention with rapid data bypass structure
Block structural diagram；
Fig. 3 is the decoding mould of the four level production line RISC-V processors provided by the invention with rapid data bypass structure
Block structural diagram；
Fig. 4 is the execution mould of the four level production line RISC-V processors provided by the invention with rapid data bypass structure
Block structural diagram；
Fig. 5 is that four level production line RISC-V processors provided by the invention with rapid data bypass structure write back mould
Block structural diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, only for illustration, Bu Nengli
Solution is the limitation to this patent.Based on the embodiments of the present invention, those of ordinary skill in the art are not making creative labor
Every other embodiment obtained under the premise of dynamic, shall fall within the protection scope of the present invention.
The following further describes the technical solution of the present invention with reference to the accompanying drawings and examples.
Embodiment 1
The present embodiment provides at a kind of four level production line RISC-V with rapid data bypass structure proposed by the present invention
Reason device includes that the overall length that can be adjusted according to instruction type dynamic is four stage pipeline structures of level Four, memory access unit, exception/interrupt
Processing unit, command memory and data storage.Data/address bus and address-bus width between memory and CPU are 32
Position.
The first order of assembly line is fetching module.The effect of fetching module is constantly according to the operating condition of program from finger
Enable the taking-up CPU instruction to be executed in memory.Fetching module includes following part:
1.PC register
The corresponding PC of instruction that current period command memory is transmitted to fetching module is stored in PC register.
2. instructing temporary storage location
Instruction temporary storage location is the memory of a 16-bit.Because CPU supports " compression instruction " defined in RISC-V,
So not only having housed the ordinary instruction of 32-bit in command memory, but also house the compression instruction of 16-bit.RISC-V definition
Compression instruction the partial informations of some usual instructions is omitted, therefore it is empty to reduce the storage that instruction occupies to a certain extent
Between.16-bit instruction presence make fetching module be sent to command memory PC may not be 4 multiple, that is, there is address
The case where being misaligned.But CPU can not know whether to instruct for compression before decoding to instruction, therefore fetching module
32-bit data should be taken out from command memory every time.When the PC that fetching module is sent to command memory is not 4
When multiple, need two periods that could take out 32-bit data, it is therefore desirable to store using instruction temporary storage location and take for the first time
The high 16-bit of 32-bit data out.The 32-bit number that the low 16-bit of its 32-bit data taken out with second is combined into
Instruction extension unit is compressed according to that can be passed to.
3. compressing instruction extension unit
According to the regulation that RISC-V command length encodes, the low 2-bit of instruction then refers to for the compression of 16-bit if not 11
It enables.Therefore compression instruction extension unit can judge this according to low 2 codings for the 32-bit data that instruction temporary storage location transmits
Whether the low 16-bit of 32-bit data is a compression instruction.According to the extension rule of compression instruction if it is compression instruction
It is extended to the ordinary instruction of 32-bit, to facilitate the work decoding of decoding module, while by the high 16- of 32-bit data
Bit deposit instruction temporary storage location, to call later；If not compression instruction then illustrates that 32-bit data are one and commonly refer to
It enables, with no treatment.
4. return-address stack
According to the definition of RISC-V official document, general register x1 can be compiled device in routine call function as letter
Often there is function call in several return addresses following assembly code:
If can will be returned when calling function using jal instruction it can be seen that compiler discovery program needs to call function
It goes back to address to be put into x1, and instructs the value for reading x1 to determine return address using jalr when exiting function.Therefore
The present invention stores the return address that program is used when calling function using return-address stack.Mould is executed when jal instructs to enter
When block, if detecting its rd=x1, not only 4 or PC is added to add 2 result that general register is written the PC being calculated,
It is pressed into return-address stack.It, then will instruction if rs1=x1, imm=0 when the instruction in decoding module is that jalr is instructed
The x1 value read from general register is compared with stack top element value, illustrates that prediction is correct if the two is equal, can be incited somebody to action
Stack top element is popped；Otherwise illustrate prediction error, do not modify the element in stack.
The size of return-address stack can be set as needed, and common value is 4~16.
5. inch prediction unit
When the instruction that fetching module is fetched from command memory is jump instruction, inch prediction unit can refer to jumping
The next instruction PC enabled is predicted.The specific function of inch prediction unit is described below with reference to different types of jump instruction
Can:
1) unconditional directly jump instruction jal
The usage of jal is jalrd, and imm, meaning is that the PC for instructing jal adds the sum of immediate offset imm as jump
Turn destination address, at the same by the PC of jal instruction plus jal instruction length and in deposit destination register rd.Due to one
Surely it can jump, there is no need to predict whether it jumps.And its jump target addresses can be used with the addition in fetching module
Device is calculated.
2) unconditional jump instruction jalr indirectly
The usage of jalr is jalrrd, rs1, imm, and meaning is that the value of source register rs1 is added immediate offset imm
Sum as jump target addresses, while by jalr instruction PC plus jalr instruction length and deposit destination register rd
In.Since it is bound to jump, there is no need to predict whether it jumps.Problem is that jump target addresses to be calculated must be read
The value of source register rs1 is taken, and the instruction only in decoding module could use the read port of general register, therefore theoretically
The jump target addresses of unpredictable jalr instruction.It, can be with returning but in the case where the function as described in (4) returns
The stack top element value of address stack is returned to predict the value as rs1=x1 in register, can then obtain jumping for jalr instruction
Destination address.It is then unpredictable for other situations, it can only just can be carried out in next step until jalr instruction enters decoding module
Reason.
3) it has ready conditions direct jump instruction bxx (beq, blt, bge)
The usage of bxx is bxx rs1, rs2, imm, if the value of the value that meaning is source register rs1 and source register rs2 it
Between meet xx setting relationship then need to jump, while using bxx instruction PC plus immediate offset imm sum as its jump
Turn destination address；Otherwise it does not jump, executes next instruction (such as when bxx is blt, if meeting the value of rs1 less than rs2's
Value, then need to jump).Also the value of register rs1 and rs2 can not be read when bxx instruction is in fetching module.For most common
Cycling condition can be judged that sentence is placed on behind loop body by for Do statement, compiler.Therefore the design based on low-power consumption is thought
Think, the present invention uses a kind of simple static prediction method: the bxx branch prediction jumped backward is jumped for needs, for
The bxx instruction jumped forward is then predicted as not jumping, and the direction jumped can judge according to the highest order of imm；For jump target
Address is obtained using the PC of bxx instruction plus immediate offset imm.
As shown in figure 3, the second level of assembly line is decoding module.Decoding module is used to extract operation code, the function of instruction
Energy code, source register, destination register and immediate, and jump instruction is handled.Decoding module includes following part:
1. command information extraction unit
Command information extraction unit is responsible for extracting the operation code of instruction, function code, source register, destination register and immediately
Number, and required data are read from the read port of general register.For four stage pipeline structures, if decoding module
In instruction source register be equal to execute or the instruction in memory access module destination register, then explanation there are RAW conflicts.Such as
The implementing result of the instruction in subsequent pipeline can be obtained in this period of fruit, then uses retransmission technique, otherwise must suspend flowing water
Line.If the destination register of the instruction in decoding module is equal to the destination register of the instruction in memory access module, illustrate to deposit
Conflict in WAW.Since the instruction write back in module is introduced into assembly line, in order to guarantee that the correctness of data is written, it is necessary to temporarily
Arrhea waterline, pause could be cancelled after the instruction execution in memory access module finishes.
2. jump instruction processing unit
Since fetching module predicts the jalr instruction for the condition that meets and all bxx instructions, so jumping finger
Enable processing unit is responsible for checking whether prediction result is correct.As described in fetching module, if jalr instruction is adjusted when exiting function
With having used return-address stack then to predict the value of register x1.Therefore wait until that instruction enters after decoding module, it be from general
The true value of x1 is read in register, and it is compared with the stack top element value of return-address stack, is illustrated if equal
Prediction is correct, executes Pop operations to stack top element；It is unequal, illustrate prediction error, to use and be read from general register
The true value of x1 calculate jump target addresses；It, at this time can also be with for the jalr instruction that do not make a prediction in upper level
Obtain their true jump target addresses；Bxx is instructed, can be deposited at this time according to the rs1 register value and rs2 of taking-up
Device value judges whether really to need to jump；Jal is instructed, since fetching module has carried out correct prediction, institute to it
Without processing.
As shown in figure 4, the third level of assembly line is execution module.Execution module includes adder, barrel shifter, logic
Arithmetic unit, hardware multiplier and division controller.The core cell of hardware multiplier is the multiplier of a 16-bit, so
3 periods are needed when executing the mul instruction for needing the low 32-bit of 64-bit multiplication result, and need 64-bit multiplication in execution
4 periods are needed when mulh [s] [u] instruction of high 32-bit as a result；Execution module is subtracted each other when calculating division using displacement
Method.In order to reduce area, when division arithmetic is required to subtract each other, shifts and more all using the existing electricity in execution module
Road, without using independent computing circuit.The calculating of division altogether need 36 periods: the 1st cyclic check divisor whether be
0, the 2nd and the 3rd the period calculate separately the absolute value of divisor and dividend, the 4th to the 35th period calculated quotient or remainder, the 36th period
Change the symbol of quotient or remainder according to the concrete condition of divide operations.Execution module execute can not in one cycle operation it is complete
When complete multiplication and division instruction, need forward two level production lines send pause signal to prevent new instruction from entering in execution module.
The instruction for not needing memory access can be performed by three class pipeline to be finished, so execution module has used general register
General register is written in the data of needs by write port 1；Fourth stage assembly line can be entered by needing the instruction of memory access.
As shown in figure 5, the fourth stage of assembly line is to write back module.Module is write back for recording the information of access instruction and inciting somebody to action
The data that memory access unit is read write back general register.CPU support writes back in module there are a unfinished access instruction,
If the access instruction write back in module conflicts with the instruction in decoding module there is no RAW or WAW, preceding three class pipeline is not
Pause, otherwise needs to suspend；If write back in module, there are have new memory access to refer to again while a unfinished access instruction
It enables and enters execution module, then need to suspend entire assembly line until the access instruction write back in module is finished.Write back module
Use the write port 2 of general register that general register is written in the data that the instruction of LOAD type is read from memory.
Memory access unit accesses memory using the address that access instruction is calculated in execution module, and sends read/write
Order and BYTE MASK.
Exception/interrupt processing unit is used to detect the exception that CPU is encountered when executing instruction, and receives external to CPU
The interrupt signal transmitted determines that CPU determines the exception/interrupt service function executed according to different abnormal causes and interrupt source.
The CPU that the present invention designs can detect three kinds of exceptions: illegal RISC-V instruction, divisor 0, memory access address are misaligned.
Decoding module can check whether the coding of instruction meets the regulation of RISC-V, and exception is reminded if not meeting；Execution module is being counted
It can detect whether divisor is 0 before calculating division, if 0 is reminded exception；Memory access unit is sent to memory before read/write command
It can detect whether the address to be accessed is aligned, if exception can be reminded by being misaligned.Exception/interrupt processing unit, which will record, causes exception
Instruction and PC, and according to setting select abnormality processing function.When interrupt signal is transmitted in outside, in reaching and responding rapidly to
Disconnected purpose, exception/interrupt processing unit will record the instruction PC write back in module or execution module, and according to external interrupt
Number selection jump to some interrupt processing function.
Obviously, the above embodiment of the present invention be only to clearly illustrate example of the present invention, and not be pair
The restriction of embodiments of the present invention.For those of ordinary skill in the art, may be used also on the basis of the above description
To make other variations or changes in different ways.There is no necessity and possibility to exhaust all the enbodiments.It is all this
Made any modifications, equivalent replacements, and improvements etc., should be included in the claims in the present invention within the spirit and principle of invention
Protection scope within.
Claims (10)
1. a kind of four level production line RISC-V processors with rapid data bypass structure, which is characterized in that including can basis
The overall length of instruction type dynamic adjustment is four stage pipeline structures of level Four, memory access unit, exception/interrupt processing unit, several
A register, memory,
The memory includes command memory and data storage；
The register includes general register, for temporal data and transmission data；
The memory access unit is connected directly with command memory, data storage, is sent out to command memory and data storage
Read write command is sent, the feedback signal that command memory and data storage transmit is sent to and writes back module；
The exception/interrupt processing unit is for detecting outside the exception and reception that CPU is encountered when executing instruction to CPU
Then the interrupt signal transmitted determines the exception/interrupt service function of CPU execution according to different abnormal causes and interrupt source；
Four stage pipeline structures are respectively fetching module, decoding module, execution module and write back module, fetching module energy
The instruction and external control signal fetched from command memory according to current period generate the PC of next instruction；Decode mould
Block is used to extract operation code, function code, source register, destination register and the immediate of instruction, and from general register
Value；Execution module is responsible for executing various arithmetic operators；Write back module for record access instruction information and will be from memory
In read data write-in general register.
2. the four level production line RISC-V processors according to claim 1 with rapid data bypass structure, feature
It is, the width of data/address bus and address bus between memory and CPU is 32.
3. the four level production line RISC-V processors according to claim 2 with rapid data bypass structure, feature
It is, the fetching module includes PC register, instruction temporary storage location, compression instruction extension unit, return address line and divides
Branch predicting unit,
The corresponding PC of instruction that command memory in current period is transmitted to fetching module is stored in the PC register；
The instruction temporary storage location is used to store high 16 of 32 data of taking-up and by itself and 32 data of taking-up
32 data of low 16 reformulations are transmitted to compression instruction extension unit；
The compression instruction extension unit for decision instruction temporary storage location be transmitted through low 16 of 32 data come whether be
One compression instruction, if compression instruction is then extended to 32 ordinary instructions；Otherwise without any processing；
The return-address stack is for storing the return address that program is used when calling function；
The inch prediction unit is used for the branch when the instruction that fetching module is fetched from command memory is jump instruction
Predicting unit can predict next instruction PC of jump instruction.
4. the four level production line RISC-V processors according to claim 3 with rapid data bypass structure, feature
It is, the decoding module includes command information extraction unit and jump instruction processing unit,
The command information extraction unit is responsible for extracting operation code, the function code, source register, mesh of instruction for extraction unit
Register and immediate, and from the read port of general register read needed for data；
Whether the jump instruction processing unit is correct to the prediction result of jump instruction for verifying value module, if prediction
It is correct then to stack top element execute Pop operations；Need to recalculate the jump target addresses of jump instruction if prediction error.
5. the four level production line RISC-V processors according to claim 1 with rapid data bypass structure, feature
It is, the execution module includes adder, barrel shifter, logical-arithmetic unit, hardware multiplier and division controller.
6. the four level production line RISC-V processors according to claim 4 with rapid data bypass structure, feature
Be, the jump instruction include unconditional directly jump instruction jal, unconditional jump instruction jalr indirectly, have ready conditions it is straight
Meet jump instruction bxx.
7. the four level production line RISC-V processors according to claim 1 with rapid data bypass structure, feature
It is, using the write port 1 of general register general register is written in the data of needs by the execution module, needs memory access
Instruction can enter fourth stage assembly line.
8. the four level production line RISC-V processors according to claim 1 with rapid data bypass structure, feature
It is, the module that writes back is write the data that the instruction of LOAD type is read from memory using the write port 2 of general register
Enter general register.
9. the four level production line RISC-V processors according to claim 1 with rapid data bypass structure, feature
It is, the interrupt signal derives from the peripheral hardware of CPU control, including timer, D and D/A converter, general purpose I/O, general
Asynchronous receiving-transmitting transmitter and serial device interfaces.
10. there are four level production line RISC-V processors of rapid data bypass structure according to claim 1 or 5,
It is characterized in that, extracts in the cataloged procedure of instruction, whether the coding for checking instruction is met the regulation of RISC-V by decoding module,
Exception is reminded if not meeting；Execution module will test whether divisor is 0 before calculating division, if 0 is reminded exception；It visits
Memory cell will test whether the address to be accessed is aligned before sending read/write command to memory, and exception is reminded if being misaligned；
Exception/interrupt processing unit record causes abnormal instruction and PC, and selects abnormality processing function.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110806899A (en) * | 2019-11-01 | 2020-02-18 | 西安微电子技术研究所 | Assembly line tight coupling accelerator interface structure based on instruction extension |
| CN110928832A (en) * | 2019-10-09 | 2020-03-27 | 中山大学 | Asynchronous pipeline processor circuit, device and data processing method |
| CN111078294A (en) * | 2019-11-22 | 2020-04-28 | 苏州浪潮智能科技有限公司 | Instruction processing method and device of processor and storage medium |
| CN111090465A (en) * | 2019-12-19 | 2020-05-01 | 四川长虹电器股份有限公司 | Decoding system and decoding method for RV32IC instruction set |
| CN111124494A (en) * | 2019-12-17 | 2020-05-08 | 天津国芯科技有限公司 | Method and circuit for accelerating unconditional jump in CPU |
| CN111159094A (en) * | 2019-12-05 | 2020-05-15 | 天津芯海创科技有限公司 | RISC-V based near data stream type calculation acceleration array |
| CN111177067A (en) * | 2019-12-13 | 2020-05-19 | 广东高云半导体科技股份有限公司 | System on chip |
| CN111459546A (en) * | 2020-03-30 | 2020-07-28 | 芯来智融半导体科技(上海)有限公司 | Device and method for realizing variable bit width of operand |
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| CN113656074A (en) * | 2021-10-18 | 2021-11-16 | 深圳市智想科技有限公司 | RISC architecture processor and parallel pipeline structure design method thereof |
| CN113779907A (en) * | 2021-09-09 | 2021-12-10 | 中山大学 | HLS-based four-stage pipeline processor design and verification method, system and equipment |
| CN113779755A (en) * | 2021-08-05 | 2021-12-10 | 中科联芯(广州)科技有限公司 | Design method of silicon-based multispectral integrated circuit chip and integrated circuit chip |
| CN113946368A (en) * | 2021-10-29 | 2022-01-18 | 西安微电子技术研究所 | Three-level pipeline architecture based on RISC-V instruction set, processor and data processing method |
| WO2022121090A1 (en) * | 2020-12-09 | 2022-06-16 | 上海交通大学 | Processor supporting high-throughput multi-precision multiplication |
| CN114721724A (en) * | 2022-03-07 | 2022-07-08 | 电子科技大学 | RISC-V instruction set-based six-stage pipeline processor |
| CN115878187A (en) * | 2023-01-16 | 2023-03-31 | 北京微核芯科技有限公司 | Processor instruction processing apparatus and method supporting compressed instructions |
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| CN116991477A (en) * | 2023-08-03 | 2023-11-03 | 上海合芯数字科技有限公司 | Rotary instruction execution method, system and execution unit |
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| CN110928832A (en) * | 2019-10-09 | 2020-03-27 | 中山大学 | Asynchronous pipeline processor circuit, device and data processing method |
| CN110806899A (en) * | 2019-11-01 | 2020-02-18 | 西安微电子技术研究所 | Assembly line tight coupling accelerator interface structure based on instruction extension |
| CN111078294B (en) * | 2019-11-22 | 2022-08-19 | 苏州浪潮智能科技有限公司 | Instruction processing method and device of processor and storage medium |
| CN111078294A (en) * | 2019-11-22 | 2020-04-28 | 苏州浪潮智能科技有限公司 | Instruction processing method and device of processor and storage medium |
| CN111159094A (en) * | 2019-12-05 | 2020-05-15 | 天津芯海创科技有限公司 | RISC-V based near data stream type calculation acceleration array |
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| CN112308759A (en) * | 2020-11-05 | 2021-02-02 | 山东云海国创云计算装备产业创新中心有限公司 | Mean value filtering method and device |
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| CN113407239A (en) * | 2021-06-09 | 2021-09-17 | 中山大学 | Assembly line processor based on asynchronous single track |
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| CN113779755B (en) * | 2021-08-05 | 2023-11-17 | 中科联芯(广州)科技有限公司 | Design method of silicon-based multispectral integrated circuit chip and integrated circuit chip |
| CN113779755A (en) * | 2021-08-05 | 2021-12-10 | 中科联芯(广州)科技有限公司 | Design method of silicon-based multispectral integrated circuit chip and integrated circuit chip |
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| CN113656074A (en) * | 2021-10-18 | 2021-11-16 | 深圳市智想科技有限公司 | RISC architecture processor and parallel pipeline structure design method thereof |
| CN113946368A (en) * | 2021-10-29 | 2022-01-18 | 西安微电子技术研究所 | Three-level pipeline architecture based on RISC-V instruction set, processor and data processing method |
| CN113946368B (en) * | 2021-10-29 | 2024-04-30 | 西安微电子技术研究所 | Three-stage pipeline architecture, processor and data processing method based on RISC-V instruction set |
| CN114721724A (en) * | 2022-03-07 | 2022-07-08 | 电子科技大学 | RISC-V instruction set-based six-stage pipeline processor |
| CN115878187A (en) * | 2023-01-16 | 2023-03-31 | 北京微核芯科技有限公司 | Processor instruction processing apparatus and method supporting compressed instructions |
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