CN102436781A - Microprocessor order split device based on implicit relevance and implicit bypass - Google Patents
Microprocessor order split device based on implicit relevance and implicit bypass Download PDFInfo
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- CN102436781A CN102436781A CN2011103468109A CN201110346810A CN102436781A CN 102436781 A CN102436781 A CN 102436781A CN 2011103468109 A CN2011103468109 A CN 2011103468109A CN 201110346810 A CN201110346810 A CN 201110346810A CN 102436781 A CN102436781 A CN 102436781A
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Abstract
The invention discloses a microprocessor order split device based on implicit relevance and an implicit bypass, comprising a detecting and splitting unit required to split order, which is used for judging whether the coded order entering the microprocessor order split device is the order required to split and splitting the order required to split into two atom orders; a split order processing unit, which is used for receiving at least two atom orders split from the order required to split by the split unit required to split order, structuring the implicit relevance for these atom orders and outputting the processed atom order; the other processing unit, which is used for receiving the order judged to not require to split by the detecting and processing unit of the order required to split and the atom order finally generated by the split order processing unit, finishing the order subsequent process and executing work. When the complex operation order with front and rear data relevance is split, the invention can effectively reduce the occupied hardware resource, expand the range of the order to be split and improve the performance of the processor.
Description
Technical field:
The present invention relates to the flush bonding processor field, especially a kind of microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass.
Background technology:
Deepening continuously and enlarging of the development embedded microprocessor application of modern integrated circuits technology makes storer become the key factor of restriction microprocessor cost and power consumption.Under specific hardware resource prerequisite, how to strengthen the instruction set function, improve code density and instruction execution efficient, be the problem that a lot of processor designers must face.A lot of flush bonding processors are to application-specific, and removable complex operations that is divided into several atomic operations is instructed when carrying out through in instruction set, introducing several, has proposed the solution of this problem.Consider the implementation complexity that processor hardware resource, power consumption and instruction split; General processor only splits the complex operations instruction that good concurrency is arranged between each operation; As from the territory, connected storage to general working storage loading data, perhaps the data storage of a plurality of general working storages to storer.
The complex operations of data dependence instruction before and after fractionation has should solve the data dependence that splits between the atomic instructions of back, eliminates this correlativity again as early as possible, needs big hardware resource support, and its realization has big difficulty.Thereby this has limited through splitting the complex operations instruction and has improved the ability that processor code density strengthens the instruction set function.
With a 32-bit microprocessor relation between processor hardware resource and the instruction set function is described.This processor always has 16 general working storage R0-R15; Performance elements such as arithmetic operator unit and memory read r/w cell are arranged; Wherein each cycle of arithmetic operator unit can only accomplish once add, subtract, atomic operation such as multiplication and division, displacement; The memory read r/w cell weekly the phase can only accomplish primary memory and read or write atomic operation, each performance element has 2 working storage read ports.Under such hardware designs, deposit the data of working storage Rk with working storage Ri and Rj data if desired and be the storage area of address, then need two instructions: earlier with " ADD RiRj " instruction Ri and the addition of Rj data, the result deposits among the Ri; Accomplish final operation with store Rk Ri again; In like manner, jump to two code zones that the register data sum is indicated if desired, also need two instruction cooperations to accomplish.
Summary of the invention
For the complex operations instruction that overcomes existing microprocessor data dependence before and after fractionation has the time need consume great amount of hardware resources, limited detachable instruction scope, limited the deficiency of processor performance, the present invention provides a kind of scope that takies hardware resource, enlarges its detachable instruction, microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass that promotes processor performance of before and after fractionation has, effectively reducing during the complex operations instruction of data dependence.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass, said microprocessor instruction detachment device comprises:
Need to split command detection and split cells, in order to judging whether the translation instruction that gets into this microprocessor instruction detachment device is to need to split instruction, and needs split to instruct and be split as at least two atomic instructions;
Split instruction process unit; Being connected in needs to split instruction fractionation and detecting unit output; Need split at least two atomic instructions that the instruction split cells will need the fractionation instruction to split in order to receive from this; To these atomic instructions structure implicit expression correlations; And introduce the implicit expression bypass technology, atomic instructions has been handled in output;
Other processing units; Be connected in the output terminal that needs to split the output terminal of command detection and split cells and split instruction process unit; Needed to split the atomic instructions that command detection and processing unit are judged as the instruction that need not to split and have split the final generation of instruction process unit in order to reception, and accomplished instruction subsequent treatment, execution work.
Further, this atomic instructions that has split the final generation of instruction process unit is handled according to stereotyped command in this microprocessor.
Preferably, the said need in fractionation command detection and the split cells safeguarded with splitting two states by idle, wherein, need not to split and instructs when getting into this command detection and split cells, and this command detection and split cells are in Idle state, do not have the action of fractionation generation; When need splitting instruction and getting into this command detection with detachment device, this command detection and split cells entering fractionation attitude are returned Idle state after instruction split into some atomic instructions.
Further again, the said instruction process unit that split comprises:
Structure implicit expression correlation module, in order to indication with safeguard and should need to split correlativity between several atomic instructions of the split one-tenth of instruction, the correlativity maintenance module is mutually independently in this structure implicit expression correlation module and this microprocessor;
The implicit expression bypass module is responsible for the bypass of data, carries out bypass in order to will need to split several atomic instructions execution results with data dependence of the split one-tenth of instruction, and explicit bypass module is independent mutually in this implicit expression bypass module and this microprocessor.
Further; This need split instruction and be split as at least two and split atomic instructions; Wherein having two of data dependence has split atomic instructions and is defined as first and has split instruction and second and split instruction; Second has split director data is relevant to first and has split instruction; The implicit expression bypass module has split instruction instruction sequence number in the particular module in microprocessor to first and has handled, and makes second to split instruction bypass to the first and split after the director data, and first has split instruction just can carry out end.
The technical conceive of this device is: microprocessor instruction set is the direct interphase of microprocessor hardware and software; The user accomplishes the related work amount through microprocessor instruction notice microprocessor hardware, and microprocessor instruction set is one of effective tool that improves microprocessor efficient.The widely used risc instruction set of microprocessor though can be suitable for adopting the architecture of streamline, super pipeline and superscale technology very effectively, improves a lot to processor performance at present.Yet because the instruction of every of risc instruction set realizes that function is limited, during programming, the user need be subdivided into each RISC with workload and instruct accessible atomic operation.In some particular application, like the read-write of storer mass data, frequent redirect etc., the user need reuse several functionally similar instructions.These have all increased the code operation amount of writing undoubtedly.Therefore, most of processors have been introduced some complex operations instructions, and reduction instruction is write, and improves instruction and carries out efficient and code density.For at the economize on hardware cost with do not influence and increase these complex operations instructions under the prerequisite of performance; Most of microprocessors have all been introduced instruction and have been split mechanism; Can only split the complex operations instruction with higher concurrency yet these instructions split mechanism, intractable has the complex operations instruction of data dependence.
In order to enlarge the scope of detachable instruction; This microprocessor has been introduced a kind of microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass technology; In the microprocessor all the translation instruction need that all will deliver to this microprocessor instruction detachment device split command detection and split cells; Needing to split command detection and split cells splits detecting the instruction that needs to split; And will split good instruction and deliver to and split instruction process unit, one splits instruction process unit makes up implicit expression correlativity and implicit expression bypass to these instructions, finally generates several and can supply this microprocessor atomic instructions of individual processing one by one.
Beneficial effect of the present invention mainly shows: enlarged detachable instruction type of microprocessor and scope, reduced microprocessor programming complicacy, effectively improved code density, the economize on hardware resource.
Description of drawings
Fig. 1 is the moving direction of the microprocessor instruction of introducing the microprocessor instruction detachment device.
Fig. 2 is a microprocessor instruction decoding information after the introducing microprocessor instruction detachment device.
Fig. 3 is microprocessor instruction detachment device instruction disassembled form machine.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Fig. 3; A kind of microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass; The wall scroll complex operations instruction of deciphering that can't disposable individual processing with microprocessor splits into the atomic instructions that several these microprocessors can be handled one by one, and this microprocessor instruction detachment device comprises:
Need to split command detection and split cells; In order to judge whether the translation instruction that gets into this microprocessor instruction detachment device is to need to split instruction; And need split the instruction be split as at least two atomic instructions, be this input end based on the microprocessor instruction detachment device of implicit expression correlativity and implicit expression bypass technology; And
Split instruction process unit; Being connected in needs to split instruction fractionation and detecting unit output; Need split at least two atomic instructions that the instruction split cells will need the fractionation instruction to split in order to receive from this; To these atomic instructions structure implicit expression correlations; And introduce the implicit expression bypass technology, atomic instructions has been handled in output.
Other processing units; Be connected in the output terminal that needs to split the output terminal of command detection and split cells and split instruction process unit; Needed to split the atomic instructions that command detection and processing unit are judged as the instruction that need not to split and have split the final generation of instruction process unit in order to reception, and accomplished instruction subsequent treatment, execution work.
Reference is shown in Figure 1, and the flow direction of this microprocessor instruction of the instruction process detachment device that need not to split is shown in black arrow in the way, and the flow direction that needs to split this device of instruction process is shown in red arrow in the way.Microprocessor is got the instruction got the unit, location after decoding; All will be by needing to split command detection and split cells in this device; Need fractionation command detection and split cells whether to need to split: to split if need not by this instruction of fractionation flag bit decision of reading command decoding information; Then instruct and directly delivered to other processing units, accomplish instruction and carry out; Split if desired; Need to split command detection and split cells by detecting instruction operation code; Determine this instruction need be split as the instruction of several what types; According to these instruction fractionation information, need to split command detection and split cells state machine and split by accomplishing instruction in Idle state and the switching that splits attitude.
The atomic instructions that fractionation is good is sent to and splits instruction process unit, adds correlation information; Suppose that first has split instruction A and second and split instruction B and split instruction, second has split instruction B data is relevant to first and has split instruction A.Then split instruction process unit, second split the instruction B operational code in, add specific implicit expression correlation information, the indication second split the instruction B be relevant to first split the instruction A.For accelerate first split instruction A, B execution speed; Prevent simultaneously first split the instruction A cross early retirement cause second split the instruction B can't obtain its data; The implicit expression bypass technology; In advance with first split instruction A data give second and split instruction B, have only second to split instruction B and obtain data after, just allowing first, to have split instruction A retired.After these processing, the atomic instructions that has split is sent to other processing units, accomplishes instruction according to general instruction and carries out.These atomic instructions are all carried out end, represent that then this complex operations instruction execution finishes.
With reference to shown in Figure 2, during instruction decode, in the decoding information of instruction, added the split position, whether need to split in order to characterize this instruction.Instruction type that splits into and number of instructions are then decided by instruction operation code.
With reference to shown in Figure 3, need not split instruction and get into when needing to split the instruction split cells, the state machine of this unit is in Idle state, characterizes minimum power consumption expense; When need fractionation instruction entering needed fractionation to instruct split cells, its state machine jumped to the fractionation attitude, and the atomic instructions number that each machine cycle splits out is determined by the microprocessor hardware resource.If this microprocessor is a single transmit, then the phase splits out an atomic instructions weekly; If send out or pilosity is penetrated for two, then split out two or many atomic instructions.After splitting end, state machine returns Idle state.
After 32-bit microprocessor mentioned above is introduced the microprocessor instruction detachment device, analyze its instruction set and code density once more.At this moment, in instruction set, increase earlier corresponding complex operations instruction storea Ri, Rj, Rk is used for depositing the data of working storage Rk with working storage Ri and Rj data and being the storage area of address.When processor was carried out, this instruction was split as " ADD RiRj " and " store Ri, Rk ", and ADD Ri Rj is in order to carrying out addition with the value of Ri and Rj, and the result is deposited among the Ri; Store Ri, Rk arrives the indicated storage address of Ri with the data storage among the Rk.In this way, realized the function of two atomic instructions having increased code density with the instruction of complex operations; And only need once decipher, practiced thrift decoding time.Not only reduced cost, also improved instruction simultaneously and carried out efficient.
Claims (5)
1. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass is characterized in that, said microprocessor instruction detachment device comprises:
Need to split command detection and split cells, in order to judging whether the translation instruction that gets into this microprocessor instruction detachment device is to need to split instruction, and needs split to instruct and be split as at least two atomic instructions;
Split instruction process unit; Being connected in needs to split instruction fractionation and detecting unit output; Need split at least two atomic instructions that the instruction split cells will need the fractionation instruction to split in order to receive from this; To these atomic instructions structure implicit expression correlations; And introduce the implicit expression bypass technology, atomic instructions has been handled in output;
Other processing units; Be connected in the output terminal that needs to split the output terminal of command detection and split cells and split instruction process unit; Needed to split the atomic instructions that command detection and processing unit are judged as the instruction that need not to split and have split the final generation of instruction process unit in order to reception, and accomplished instruction subsequent treatment, execution work.
2. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 1 is characterized in that, this has split the final atomic instructions that generates of instruction process unit and in this microprocessor, has handled according to stereotyped command.
3. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 1 and 2; It is characterized in that said the need in fractionation command detection and the split cells safeguarded with the fractionation two states by idle; Wherein, When need not to split instruction this command detection of entering and split cells, this command detection and split cells are in Idle state, do not have the action of fractionation and take place; When need splitting instruction and getting into this command detection with detachment device, this command detection and split cells entering fractionation attitude are returned Idle state after instruction split into some atomic instructions.
4. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 1 and 2 is characterized in that, the said instruction process unit that split comprises:
Structure implicit expression correlation module, in order to indication with safeguard and should need to split correlativity between several atomic instructions of the split one-tenth of instruction, the correlativity maintenance module is mutually independently in this structure implicit expression correlation module and this microprocessor;
The implicit expression bypass module is responsible for the bypass of data, carries out bypass in order to will need to split several atomic instructions execution results with data dependence of the split one-tenth of instruction, and explicit bypass module is independent mutually in this implicit expression bypass module and this microprocessor.
5. the microprocessor instruction detachment device based on implicit expression correlativity and implicit expression bypass according to claim 4; It is characterized in that; This need split instruction and be split as at least two and split atomic instructions; Wherein have two of data dependence and split atomic instructions and be defined as first and split instruction and second and split instruction, second has split director data is relevant to first and has split instruction, and the implicit expression bypass module has split instruction instruction sequence number in the particular module in microprocessor to first and handled; Make second to split instruction bypass to the first and split after the director data, first has split instruction just can carry out end.
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| CN107430508A (en) * | 2015-03-27 | 2017-12-01 | 英特尔公司 | For providing instruction and the logic of atoms range operation |
| CN111090465A (en) * | 2019-12-19 | 2020-05-01 | 四川长虹电器股份有限公司 | Decoding system and decoding method for RV32IC instruction set |
| CN114401298A (en) * | 2021-12-16 | 2022-04-26 | 荣耀终端有限公司 | Data transmission method, equipment and system |
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| CN114401298A (en) * | 2021-12-16 | 2022-04-26 | 荣耀终端有限公司 | Data transmission method, equipment and system |
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| CN102436781B (en) | 2014-02-12 |
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