CN102426860A - Method for detecting disturbance of programming operation to adjacent memory cells - Google Patents

Abstract

The invention provides a method for detecting interference of programming operation on adjacent memory cells, which comprises the steps of simultaneously gating a plurality of continuous bit lines while programming operation is carried out on cells of a memory array, measuring the voltage of two continuous bit lines adjacent to the bit line of a programmed memory cell, calculating the leakage current flowing through the memory cells connected with the two continuous bit lines, and detecting whether original information in the memory cells adjacent to the programmed memory cell is interfered by the leakage current by judging whether the leakage current is larger than a preset current value or not. In addition, if voltages of two consecutive bit lines adjacent to the bit line of the programmed memory cell to which the low voltage is applied are measured, it is also possible to detect whether the programming speed of the programmed memory cell is disturbed by the leakage current.

Description

Method for detecting disturbance of programming operation to adjacent memory cells

technical field

The invention relates to the field of memory information storage, in particular to a method for detecting the interference of memory array programming operations on adjacent memory cells. the

Background technique

The core of the entire flash memory is an array of flash storage units. See Figure 1. The flash storage unit is an example of an ordinary MOS tube. Each storage unit (cell) has three ports, one of which is a control port, which is equivalent to the common MOS tube. The gate, and the other two ports are equivalent to the source and drain of ordinary MOS transistors. The control ports of the memory cells are connected to the word line, and the control ports of the memory cells in the same row of the array are connected to the same word line WL1. The sources and drains of memory cells in the same row in the memory array are connected end to end in sequence, and the sources and drains of two adjacent memory cells are connected to a bit line. Usually when memory cells are programmed (including writing, erasing, etc.), take memory cell cell2 programming in Fig. Two bit lines BLa and BLa+1 connected to the source and drain of the unit cell2, the programming current supply device applies the low voltage required for programming to the bit line BLa, and the programming voltage supply device applies the programming required for the bit line BLa+1 The high voltage of the memory cell cell2 has a potential difference. Under the action of the programming current I, due to the channel hot electron effect (CHE) of the flash memory cell, charges are injected into the storage layer of the memory cell cell2 to complete the programming operation of the memory cell. the

At present, when programming the memory cell cell2, only the programming of this memory cell is concerned, regardless of whether the surrounding memory cells (such as cell0, cell1, cell3, cell4) are affected during the programming operation. During several cycles before the program operation of the memory cell cell1, the bit line BLa-1 adjacent to the bit line BLa to which the memory cell cell2 applies a low voltage may have been applied with a signal, and there will be residual charges left on the bit line BLa -1 on. When performing the programming operation of the memory cell cell2, due to the low voltage applied to the bit line BLa, a potential difference is generated across the memory cell cell1, thereby forming a leakage current flowing through the memory cell cell1, and the word line WL1 is placed at a high level during the programming process to enable When the memory cell is turned on, the potential of the word line WL1 is relatively high during the programming operation. When the leakage current is large, the charge will enter the storage layer of the memory cell cell1, which will interfere with the original storage information of the memory cell cell1 and may make the memory cell cell1 The original stored information is overwritten. the

Contents of the invention

The invention solves the problem of detecting whether the programming operation of the memory array causes interference to adjacent cells. the

In order to achieve the above object, the present invention provides a method for detecting the interference of memory array programming operations on adjacent memory cells, including:

Gate the word line of the programmed memory cell; gate a plurality of consecutive bit lines of the memory array, wherein a first programming voltage is applied to one bit line of the programmed memory cell, and a second programming voltage is applied to the other bit line voltage, the second programming voltage is higher than the first programming voltage; each bit line is only applied once during the detection process;

measuring the voltage between two consecutive bit lines adjacent to the bit line of the programmed memory cell;

calculating the leakage current flowing through the memory cells connected by the two consecutive bit lines according to the voltage between the two consecutive bit lines;

Judging whether the leakage current is greater than a preset current value, if yes, the information stored in the storage unit adjacent to the programmed storage unit is disturbed by the leakage current; if not, the storage unit adjacent to the programmed storage unit The stored information is not disturbed by the leakage current. the

Compared with the prior art, the present invention has the following advantages:

The present invention also provides a method for detecting the interference of the programming operation of the memory array on the adjacent memory cells. Simultaneously, a plurality of consecutive bit lines are selected, and while the memory cells are being programmed, two consecutive bit lines adjacent to the bit lines of the programmed memory cells are measured. Line voltage, calculate the leakage current flowing through the memory cells connected to the two consecutive bit lines, and by judging whether the leakage current is greater than the preset current value, the original information in the memory cells adjacent to the programmed memory cells can be detected Whether it is disturbed by leakage current. the

In addition, if the voltages of two consecutive bit lines adjacent to the bit line to which a low voltage is applied to the programmed memory cell are measured, the leakage current flowing through the memory cell connected to the two consecutive bit lines is calculated, and by judging the leakage current The magnitude of the current can detect whether the programming speed and accuracy of the programmed memory cell are disturbed by the leakage current. the

Description of drawings

The above and other objects, features and advantages of the present invention will be more clearly illustrated by the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intentionally scaled according to the actual size, and the emphasis is on illustrating the gist of the present invention. the

Fig. 1 is a schematic diagram of device connection during programming operation of memory array unit;

Fig. 2 is the flow chart of the method for detecting memory array programming operation of the present invention interferes with adjacent memory cells;

Fig. 3 is a schematic diagram of device connection during detection by the method of the first embodiment of the present invention;

Fig. 4 is the connection schematic diagram that the method of the first embodiment of the present invention has voltage follower;

Fig. 5 is the schematic circuit diagram of the voltage following device of the first embodiment;

Fig. 6 is the schematic diagram of high precision voltage testing device;

Fig. 7 is a schematic diagram of device connection during detection by the method of the first embodiment of the present invention;

FIG. 8 is a schematic diagram of the connection of the bit line gating device of the method for detecting the interference of the programming operation of the memory array on the adjacent memory cells of the present invention. the

Detailed ways

As described in the background art, when a conventional memory array performs programming operations, no signal is applied to the bit lines adjacent to the bit lines to which the low-voltage signal or the high-voltage signal is applied. During several programming cycles before the current programming operation, the Because the bit line adjacent to the bit line of the programmed memory cell has been applied with a programming signal, there will be residual positive charges. There is a potential difference between the electrode and the drain to generate a leakage current. When programming, the potential of the word line is high. When the leakage current is large, the charge will enter the storage layer of the memory cell, and the original memory cell adjacent to the programmed memory cell Stored information interferes. the

In order to detect whether the stored information in the adjacent memory cells sharing a word line adjacent to the programmed memory cell is affected by the programming operation during the programming operation of the memory cells of the memory array, the present invention proposes a method for detecting the interference of the programming operation on the adjacent memory cells The method, the technical solution is to simultaneously measure the voltage between two consecutive bit lines adjacent to the bit line of the programmed memory cell when programming the programmed memory cell, and calculate the voltage flowing through the two consecutive bit lines connected The leakage current of the memory cell, and judging whether the leakage current will interfere with the information stored in the memory cell adjacent to the programmed memory cell. The scheme of the present invention can detect whether the programming operation will interfere with the storage unit adjacent to the programmed storage unit by measuring the leakage current flowing through the storage unit adjacent to the programmed storage unit while the programming operation is in progress. the

The detection flow chart of the method for detecting the interference of the programming operation on the adjacent storage unit disclosed by the present invention is shown in Figure 2, including:

Step S1, gating the word line of the programmed memory cell; gating multiple consecutive bit lines of the memory array, wherein the first programming voltage is applied to one bit line of the programmed memory cell, and the other bit line is applied A second programming voltage, the second programming voltage is higher than the first programming voltage; each bit line is only applied with a voltage once during a programming process;

Step S2, measuring the voltage between two consecutive bit lines adjacent to the bit line of the programmed memory cell;

Step S3, calculating the leakage current flowing through the memory cells connected to the two consecutive bit lines according to the voltage between the two consecutive bit lines;

Step S4, judging whether the leakage current is greater than a preset current value, if yes, the programming operation interferes with the information stored in the memory unit adjacent to the programmed memory unit by the leakage current; The information stored in the storage unit adjacent to the programmed storage unit is not disturbed by the leakage current. the

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. the

In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below. the

Secondly, the present invention is described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention. Describe the method of the present invention in detail below by specific embodiment:

Embodiment one

This embodiment provides a method for detecting the interference of the programming operation on adjacent memory cells, detecting the voltage between two consecutive bit lines adjacent to the bit line to which the programmed memory cell applies a low voltage, and performing a programming operation on the memory cell Refer to Figure 3 for a schematic diagram of detecting the interference of a programming operation on an adjacent memory cell. Taking the programming operation of the memory cell Celln+2 as an example, the word line gating control signal is used to gating the word line WL of the memory cell Celln+2 through the word line gating device. , the bit line gating control signal simultaneously gating at least four consecutive bit lines BLn-1, BLn, BLn+1 and BLn+2 of the memory array through the bit line gating device, each bit line is only applied in a programming operation Primary voltage, the programming current providing device applies the first programming voltage to the bit line BLn+1, and the programming voltage providing device applies the second programming voltage to the bit line BLn+2, wherein the second programming voltage is greater than the first programming voltage; The bit lines BLn-1 and BLn adjacent to BLn+1 are connected to the voltage testing device through the bit line gating device, and the voltage between the bit lines BLn-1 and BLn is measured by the voltage testing device. Wherein, the programming current supply device and the programming voltage supply device are commonly used devices when programming memory cells. the

If there is residual charge in the bit lines BLn-1 and BLn, then when the memory cell Celln+2 is programmed, the bit line BLn+1 is momentarily placed at the first programming voltage, because the word line WL is a high potential, and the memory cell Celln +2 The adjacent memory cells Celln and Celln+1 are turned on, and there will be a leakage current flowing through their channels. When the leakage current exceeds a preset current value, electrons will enter the floating gates of the memory cells Celln and Celln+1, The original storage information of the storage units Celln and Celln+1 is disturbed. The method of measuring the magnitude of the leakage current is to measure the voltage value _U1 between the bit line BLn-1 and BLn at the moment of programming operation by the voltage test device. Information related. The leakage current Ileak1 flowing on the storage unit Celln is calculated according to the following formula:

Ileak1 = U ₁ /R1

Calculate the magnitude of the leakage current Ileak1, compare the leakage current with the preset current value, if the leakage current is greater than the preset current, the information of the storage unit Celln and Celln+1 may be rewritten due to the interference of the leakage current; if the leakage current is less than the preset value If the current is set, the information of the storage unit will not be disturbed by the leakage current. the

In the method for detecting interference of programming operation on adjacent memory cells in this embodiment, at least five bit lines in the memory array may be selected, and at least one bit line adjacent to the bit line to which the second programming voltage is applied is applied. The same voltage as the second programming voltage. Referring to Fig. 4, during the programming operation, the bit line gating control signal also gating the bit line BLn+3 adjacent to the bit line BLn+2 through the bit line gating device, and the bit line BLn+3 is applied to the bit line BLn+ 2 equal to the second programming voltage, the voltage applied to the bit line BLn+3 is provided by the voltage follower. The function of the voltage follower is to follow the voltage of the end of the programmed memory cell to which the second programming voltage is applied, and make the voltage of the bit line connected to it reach the same value. When programming the memory cell Celln+2, the voltages at both ends of the memory cell Celln+3 are equal, so no leakage current will be generated, and the programming accuracy of the memory cell Celln+2 can be guaranteed. the

An operational amplifier may be included in the voltage follower, as shown in FIG. 5 , the output terminal 12 of the operational amplifier is connected to the inverting input terminal 11, so that the voltage of the output terminal 12 of the amplifier is consistent with the voltage of the non-inverting input terminal 10. Referring to Fig. 4, the input terminal 10 of the operational amplifier is the input terminal of the voltage follower device, which is connected to the voltage output terminal of the programming voltage supply device, and the voltage output by the output terminal 12 of the operational amplifier is applied to the bit line BLn+ through the bit line gating device 3 on. During the program operation, the voltage follower can charge the bit line BLn+3 connected to it synchronously with the bit line BLn+2. the

In addition, the voltage follower circuit in this embodiment may also include a control terminal. Referring to FIG. 5, the voltage follower circuit operates when the control terminal 13 is at a high level, and the output terminal 12 outputs a voltage equal to the non-inverting input terminal 10; the control terminal 13 is at a low level. level, the voltage follower circuit does not work, and the output voltage of the output terminal 12 is zero. the

The voltage testing device in the present embodiment can adopt general voltage testing equipment, also can adopt high-precision voltage testing device, its structure sees Fig. 6, comprises preamplifier circuit, high-pass filter circuit, low-pass filter circuit, main amplifier circuit and 50Hz notch circuit, wherein the preamplifier circuit is used to amplify the voltage signal collected by the sensor of the high-precision test device in a differential mode to avoid signal distortion, and can be composed of a three-stage operational amplifier with automatic offset compensation (for example, it can be used LM725CN and other independent components); high-pass and low-pass filter circuits are used to reduce test noise interference, which can be composed of a second-order voltage-controlled source circuit; the main amplifier circuit and 50Hz trap circuit are used to generate and match the input of the A/D converter Amplitude. After the voltage signal collected by the sensor is differential mode, the high-pass and low-pass filter circuits reduce the test noise interference, and finally the main amplifier circuit and 50Hz notch circuit generate a signal amplitude that matches the input of the A/D converter, with high precision The voltage testing device can test the voltage value sensitively and accurately. the

At the same time, referring to Figure 3, when the memory cell Celln+2 is programmed, if there is a leakage current in the adjacent memory cells Celln, Celln+1, etc., there will be charges continuously added to the bit line BLn+2 until the remaining After all the charges are leaked, the bit line BLn+1 can reach the low voltage value U ₀ satisfying the program operation, and the result of the read operation at this time can be valid. Therefore, the existence of the leakage current may interfere with the speed of the programming operation, and may also affect the accuracy of the programming. The method for detecting the interference of the programming operation on adjacent memory cells in this embodiment can also detect whether the speed and accuracy of the programming operation are disturbed by the leakage current by judging the magnitude of the leakage current.

Embodiment two:

This embodiment provides a method for detecting the interference of programming operations on adjacent memory cells, by detecting the voltage between two consecutive bit lines adjacent to the bit line to which a high voltage is applied to the programmed memory cell, when performing a programming operation on the memory cell Refer to FIG. 7 for a schematic diagram of detecting the interference of a programming operation on an adjacent storage unit. Taking the programming operation of the storage unit Cellm+1 as an example, the word line gating control signal gates the word line WL of the storage unit Cellm+1 through the word line gating device. The bit line gating control signal simultaneously gating at least four consecutive bit lines BLm, BLm+1, BLm+2 and BLm+3 of the memory array through the bit line gating device, and the programming current supply device applies the first bit line BLm to the bit line BLm. programming voltage, the programming voltage providing device applies a second programming voltage to the bit line BLm+1, and the bit lines BLm+2 and BLm+3 adjacent to the bit line BLm+1 are connected to the voltage testing device through the bit line gating device, The voltage between the bit lines BLm+2 and BLm+3 is measured by a voltage test device. Wherein, the programming current supply device and the programming voltage supply device are commonly used devices when programming memory cells, and the voltage testing device can also use the high-precision testing device in the first embodiment. the

When programming the memory cell Cellm+1, the bit line BLm+1 is instantly placed at the second programming voltage U ₂ , since the word line WL is at a high potential, the memory cells Cellm+2 and Cellm+ adjacent to the memory cell Cellm+1 3 conduction, no voltage is applied to the bit lines BLm+2 and BLm+3, there is a potential difference between the two ends of the memory cells Cellm+2 and Cellm+3, and a leakage current Ileak2 will flow through the memory cells Cellm+2 and Cellm+3 channel, when the leakage current exceeds the set current value, electrons will enter the floating gates of the memory cells Cellm+2 and Cellm+3, which will interfere with the original stored information of the memory cells Cellm+2 and Cellm+3. The method for measuring the magnitude of the leakage current is to measure the voltage value U ₂ between the instantaneous bit line BLm+2 and BLm+3 during the programming operation by a voltage testing device, the channel resistance of the memory cell Cellm+3 is R2, and the memory cell The channel resistance is related to the information stored on it. The leakage current Ileak2 flowing on the storage unit Cellm+3 is calculated according to the following formula:

Ileak2 = U ₂ /R2

Calculate the magnitude of the leakage current Ileak2, compare the leakage current with the preset current value, if the leakage current is greater than the preset current, the information of the storage cells Cellm+2 and Cellm+3 may be rewritten due to the interference of the leakage current; if the leakage current is less than the preset value The preset current, the storage unit information will not be disturbed by the leakage current. the

At the same time, the programming information when programming the memory cell Cellm+1 is determined by the programming current I on the bit line BLm+1, the existence of leakage current Ileak2 during programming may affect the accuracy of the programming current I, so the detection of this embodiment In the method that programming operation interferes with adjacent memory cells, the accuracy of programming operation can also be detected by judging the size of leakage current. the

In the method for detecting the interference of the programming operation on adjacent memory cells in this embodiment, the multiple consecutive bit lines of the memory array are selected by the bit line gating device according to the gating control signal. The bit line gating device has various structures. The bit line gating device of the embodiment may adopt a gating structure in which one gating control signal is used to gate one bit line. Referring to FIG. 8, the bit line gating device includes a plurality of MOS transistors M1, M2, M3..., when the control signal is at a high level, the source and drain of the MOS transistors are turned on, and the bit line gating control signal S1 gating MOS transistor M1, the programming current providing device applies the first programming voltage to the bit line BLm of the memory array through the MOS transistor M1; The second programming voltage is applied to the bit line BLm+1; the bit line gating control signal S3 selects the MOS transistor M3, and the bit line BLm+2 of the storage array is connected to one end of the voltage testing device through the MOS transistor M3; the bit line gating control signal S4 The MOS transistor M4 is selected, and the bit line BLm+3 of the storage array is connected to the other end of the voltage testing device through the MOS transistor M4. the

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. the

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention. the

Claims (9)

1. A method for detecting programming operation interference to adjacent memory cells, characterized in that, comprising: Gate the word line of the programmed memory cell; gate a plurality of consecutive bit lines of the memory array, wherein a first programming voltage is applied to one bit line of the programmed memory cell, and a second programming voltage is applied to the other bit line Voltage, the second programming voltage is higher than the first programming voltage; each bit line can only apply a voltage once during the detection process; measuring the voltage between two consecutive bit lines adjacent to the bit line of the programmed memory cell; calculating the leakage current flowing through the memory cells connected by the two consecutive bit lines according to the voltage between the two consecutive bit lines; Judging whether the leakage current is greater than a preset current value, if yes, the information stored in the storage unit adjacent to the programmed storage unit is disturbed by the leakage current; if not, the storage unit adjacent to the programmed storage unit The stored information is not disturbed by the leakage current. 2. The method according to claim 1, wherein the method for detecting the interference of the programming operation on the adjacent memory cell is characterized in that, measuring the distance between two consecutive bit lines adjacent to the bit line applying the first programming voltage to the programmed memory cell voltage. 3. The method according to claim 2, characterized in that at least five consecutive bit lines of the memory array are gated, and among the at least five continuous bit lines, the At least one continuous bit line adjacent to the bit line to which the second programming voltage is applied for programming the memory cell is applied with a voltage equal to the second programming voltage. 4. The method according to claim 3, characterized in that the at least one continuous bit line adjacent to the bit line to which the high voltage is applied to the programmed memory cell is applied with The voltage equal to the second programming voltage is: The second programming voltage is input from the non-inverting input terminal of the operational amplifier, and after the operation of the operational amplifier, a voltage equal to the second programming voltage is applied to the bit line connected to the output terminal of the operational amplifier, and the inverting input of the operational amplifier terminal is connected to the output terminal. 5. The method according to claim 1, wherein the method for detecting interference of programming operation to adjacent memory cells is characterized in that, measuring the distance between two consecutive bit lines adjacent to the bit line applying the second programming voltage to the programmed memory cell voltage. 6. The method according to any one of claims 1 to 5, wherein the method for detecting interference of a programming operation to an adjacent memory cell is characterized in that the measurement of two consecutive bit lines adjacent to the bit line of the programmed memory cell Voltages between include: After collecting the voltage between the two consecutive bit lines, perform the following steps in sequence; The voltage between the two consecutive bit lines is amplified in a differential mode through a preamplifier circuit to obtain an amplified voltage signal; The amplified voltage signal value is removed through a high-pass filter circuit and a low-pass filter circuit to remove noise interference; The amplified voltage signal after the noise interference is removed passes through the main amplifier circuit and the 50Hz trap circuit to convert the amplitude. 7. The method according to any one of claims 1 to 5, characterized in that the plurality of continuous bit lines of the gate memory array are: A plurality of gating control signals control a plurality of MOS transistors to be turned on, wherein one gating control signal controls the source and drain of a MOS transistor to be turned on, so that the bit line connected to the source of a MOS transistor is applied to the drain. The first programming voltage or the second programming voltage of the polarity. 8. The method according to any one of claims 1 to 5, characterized in that the programming current supply device applies a first programming voltage to a bit line of the programmed memory cell . 9. The method according to any one of claims 1 to 5, characterized in that the programming voltage supply device applies a second programming voltage to another bit line of the programmed memory cell. Voltage.

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