CN102426860A - Method for detecting interference of programming operation to adjacent memory cell - Google Patents
Method for detecting interference of programming operation to adjacent memory cell Download PDFInfo
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Abstract
The invention provides a method for detecting interference of programming operation on adjacent memory cells, which comprises the steps of simultaneously gating a plurality of continuous bit lines while programming operation is carried out on cells of a memory array, measuring the voltage of two continuous bit lines adjacent to the bit line of a programmed memory cell, calculating the leakage current flowing through the memory cells connected with the two continuous bit lines, and detecting whether original information in the memory cells adjacent to the programmed memory cell is interfered by the leakage current by judging whether the leakage current is larger than a preset current value or not. In addition, if voltages of two consecutive bit lines adjacent to the bit line of the programmed memory cell to which the low voltage is applied are measured, it is also possible to detect whether the programming speed of the programmed memory cell is disturbed by the leakage current.
Description
Technical field
The present invention relates to the memorizer information field of storage, particularly relate to the operation of detection of stored array program closing on the method that storage unit is disturbed.
Background technology
The core of whole flash memories is the array that flash memory cell constitutes; Referring to Fig. 1; Flash memory cell is an example with common metal-oxide-semiconductor, and each storage unit (cell) has three ports, and one of them is a control port; The grid that is equivalent to common metal-oxide-semiconductor, all the other two ports are equivalent to the source electrode and the drain electrode of common metal-oxide-semiconductor.The control port of storage unit connects word line, and the control port with delegation's storage unit connects same word line WL1 in the array, and word line potential is just realized the unlatching of storage unit and shutoff.Source electrode with delegation's storage unit in the storage array joins end to end with drain electrode in order, and the source electrode of two adjacent storage unit and drain electrode are connected on the bit line.When usually storage unit being programmed (comprise and write, wipe etc.); So that storage unit cell2 among Fig. 1 is programmed for example; Word line WL1 level is that high back storage unit cell2 opens, two bit line BLa that bit line strobe unit gating storage unit cell2 source electrode is connected with drain electrode and BLa+1, and the program current generator applies the required low-voltage of programming for bit line BLa; The program voltage generator applies the required high voltage of programming for bit line BLa+1, and there is electric potential difference in storage unit cell2 two ends.Under the effect of program current I, because flash memory cell channel hot electron effect (CHE), electric charge injects the programming operation of the accumulation layer completion storage unit of storage unit cell2.
At present, when storage unit cell2 is carried out programming operation, only pay close attention to the programming situation of this storage unit, do not consider whether storage unit (for example cell0, cell1, cell3, cell4) is affected around it in this programming operation process.In some periodic processes before storage unit cell1 being carried out programming operation, the bit line BLa adjacent bit lines BLa-1 that applies low-voltage with storage unit cell2 possibly once be applied in signal, had residual charge and stayed on the bit line BLa-1.When carrying out storage unit cell2 programming operation; Because bit line BLa applies low-voltage, storage unit cell1 two ends produce electric potential difference, thereby form the Leakage Current of the storage unit cell1 that flows through; And word line WL1 places high level that storage unit is opened in programming process; During programming operation, the current potential of word line WL1 is higher, and Leakage Current will make electric charge get into the accumulation layer of storage unit cell1 when big; The original canned data of storage unit cell1 is produced interference, the original canned data of storage unit cell1 is rewritten.
Summary of the invention
Whether cause the problem of interference to closing on the unit when the invention solves the operation of detection of stored array program.
For achieving the above object, the invention provides a kind of detection of stored array program operation to closing on the method that storage unit is disturbed, comprising:
Gating is programmed the word line of storage unit; Many continuous bit lines of gating storage array wherein, apply first program voltage at a said bit line that is programmed storage unit, and another root bit line applies second program voltage, and said second program voltage is higher than said first program voltage; Every bit line only applies primary voltage in testing process;
Measure the voltage between two continuous bit lines adjacent with the said bit line that is programmed storage unit;
Calculate the Leakage Current of the storage unit that flows through said two continuous bit lines connections according to the voltage between said two continuous bit lines;
Whether judge said Leakage Current greater than the predetermined current value, if receive said Leakage Current and disturb with the said canned data that is programmed in the storage unit that storage unit closes on; If not, be programmed with said that canned data is not disturbed by said Leakage Current in the storage unit that storage unit closes on.
Compared with prior art, the present invention has advantage:
The present invention also provides the operation of detection of stored array program to closing on the method that storage unit is disturbed; Many continuous bit lines of while gating; In memory cells; Measure the voltage of the continuous two piece bit lines adjacent with the bit line that is programmed storage unit; Calculated flow is crossed the Leakage Current of the storage unit that said two continuous bit lines connect, and through whether judging said Leakage Current greater than the predetermined current value, can detect and be programmed the interference whether original information in the storage unit that storage unit closes on receives Leakage Current.
In addition; If measure the voltage of the continuous two piece bit lines adjacent with the bit line that applies low-voltage that is programmed storage unit; Calculated flow is crossed the Leakage Current of the storage unit of said two continuous bit lines connections; Through the interference of judging the size of said Leakage Current, can detect whether the program speed that is programmed storage unit and precision receive Leakage Current.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, characteristic and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by physical size equal proportion convergent-divergent.
Device when Fig. 1 is the cells of memory arrays programming operation connects synoptic diagram;
Fig. 2 operates closing on the method flow gauge figure that storage unit is disturbed for detection of stored array program of the present invention;
Fig. 3 be the method for the first embodiment of the present invention when detecting device connect synoptic diagram;
Fig. 4 has the connection synoptic diagram of voltage follow device for the method for the first embodiment of the present invention;
Fig. 5 is the circuit diagram of the voltage follow device of first embodiment;
Fig. 6 is the synoptic diagram of high-accuracy voltage proving installation;
Fig. 7 be the method for the first embodiment of the present invention when detecting device connect synoptic diagram;
Fig. 8 operates the bit line strobe unit connection synoptic diagram to the method for closing on the storage unit interference for detection of stored array program of the present invention.
Embodiment
Said as background technology; Do not apply any signal when conventional storage array carries out programming operation with on the bit line adjacent bit lines that applies low voltage signal or high voltage signal; In some programming cycle processes before the current programming operation; Owing to once be applied in programming signal, have residual positive charge, with the bit line adjacent bit lines that is programmed storage unit in the moment of programming operation; There is electric potential difference in source electrode with the storage unit of closing on that is programmed the shared word line that storage unit closes on and produces Leakage Current with the drain electrode two ends; Word line potential is higher during programming, and Leakage Current will make electric charge get into the accumulation layer of storage unit when big, to be programmed the original canned data of storage unit that storage unit closes on and produce and disturb.
During for the storage unit programming operation of detection of stored array with the storage unit of closing on that is programmed the shared word line that storage unit closes in canned data whether receive the influence of programming operation; The present invention proposes a kind of programming operation that detects to closing on the method that storage unit is disturbed; Technical scheme is when being programmed storage unit and programming; Measure and be programmed the voltage between two adjacent continuous bit lines of the bit line of storage unit simultaneously; Calculated flow is crossed the Leakage Current of the storage unit that said two continuous bit lines connect, and judges whether this Leakage Current can disturb with said and be programmed canned data in the storage unit that storage unit closes on.Scheme of the present invention can be when programming operation carries out; Flow through and the Leakage Current that is programmed the storage unit that storage unit closes on through measurement, reach detect programming operation whether can be programmed the storage unit that storage unit closes on and produce the purpose of disturbing.
Detection programming operation disclosed by the invention is seen Fig. 2 to the testing process figure of the method for closing on storage unit and disturbing, and comprising:
Step S1, gating are programmed the word line of storage unit; Many continuous bit lines of gating storage array wherein, apply first program voltage at a said bit line that is programmed storage unit, and another root bit line applies second program voltage, and said second program voltage is higher than said first program voltage; Every bit line only applies primary voltage in a programming process;
Step S2 measures the voltage between two continuous bit lines adjacent with the said bit line that is programmed storage unit;
Step S3, the Leakage Current of the storage unit of said two continuous bit lines connections is flow through in calculating according to the voltage between said two continuous bit lines;
Whether step S4 judges said Leakage Current greater than the predetermined current value, if programming operation pair receives said Leakage Current and disturbs with the said canned data that is programmed in the storage unit that storage unit closes on; If not, programming operation pair is programmed with said that canned data is not disturbed by said Leakage Current in the storage unit that storage unit closes on.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Secondly, the present invention combines synoptic diagram to be described in detail, and when the embodiment of the invention was detailed, for ease of explanation, said synoptic diagram was an example, and it should not limit the scope of the present invention's protection at this.Describe method of the present invention in detail through concrete embodiment below:
Embodiment one
Present embodiment provides a kind of programming operation that detects to closing on the method that storage unit is disturbed; Detect and be programmed storage unit and apply the voltage between two adjacent continuous bit lines of the bit line of low-voltage; Detect when storage unit is carried out programming operation programming operation to the detection synoptic diagram that closes on storage unit and disturb referring to Fig. 3; Think that it is example that storage unit Celln+2 carries out programming operation; Word line gating control signal is through the word line WL of word line strobe unit gating storage unit Celln+2, and bit line gating control signal is through at least four continuous bit line BLn-1, BLn, BLn+1 and BLn+2 of bit line strobe unit while gating storage array, and every bit line only applies primary voltage in a programming operation; The program current generator applies first program voltage for bit line BLn+1; The program voltage generator applies second program voltage for bit line BLn+2, and wherein, second program voltage is greater than first program voltage; Be connected on the voltage test device through the bit line strobe unit with bit line BLn+1 adjacent bit lines BLn-1 and BLn, the voltage between bit line BLn-1 and the BLn is measured through voltage test device.Usual means when wherein, program current generator and program voltage generator are programmed for carrying out storage unit usually.
If have residual charge among bit line BLn-1 and the BLn; Then when storage unit Celln+2 is programmed; Bit line BLn+1 is placed first program voltage by moment, because word line WL is noble potential, and the storage unit Celln and the Celln+1 conducting that close on storage unit Celln+2; To there be Leakage Current to flow through their raceway groove; When this Leakage Current surpasses the predetermined current value, can make electronics get into the floating boom of storage unit Celln and Celln+1, storage unit Celln and the original canned data of Celln+1 are produced interference.The method of measuring the Leakage Current size is to measure the magnitude of voltage U between programming operation moment bit line BLn-1 and BLn by voltage test device
1, the channel resistance of storage unit Celln is R1, the channel resistance of storage unit with its on canned data relevant.The Leakage Current Ileak1 that flows through on the storage unit Celln is according to computes:
Ileak1＝U
1/R1
Calculate the size of Leakage Current Ileak1, relatively Leakage Current and predetermined current value, if Leakage Current greater than predetermined current, storage unit Celln and Celln+1 information receive the Leakage Current interference, may be rewritten; If Leakage Current is less than said predetermined current, location information is not stated Leakage Current and is disturbed.
The detection programming operation of present embodiment is in the method for closing on the storage unit interference; At least five bit lines in all right gating storage array apply the voltage identical with second program voltage at least one bit line adjacent with the bit line that applies second program voltage.Referring to Fig. 4; When programming operation; Bit line gating control signal is passed through bit line strobe unit also gating and bit line BLn+2 adjacent bit lines BLn+3, and bit line BLn+3 applies second program voltage that equates with bit line BLn+2, and the voltage that is applied to bit line BLn+3 is provided by the voltage follow device.The effect of voltage follow device is to follow the voltage that the storage unit that is programmed applies second program voltage, one end, and makes the bit-line voltage that is attached thereto arrive same value.When storage unit Celln+2 was programmed, the voltage of storage unit Celln+3 equated, so can not produce Leakage Current, can guarantee the programming precision on the storage unit Celln+2.
Can comprise an operational amplifier in the voltage follow device, as shown in Figure 5, the output terminal 12 of operational amplifier is connected with inverting input 11, make amplifier output terminal 12 voltage just and the voltage of in-phase input end 10 be consistent.Referring to Fig. 4, the input end 10 of operational amplifier is the input end of voltage follow device, is connected the voltage output end of program voltage generator, and the voltage of output terminal 12 outputs of operational amplifier is applied on the bit line BLn+3 through the bit line strobe unit.When programming operation, the voltage follow device can carry out synchronous charging for connected bit line BLn+3 follows bit line BLn+2.
In addition, the voltage follower circuit in the present embodiment can also comprise control end, referring to Fig. 5, and voltage follower circuit work when control end 13 is high level, the voltage that output terminal 12 outputs equate with in-phase input end 10; When control end 13 was low level, voltage follower circuit was not worked, and output terminal 12 output voltages are zero.
Voltage test device in the present embodiment can adopt general voltage tester equipment; Also can adopt the high-accuracy voltage proving installation; Its structure is referring to Fig. 6; Comprise pre-amplification circuit, high-pass filtering circuit, low-pass filter circuit, main amplifying circuit and 50Hz trap circuit; Wherein, pre-amplification circuit be used for the sensor acquisition of high precision measurement device to voltage signal carry out the differential mode mode and amplify and avoid distorted signals, can form (for example can adopt independent components such as LM725CN) by three-stage operational amplifier with automatic offset compensation; High pass and low-pass filter circuit are used to reduce test noise to be disturbed, and can be made up of second order voltage controlled source circuit; Main amplifying circuit and 50Hz trap circuit are used to produce the amplitude with the input end coupling of A/D converter.Sensor acquisition to voltage signal carry out the differential mode mode after; High pass and low-pass filter circuit reduce test noise to be disturbed; The signal amplitude of the input end coupling of process main amplifying circuit and 50Hz trap circuit generation at last and A/D converter, the high-accuracy voltage proving installation can test out magnitude of voltage sensitive and accurately.
Simultaneously; Referring to Fig. 3; When storage unit Celln+2 is programmed,, just have electric charge constantly to add on the bit line BLn+2 if there is Leakage Current to exist on the storage unit Celln that closes on it, Celln+1 etc.; Finish up to whole leakage of residual charge, bit line BLn+1 just can reach the low voltage value U that satisfies programming operation
0, the read operation result of this moment could be effectively.Therefore, the existence of Leakage Current, but with the speed of interfere programming operation, also possibly influence the precision of programming.The detection programming operation of present embodiment also can detect the interference whether programming operation speed and precision receive Leakage Current to closing on the method that storage unit is disturbed through the size of judging Leakage Current.
Embodiment two:
Present embodiment provides a kind of programming operation that detects to closing on the method that storage unit is disturbed; Detect and be programmed storage unit and apply the voltage between two adjacent continuous bit lines of high-tension bit line; Detect when storage unit is carried out programming operation programming operation to the detection synoptic diagram that closes on storage unit and disturb referring to Fig. 7; Carrying out programming operation with storage unit Cellm+1 is example; Word line gating control signal is through the word line WL of word line strobe unit gating storage unit Cellm+1; Bit line gating control signal is through at least four continuous bit line BLm, BLm+1, BLm+2 and BLm+3 of bit line strobe unit while gating storage array, and the program current generator applies first program voltage for bit line BLm, and the program voltage generator applies second program voltage for bit line BLm+1; Be connected on the voltage test device through the bit line strobe unit with bit line BLm+1 adjacent bit lines BLm+2 and BLm+3, the voltage between bit line BLm+2 and the BLm+3 is measured through voltage test device.Wherein, the usual means when program current generator and program voltage generator are programmed for carrying out storage unit usually, voltage test device also can adopt the high precision measurement device among the embodiment one.
When storage unit Cellm+1 was programmed, bit line BLm+1 was placed the second program voltage U by moment
2Because word line WL is a noble potential; With storage unit Cellm+2 and Cellm+3 conducting that storage unit Cellm+1 closes on, bit line BLm+2 and BLm+3 do not apply voltage, have electric potential difference at the two ends of storage unit Cellm+2 and Cellm+3; To there be Leakage Current Ileak2 to flow through the raceway groove of storage unit Cellm+2 and Cellm+3; This Leakage Current surpasses when setting current value, can make electronics get into the floating boom of storage unit Cellm+2 and Cellm+3, and storage unit Cellm+2 and the original canned data of Cellm+3 are produced interference.The method of measuring the Leakage Current size is to measure moment bit line BLm+2 and the magnitude of voltage U between the BLm+3 when the programming operation by voltage test device
2, the channel resistance of storage unit Cellm+3 is R2, the channel resistance of storage unit with its on canned data relevant.The Leakage Current Ileak2 that flows through on the storage unit Cellm+3 is according to computes:
Ileak2＝U
2/R2
Calculate the size of Leakage Current Ileak2, relatively Leakage Current and predetermined current value, if Leakage Current greater than predetermined current, storage unit Cellm+2 and Cellm+3 information receive the Leakage Current interference, may be rewritten; If Leakage Current is less than said predetermined current, location information is not stated Leakage Current and is disturbed.
Simultaneously; Programming information when storage unit Cellm+1 is programmed is determined by the program current I on the bit line BLm+1; The existence of Leakage Current Ileak2 during programming; May influence the accuracy of program current I, so the detection programming operation of present embodiment can also detect the accuracy of programming operation to closing on the method that storage unit is disturbed through the size of judging Leakage Current.
The detection programming operation of present embodiment is in the method for closing on the storage unit interference; Many continuous bit lines of gating storage array are realized according to the gating control signal by the bit line strobe unit; The bit line strobe unit has multiple structure, and the bit line strobe unit of present embodiment can adopt the gating structure of a bit line of a gating control signal gating.Referring to Fig. 8; The bit line strobe unit comprises a plurality of MOS transistor M1, M2, M3...; When control signal is high level; The source electrode of MOS transistor and drain electrode conducting, bit line gating control signal S1 gating MOS transistor M1, program current generator are that the bit line BLm of storage array applies first program voltage through MOS transistor M1; Bit line gating control signal S2 gating MOS transistor M2, program voltage generator are that the bit line BLm+1 of storage array applies second program voltage through MOS transistor M2; Bit line gating control signal S3 gating MOS transistor M3, the bit line BLm+2 of storage array is connected with voltage test device one end through MOS transistor M3; Bit line gating control signal S4 gating MOS transistor M4, the bit line BLm+3 of storage array is connected with the voltage test device other end through MOS transistor M4.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (9)
1. one kind is detected programming operation to closing on the method that storage unit is disturbed, and it is characterized in that, comprising:
Gating is programmed the word line of storage unit; Many continuous bit lines of gating storage array wherein, apply first program voltage at a said bit line that is programmed storage unit, and another root bit line applies second program voltage, and said second program voltage is higher than said first program voltage; Every bit line can only apply primary voltage in testing process;
Measure the voltage between two continuous bit lines adjacent with the said bit line that is programmed storage unit;
Calculate the Leakage Current of the storage unit that flows through said two continuous bit lines connections according to the voltage between said two continuous bit lines;
Whether judge said Leakage Current greater than the predetermined current value, if receive said Leakage Current and disturb with the said canned data that is programmed in the storage unit that storage unit closes on; If not, be programmed with said that canned data is not disturbed by said Leakage Current in the storage unit that storage unit closes on.
2. detection programming operation according to claim 1 is characterized in that closing on the method that storage unit is disturbed, and measures and the said storage unit that is programmed applies the voltage between two adjacent continuous bit lines of the bit line of first program voltage.
3. detection programming operation according to claim 2 is to closing on the method that storage unit is disturbed; It is characterized in that; At least five continuous bit lines of gating storage array; In said at least five continuous bit lines, be programmed at least one adjacent continuous bit line of bit line that storage unit applies second program voltage and apply the voltage that equates with said second program voltage with said.
4. detection programming operation according to claim 3 is to closing on the method that storage unit is disturbed; It is characterized in that the said and said storage unit that is programmed applies at least one adjacent continuous bit line of high-tension bit line and applies the voltage that equates with said second program voltage and be:
Said second program voltage is from the in-phase input end input of operational amplifier; Through being that the bit line that is connected the output terminal of operational amplifier applies the voltage that equates with said second program voltage after the operational amplifier computing, the inverting input of said operational amplifier is connected output terminal.
5. detection programming operation according to claim 1 is characterized in that closing on the method that storage unit is disturbed, and measures and the said storage unit that is programmed applies the voltage between two adjacent continuous bit lines of the bit line of second program voltage.
According to each described detection programming operation of claim 1 to 5 to closing on the method that storage unit is disturbed, it is characterized in that the voltage that said measurement and said is programmed between two adjacent continuous bit lines of the bit line of storage unit comprises:
After gathering the voltage between said two continuous bit lines, order is carried out following each step;
Voltage between said two continuous bit lines carries out the differential mode mode through pre-amplification circuit and amplifies the acquisition amplification voltage signal;
Said amplification voltage signal value is removed noise through high-pass filtering circuit and low-pass filter circuit;
Amplification voltage signal after the removal noise is through main amplifying circuit and 50Hz trap circuit transition amplitude.
According to each described detection programming operation of claim 1 to 5 to closing on the method that storage unit is disturbed, it is characterized in that many continuous bit lines of said gating storage array are:
A plurality of gating control signals are controlled a plurality of MOS transistor conductings; Wherein, The source electrode and drain electrode conducting of a MOS transistor of a gating control signal control make the bit line of the source electrode that is connected a MOS transistor apply said first program voltage or second program voltage that is connected drain electrode.
According to each described detection programming operation of claim 1 to 5 to closing on the method that storage unit is disturbed, it is characterized in that the program current generator is that a said bit line that is programmed storage unit applies first program voltage.
According to each described detection programming operation of claim 1 to 5 to closing on the method that storage unit is disturbed, it is characterized in that the program voltage generator is that said another root bit line that is programmed storage unit applies second program voltage.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105372435A (en) * | 2014-08-26 | 2016-03-02 | 中国科学院苏州纳米技术与纳米仿生研究所 | Biological detection system based on graphene and making and integrating methods thereof |
| CN109390028A (en) * | 2017-08-10 | 2019-02-26 | 北京兆易创新科技股份有限公司 | It is automatically repaired the method and device of NOR type storage array bit line failure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411001A (en) * | 2001-09-27 | 2003-04-16 | 夏普公司 | Bit line controlling decoder circuit, semiconductor storage device and data device and data reading method thereof |
| US20040190351A1 (en) * | 2003-03-24 | 2004-09-30 | Kabushiki Kaisha Toshiba | Leak immune semiconductor memory |
| CN101667455A (en) * | 2008-09-01 | 2010-03-10 | 松下电器产业株式会社 | Semiconductor memory device |
| CN102148051A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Memory and sensitive amplifier |
-
2011
- 2011-11-30 CN CN201110391567.2A patent/CN102426860B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411001A (en) * | 2001-09-27 | 2003-04-16 | 夏普公司 | Bit line controlling decoder circuit, semiconductor storage device and data device and data reading method thereof |
| US20040190351A1 (en) * | 2003-03-24 | 2004-09-30 | Kabushiki Kaisha Toshiba | Leak immune semiconductor memory |
| CN101667455A (en) * | 2008-09-01 | 2010-03-10 | 松下电器产业株式会社 | Semiconductor memory device |
| CN102148051A (en) * | 2010-02-10 | 2011-08-10 | 上海宏力半导体制造有限公司 | Memory and sensitive amplifier |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105372435A (en) * | 2014-08-26 | 2016-03-02 | 中国科学院苏州纳米技术与纳米仿生研究所 | Biological detection system based on graphene and making and integrating methods thereof |
| CN109390028A (en) * | 2017-08-10 | 2019-02-26 | 北京兆易创新科技股份有限公司 | It is automatically repaired the method and device of NOR type storage array bit line failure |
| CN109390028B (en) * | 2017-08-10 | 2021-01-22 | 北京兆易创新科技股份有限公司 | Method and device for automatically repairing NOR type memory array bit line fault |
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