TWI431630B - Apparatus of lift-time test for non-volatile memory and method thereof - Google Patents

Description

Lifetime detecting device and method for non-volatile memory

The present invention relates to a non-volatile memory detecting device and method, and more particularly to a non-volatile memory life detecting device and method.

A non-volatile memory is a type of memory that can retain its stored data while the memory is not being powered. In today's technology, non-volatile memory can be roughly divided into two types, one of which is a read only memory (ROM), and the other is a flash memory.

In addition to the speed, capacity, and price of accessing data, non-volatile memory has an important feature that needs to be considered by users, that is, the lifetime of non-volatile memory. In the detection of the lifetime of non-volatile memory, conventional techniques are often carried out by means of increasing the temperature.

Please refer to FIG. 1 below. FIG. 1 is a timing diagram showing the relationship between the charge loss rate of a non-volatile memory at a different temperature reaching a critical value. In the past semiconductor process, because the bottom oxide layer (Bottom Oxide, Box) of the non-volatile memory is thicker, the relationship between the data storage time and the activation energy (the slope of the curve) is shown. 1 is shown by curves 110 and 120. Curves 110 and 120 have charge loss rates of 70% and 85%, respectively, which are derived for different charge loss interpretation criteria. The linearity of the curves 110, 120 is very good. Therefore, in the prior art, it is feasible to use the temperature rise for detecting the lifetime of the non-volatile memory.

However, with the change of process technology, the bottom oxide layer of today's non-volatile memory is getting thinner and thinner, and the relationship between data storage time and activation energy of non-volatile memory is shown as curve 130 of FIG. And 140 shows. Obviously, curves 130 and 140 do not have excellent linearity in the low temperature region (the right segment of FIG. 1), and therefore, the accuracy of prediction of the lifetime of the low temperature region of the nonvolatile memory by temperature rise is also It will fall.

In addition, in the conventional temperature rising detection mode, it is necessary to provide different stable temperatures so that the charge loss rate of the floating gate of the non-volatile memory reaches a critical value, which requires a long time, which inevitably increases the cost of the test.

The present invention respectively provides a non-volatile memory life detecting device and method for accurately and quickly detecting the lifetime of a non-volatile memory.

The present invention provides a lifetime detection method for a non-volatile memory unit, comprising: first, providing a first bias voltage to a control gate of a non-volatile memory unit. Next, the charge loss rate of the floating gate of the non-volatile memory unit is detected, and when the charge loss rate exceeds a preset threshold, the first charge loss time of the first bias voltage is recorded. And providing a second bias voltage to the control gate of the memory unit of the non-volatile memory, and then detecting the charge loss rate of the floating gate of the memory unit. When the charge loss rate exceeds a preset threshold, the record is recorded. The second charge loss time at which the two bias voltages act. Then, providing a third bias voltage to the control gate of the non-volatile memory unit, and then detecting the charge loss rate of the floating gate of the memory unit, and recording the third bias when the charge loss rate exceeds a preset threshold The third charge loss time of the voltage action. Finally, the physical model and the linear approximate extrapolation arithmetic operation are performed according to the first, second, and third bias voltages applied to the control gate and the calculated first, second, and third charge loss times of the floating gate, and Obtaining a charge loss factor caused by electric field acceleration by an arithmetic operation, and knowing the lifetime of the non-volatile memory unit, and according to the voltage values of the first, second, and third bias voltages and the corresponding first The relationship between the second and third charge loss times is to obtain the memory lifetime equation.

In an embodiment of the invention, the step of detecting the charge loss rate of the memory unit includes: first, measuring and calculating the control gate of the non-volatile memory unit to be applied with the first, second, and third bias voltages. The drain current of the bit line measured when one of the voltages is measured. And, the ratio of the drain current of the bit line to the drain current of the bit line when the non-volatile memory cell is not applied with any bias voltage is calculated to obtain a charge loss rate.

In an embodiment of the present invention, the step of the life detecting method further includes: firstly, providing a non-volatile memory unit for testing, and then providing a test pattern and targeting the non-volatile memory unit according to the test pattern. Charge it.

In an embodiment of the invention, the control gate of the memory cell providing the first, second, and third bias voltages to the non-volatile memory is used to generate the first on the charge tunneling path of the memory cell. An applied electric field, a second applied electric field, and a third applied electric field.

In an embodiment of the present invention, the method for detecting a lifetime, further comprising: providing at least a fourth bias voltage to a control gate of the non-volatile memory unit, and detecting the non-volatile memory unit. Charge loss rate. When the charge loss rate exceeds a predetermined threshold, at least a fourth charge loss time at which the fourth bias voltage acts is recorded.

In an embodiment of the present invention, the life cycle detecting method further includes: matching the first, second, and third biases according to the fourth bias voltage and the calculated fourth charge loss time of the floating gate The voltage and the calculated first, second, and third charge loss times of the floating gate are used to perform a linear extrapolation operation of the physical model and the linear approximation operation to obtain an electric field acceleration charge loss factor and to obtain an applied electric field. The lifetime of non-volatile memory.

In an embodiment of the invention, the life detecting method further includes applying a fifth bias voltage to verify a control gate of the non-volatile memory unit, wherein the effective time for applying the fifth bias voltage is determined by the fifth The bias voltage value is substituted into the memory lifetime equation. If the non-volatile memory reaches the preset threshold within the effective time or the end of the effective period of applying the fifth bias, the non-volatile memory unit is determined to be invalid. .

The invention provides a lifetime detecting device for a non-volatile memory, comprising a bias supply circuit, a control circuit and a current detector. The bias supply circuit is coupled to the non-volatile memory for providing a first bias voltage through a word line of the non-volatile memory array formed by the plurality of non-volatile memory cells in the non-volatile memory The two bias voltages and the third bias voltage are to the control gates that are not the volatile memory cells. The control circuit is coupled to the bias supply circuit for controlling the bias voltage supply circuit to provide the first, second, and third bias voltages to the bias voltage value of the word line of the non-volatile memory array and the duration of the action. The current detector is coupled to the control circuit and the bit line of the non-volatile memory array for detecting the charge loss rate of the floating gate of the non-volatile memory array. Wherein, the control circuit records the first charge loss time when the first bias voltage is applied, and the charge loss rate is greater than a preset threshold, when the second bias voltage acts and the charge loss rate is greater than a preset threshold The second charge loss time is recorded, and the third charge loss time is recorded when the third bias voltage is applied and the charge loss rate is greater than a predetermined threshold. According to the first, second and third bias voltages and the first, second and third charge loss times, the linear extrapolation operation of the physical model and the linear approximation operation are performed to obtain the electric field acceleration charge loss factor and the non-applied electric field is obtained. The lifetime of volatile memory.

Based on the above, the present invention utilizes different bias voltages on the control gates of the non-volatile memory cells to produce different applied electric fields. The charge loss state of the memory cell is detected to obtain the charge loss time generated by the memory cell under different applied electric fields. Moreover, physical model and linear approximation extrapolation arithmetic operations are performed using different charge loss times generated by different bias voltages to obtain an electric field accelerating factor (slope parameter) of dominant charge loss and life of non-volatile memory. period.

The above described features and advantages of the present invention will be more apparent from the following description.

Referring to FIG. 2, FIG. 2 is a flow chart showing the steps of the non-volatile memory lifetime detecting method 200 according to an embodiment of the present invention. The step of the lifetime detection method 200 of the present embodiment includes first providing a first bias voltage to a control gate of the non-volatile memory unit (step S210). That is, a first bias voltage is applied to the control gate of the non-volatile memory cell under test, and an applied electric field is generated on the charge tunneling path in the memory cell.

Next, detecting a charge loss rate of a floating gate of a memory cell of the non-volatile memory, and recording a first bias voltage when the charge loss rate exceeds a predetermined threshold A charge loss time (step S220). That is, the charge loss rate of the floating gate for the non-volatile memory cell in the case where the first bias voltage is continuously applied. Due to the continuous application of the first bias voltage, the charge loss rate of the memory cell is increased with the application time of the first bias voltage. Once the charge loss rate of the memory cell is detected to exceed a predetermined threshold, the length of time during which the first bias voltage is applied is recorded as the first control gate of the non-volatile memory unit. The first charge loss time of the floating gate corresponding to the bias voltage.

Please note that the detection of the so-called charge loss rate can be determined by measuring the magnitude of the current supplied by the memory cell or the drain of the drain by the bit line of the memory cell. As is well known in the art, the memory unit will internally have a stable threshold voltage to determine the stored data as digital data after being charged according to the data to be stored. 1" or "0". When the applied electric field generated by the first bias voltage is applied to the memory unit, the stored charge of the floating gate will be lost, thereby causing the stored digital data to be "1" or "0". The threshold voltage level can provide or the value of the current flowing into the drain decreases.

In addition, the preset threshold is a data set by the tester. This preset threshold is set based on the maximum product application tolerance of the charge loss rate of the memory cells in the non-volatile memory. That is to say, when the charge loss rate of the floating gate of the non-volatile memory unit exceeds a preset threshold, it indicates that the non-volatile memory has been unable to discriminate "1" or "0".

Here, the charge loss rate can be calculated by measuring the drain current of the bit line of the non-volatile memory cell when the control gate of the non-volatile memory cell is applied with the first bias voltage, and calculating The ratio of the drain current of this bit line to the drain current of the bit line generated when the control gate of the non-volatile memory cell is not applied with any bias voltage. This calculated ratio is the charge loss rate of the floating gate of the non-volatile memory cell.

Step S220 is continued, followed by providing a second bias voltage to the control gate of the memory unit of the non-volatile memory (step S230), and detecting the charge loss rate of the floating gate of the memory unit, when the charge When the loss rate exceeds the preset threshold, the second charge loss time at which the second bias voltage acts is also recorded (step S240).

Note here that the first bias voltage for controlling the gate in step S210 is different from the voltage value of the second bias voltage in step S230. To put it simply, the memory cells of the non-volatile memory are provided with bias voltages (applied electric fields) of control gates of different sizes, and are recorded by the measurement of the charge loss rate of the floating gates. Different charge loss times for non-volatile memory under different applied electric fields.

Next, providing a third bias voltage to the control gate of the memory unit of the non-volatile memory (step S250), and detecting the charge loss rate of the floating gate of the memory unit, when the charge loss rate exceeds the preset At the critical value, the third charge loss time at which the third bias voltage acts is also recorded (step S260). Here, the voltage values of the first, second, and third bias voltages described above are not equal.

Finally, the arithmetic operation is performed according to the first, second, and third bias voltages applied to the control gate and the first, second, and third charge loss times of the floating gate, and by repeating several different bias voltages. Performing an arithmetic operation on the calculated charge loss time of the floating gate to obtain an electric field acceleration factor and a charge loss rate, thereby obtaining a lifetime of the non-volatile memory (step S270), and according to the first, The relationship between the voltage values of the two and three bias voltages and the corresponding first, second, and third charge loss times to obtain a memory lifetime equation.

It is worth mentioning that in addition to providing three different bias voltages for lifetime detection of the non-volatile memory under test, it is also possible to add at least one bias voltage different from the control gate, for example, providing Four bias voltages to the control gate of the memory cell of the non-volatile memory to obtain a fourth charge loss time, and thereby with the first, second, and third bias voltages and the first, second, and third charge loss times Linear extrapolation of physical models and linear approximation to perform lifetime detection of non-volatile memory.

In this embodiment, the so-called arithmetic operation may utilize a first bias voltage, a first charge loss time, a second bias voltage, a second charge loss time proportional relationship, and a third bias voltage and a third charge loss time. The proportional relationship uses a linear extrapolation algorithm of the physical model to calculate the charge loss time when the non-volatile memory is not applied with an applied electric field. The charge loss time when the applied electric field is not applied is equivalent to the lifetime of the non-volatile memory to be tested (S270). Here, the so-called physical model is obtained by calculation of a non-volatile memory unit using a physical effect mechanism, which is well known to those of ordinary skill in the art and will not be described in detail herein.

Since the first, second and third charge loss times (or more charge loss time) do not necessarily exhibit a perfect linear alignment. Therefore, under the correspondence of more than two obtained bias voltages and charge loss times, the so-called optimal linear approximation method commonly used in numerical analysis can be used to perform arithmetic operations, and thereby obtaining no applied external electric field. The charge loss time of the floating gate of a non-volatile memory, that is, the lifetime of a non-volatile memory.

In addition, the embodiment may further apply a fifth bias voltage to verify the control gate of the non-volatile memory unit, wherein the effective time for applying the fifth bias voltage is substituted into the memory by the fifth bias voltage value. Obtained from the equation of life. The non-volatile memory unit is determined to be ineffective if the non-volatile memory has reached a predetermined threshold during the effective time or end of application of the fifth bias.

Referring to FIG. 3A, FIG. 3A is a diagram showing a relationship between a voltage value of a bias voltage generated at a control gate and a duty time thereof and a charge loss rate of a floating gate according to an embodiment of the invention. Curves 311 to 317 indicate the measured floating gates under different bias voltages (for example, -9V, -8V, -7V, -6V, -5V, -4V, -3V, respectively). The charge loss rate is plotted against the time of action of the bias voltage that controls the gate. In this embodiment, the preset threshold value set is 75%. That is, when the charge loss rate exceeds 25% (100% to 75%), the application time of the bias voltage is the charge loss time. Taking curve 313 as an example, when the bias voltage is applied to -7V, the charge loss time of the non-volatile memory is 10 ¹ second, that is, 10 seconds.

Referring to FIG. 3A and FIG. 3B simultaneously, FIG. 3B is a diagram showing the relationship between the bias voltage generated according to FIG. 3A and the corresponding tunneling electric field and the charge loss time. The corresponding points 311P~317P correspond to the curves 311~317 of FIG. 3A, respectively. Briefly, the curve 313 shown in FIG. 3A indicates that the charge loss time is 10 seconds when the bias voltage is -7 V, and corresponds to FIG. 3B as the corresponding point 313P. Corresponding relationship between the corresponding points and the respective curves may be derived according to the above-mentioned curve 313 and the corresponding point 313P, and details are not described herein. FIG. 3B further illustrates the relationship between the magnitude of the bias voltage and the applied applied electric field. Taking the corresponding point 313P as an example, when the bias voltage is equal to -7 V, the applied electric field is 9 MV/cm.

Please pay special attention here, the arrangement of the corresponding points 312P~317P is neat and almost linear, while the corresponding point 311P is not. The corresponding point 311P causes an excessively large applied voltage by applying an excessive bias voltage (-9 V), thereby causing an extremely short charge loss time. Obviously the corresponding point 311P data is not a reference value, but can be discarded. In the case where the corresponding point 311P is discarded, the straight line 320 can be calculated for the corresponding points 312P to 317P by, for example, an arithmetic operation of the best linear approximation. And by calculating the intersection of the vertical axis of the relationship between the line 320 and FIG. 3B, the value of the slope of the line calculated by the corresponding points 312P to 317P is the electric field acceleration factor. By using the electric field acceleration factor and the charge loss rate, the lifetime of the tested non-volatile memory without applying an applied electric field can be known. It is important to note that the linear physical model described above is merely a simple linear physical model as an example, and does not mean that the invention must be limited to use a linear physical model as described above.

In order to more clearly illustrate the details of the operation of the embodiment of the test method for non-volatile memory of the present invention, a practical example will be presented below. Further, the features of the present invention can be more easily understood by those of ordinary skill in the art.

When performing the test, the non-volatile memory wafer that completes the process flow is first introduced into the test machine, and the wafer level test machine is used to pass through, for example, a probe card or other means. To write a test pattern to the non-volatile memory of one of the wafers. This test pattern is input by the test engineer to the test machine, which includes a number of digital signals that are different from "0" and "1". The test machine charges (ie, writes) the test pattern to a plurality of memory cells (also referred to as memory array cells) of the non-volatile memory under test.

After completing the charging operation described above, the test machine provides different bias voltages for the tested non-volatile memory at different points in time, and obtains different charge loss times according to the action steps described in the foregoing embodiments. Finally, the test machine reuses the obtained charge loss time and the corresponding applied bias voltage for arithmetic operations, and obtains the lifetime of the measured non-volatile memory.

Referring to FIG. 4A, FIG. 4A is a schematic diagram of a lifetime detecting device for a non-volatile memory according to another embodiment of the present invention. The lifetime detecting device 410 is coupled to the non-volatile memory, and the lifetime detecting device 410 includes a control circuit 411, a bias providing circuit 412, and a current detector 413. The bias supply circuit 412 is coupled to the non-volatile memory for providing different bias voltages VBIAS1, VBIAS2, VBIAS3 to the word line of the memory unit 420 of the non-volatile memory (control gate CG) . The control circuit 411 is coupled to the bias supply circuit 412 for controlling the bias voltage supply circuit 412 to provide the bias voltage VBIAS1, VBIAS2, VBIAS3 to the bias voltage value and duration of the control gate CG of the memory unit 420. The current detector 413 is coupled to the source circuit Source and the drain Drain of the control circuit 411 and the non-volatile memory unit for detecting the charge loss rate of the floating gate FG of the memory unit 420.

It should be noted that FIG. 4A only shows a single memory unit 420 for the sake of clear implementation of the embodiment, and does not mean that the lifetime detecting device 410 can only detect for one memory unit. In fact, in the non-volatile memory under test, all of the memory array units can be completed by one-time detection by the lifetime detecting device 410.

Further, the control circuit 411 records the first charge loss time when the first bias voltage VBIAS1 acts and the charge loss rate is greater than a predetermined threshold, and the charge when the second and third bias voltages VBIAS2, VBIAS3 are respectively applied. The second and third charge loss times when the loss rate is greater than the preset threshold. The control circuit 411 performs arithmetic operations according to the first, second, and third bias voltages VBIAS1, VBIAS2, VBIAS3, and the first, second, and third charge loss times, and obtains the lifetime of the non-volatile memory by arithmetic operations.

The details of the operation of the non-volatile memory lifetime detecting device 410 of the present embodiment are the same as those of the embodiment of the non-volatile memory lifetime detecting method of the present invention, and the description thereof will not be repeated.

In addition, please refer to FIG. 4B. FIG. 4B is a schematic diagram of detecting the non-volatile memory array by the lifetime detecting device 410 according to the embodiment of the present invention. Among them, the non-volatile memory array shown in FIG. 4B is only one of the simplest examples. In the depiction of FIG. 4B, the lifetime detection device 410 can also be coupled to the lifetime of a non-volatile memory array composed of a plurality of non-volatile memory cells 4201-420N. The bias supply circuit 412 provides a bias voltage to the non-volatile memory cells 4201 to 420N through the word lines WL1 WL WLn, and the current detector 413 detects the non-volatile by the bit lines BL1 BL BLm. The drain current of the memory cells 4201 to 420N. As such, the lifetime of all of the non-volatile memory cells 4201-420N located in the non-volatile memory array can be known by the lifetime detection device 410.

In summary, the present invention provides a memory unit applied electric field by applying different bias voltages to the control gates on the memory cells of the non-volatile memory. And the charge loss time of the non-volatile memory under different bias voltages is obtained by measuring the charge loss rate of the floating gate of the memory unit. The arithmetic operation is performed by obtaining the charge loss time and the corresponding bias voltage, and the electric field acceleration factor and the lifetime of the non-volatile memory are detected. This method of applying an applied electric field does not affect the thickness of the bottom oxide layer of the non-volatile memory, and the lifetime of the accurate non-volatile memory can be detected. Moreover, the rise (boost) and settling time required to apply the bias voltage are short, which saves time and cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

110~140, 311~317‧‧‧ Curve

200‧‧‧Lifetime detection method

311P~317P‧‧‧ corresponding point

320‧‧‧ Straight line

410‧‧‧Lifetime detection device

411‧‧‧Control circuit

412‧‧‧ bias supply circuit

413‧‧‧ Current Detector

420, 4201~420N‧‧‧ memory unit

VBIAS1, VBIAS2, VBIAS3‧‧‧ bias voltage

FG‧‧‧Floating gate

CG‧‧‧Control gate

Source‧‧‧ source

Drain‧‧‧汲

Steps of the S210~S270‧‧‧ test method

BL1~BLn‧‧‧ bit line

WL1~WLn‧‧‧ word line

FIG. 1 is a graph showing the time relationship of the non-volatile memory at a different temperature corresponding to a charge loss rate reaching a critical value.

2 is a flow chart showing the steps of a lifetime detection method 200 for a non-volatile memory according to an embodiment of the invention.

FIG. 3A is a graph showing the relationship between the voltage value of the bias voltage and its action time and the charge loss rate according to an embodiment of the invention. FIG.

FIG. 3B is a graph showing the relationship between the bias voltage generated according to FIG. 3A and the corresponding tunneling electric field and the charge loss time.

4A is a schematic diagram of a lifetime detecting device for a non-volatile memory according to another embodiment of the present invention.

FIG. 4B is a schematic diagram of the lifetime detecting device 410 detecting the non-volatile memory array according to the embodiment of the present invention.

200. . . Lifetime detection method

S210~S270. . . Steps of the detection method

Claims (15)

A life time detecting method for a non-volatile memory unit includes: providing a first bias voltage to a control gate of the non-volatile memory unit; detecting a charge loss of the non-volatile memory unit Rate, when the charge loss rate exceeds a predetermined threshold, recording a first charge loss time of the first bias voltage; providing a second bias voltage to the control gate of the non-volatile memory unit; Detecting the charge loss rate of the memory cells, when the charge loss rate exceeds the predetermined threshold, recording a second charge loss time of the second bias voltage; providing a third bias voltage to a control gate of the memory cells of the non-volatile memory unit; detecting the charge loss rate of the memory cells, and recording the third bias voltage when the charge loss rate exceeds the predetermined threshold a third charge loss time of the action; and the first, second, and third charge loss times according to the first, second, and third bias voltages applied to the control gate and the calculated floating gate Performing a linear extrapolation operation of a physical model and a linear approximation operation to obtain an electric field acceleration charge loss factor and obtaining a lifetime of the non-volatile memory when no electric field is applied, and according to the first, second, and third biases The voltage value of the voltage is related to the corresponding first, second and third charge loss time To a memory life cycle equation. The method for detecting a lifetime of the floating gate according to claim 1, wherein the step of detecting a charge loss rate of the floating gate of the memory unit comprises: measuring and calculating the control gate of the non-volatile memory unit a drain current measured when one of the first, second, and third bias voltages is applied; and calculating a drain current when the drain current is not applied to the non-volatile memory cell The ratio of the currents is obtained to obtain the charge loss rate. The method for detecting a lifetime according to claim 1, further comprising: providing the non-volatile memory unit for testing; and providing a test pattern and charging the non-volatile memory unit according to the test pattern . The life cycle detecting method according to claim 1, wherein the linear approximation operation is an optimal linear approximation extrapolation algorithm. The method for detecting a lifetime according to claim 1, wherein the first, second, and third bias voltages are supplied to the control gate of the non-volatile memory unit of the non-volatile memory for use in the non-volatile A first applied electric field, a second applied electric field, and a third applied electric field are generated on the charge tunneling path of the memory cell. The method for detecting a lifetime according to claim 1, further comprising: providing at least a fourth bias voltage to the non-volatile memory unit Controlling the gate; detecting the charge loss rate of the non-volatile memory cell, and recording the at least one fourth charge loss time of the fourth bias voltage when the charge loss rate exceeds the predetermined threshold. The method for detecting a lifetime according to claim 6, wherein the method further comprises: matching the fourth bias voltage and the calculated fourth charge loss time of the floating gate according to the first, second, a three-bias voltage and the calculated first, second, and third charge loss times of the floating gate to perform a linear extrapolation operation of the physical model and the linear approximation operation to obtain the electric field acceleration charge loss factor and The lifetime of the non-volatile memory when no electric field is applied. The method of detecting a lifetime according to claim 1, further comprising: applying a fifth bias voltage to verify a control gate of the non-volatile memory unit, wherein an effective time of applying the fifth bias voltage Obtaining the fifth bias voltage value into the memory lifetime equation, if the non-volatile memory reaches the preset threshold during the effective time or end of applying the fifth bias, the non-volatile The memory unit is determined to be invalid. A non-volatile memory lifetime detecting device includes: a bias providing circuit coupled to the non-volatile memory for transmitting a plurality of non-volatile memory cells in the non-volatile memory The word line of the non-volatile memory array provides a first bias voltage, one a second bias voltage and a third bias voltage to the control gates of the non-volatile memory unit; a control circuit coupled to the bias supply circuit for controlling the bias supply circuit to provide the first a bias voltage value of the first, second, and third bias voltages to the word line of the non-volatile memory array and a duration of the action time; and a current detector coupled to the control circuit and the non-volatile memory for detecting Measuring a charge loss rate of the floating gate of the non-volatile memory array, wherein the control circuit records a first charge when the first bias voltage is applied and the charge loss rate is greater than a predetermined threshold Loss time, recording a second charge loss time when the second bias voltage is applied and the charge loss rate is greater than the predetermined threshold, and when the third bias voltage is applied and the charge loss rate is greater than The preset threshold value records a third charge loss time, and the control circuit performs a linear extrapolation operation of the physical model according to the first, second, and third bias voltages and the first, second, and third charge loss times. And a linear approximation operation to obtain an electric field acceleration charge loss factor and to obtain a lifetime of the non-volatile memory when no electric field is applied, and according to the voltage values of the first, second, and third bias voltages The relationship of the first, second, and third charge loss times is to obtain a memory lifetime equation. The life detecting device of claim 9, wherein the step of detecting a charge loss rate of the non-volatile memory array comprises: measuring, and calculating, the non-volatile memory array by the current detector a drain current of one of the bit lines measured when the word line is applied to one of the first, second, and third bias voltages, and calculating the drain current of the bit line and the non-volatile memory array The ratio of the drain current of the bit line when any bias voltage is applied to obtain the charge loss rate. The life-time detecting device of claim 9, wherein the control circuit further comprises charging the non-volatile memory array according to a test pattern. The life detecting device of claim 9, wherein the bias providing circuit provides the first, second, and third bias voltages to the word line of the non-volatile memory array of the non-volatile memory. A first applied electric field, a second applied electric field, and a third applied electric field are generated on the charge tunneling path of the memory cell array. The life detecting device of claim 9, wherein the control circuit further controls the bias providing circuit to provide at least a fourth bias voltage to a control gate of the non-volatile memory unit, the current detecting And detecting the charge loss rate of the non-volatile memory unit, and recording the at least one fourth charge loss time of the fourth bias voltage when the charge loss rate exceeds the predetermined threshold. The life detecting device of claim 13, wherein the control circuit further comprises: according to the fourth bias voltage and the calculated fourth charge loss time of the floating gate, according to the first And a second linear bias voltage and the calculated first, second, and third charge loss times of the floating gate to perform a linear extrapolation operation of the physical model and the linear approximation operation to obtain the electric field accelerated charge loss factor and Got The lifetime of the non-volatile memory when no electric field is applied. The life detecting device of claim 9, wherein the bias providing circuit further applies a fifth bias voltage to verify a control gate of the non-volatile memory unit, wherein the fifth bias voltage is applied The effective time is obtained by substituting the fifth bias voltage value into the memory lifetime equation, and if the non-volatile memory reaches the preset threshold during the effective time or end of applying the fifth bias, Then the non-volatile memory unit is determined to be invalid.