CN102420611A - Sampling rate conversion method and device of digital signal - Google Patents

Sampling rate conversion method and device of digital signal Download PDF

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CN102420611A
CN102420611A CN2011100251345A CN201110025134A CN102420611A CN 102420611 A CN102420611 A CN 102420611A CN 2011100251345 A CN2011100251345 A CN 2011100251345A CN 201110025134 A CN201110025134 A CN 201110025134A CN 102420611 A CN102420611 A CN 102420611A
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吴晟
林福辉
张本好
李昙
徐晶明
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Spreadtrum Communications Shanghai Co Ltd
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Abstract

The invention discloses a sampling rate conversion method and device of a digital signal, aiming to provide a sampling rate cascading conversion method matched with small conversion. The key points of the technical scheme of the sampling rate cascading conversion method comprise the steps of: decomposing the sampling rate conversion into a situation of only executing integer conversion, a situation of only executing the small conversion and a situation of carrying out both of the integer conversion and the small conversion according to a situation of different integer ratios of an input sampling rate and an output sampling rate; and determining positions of the small conversion and the integer conversion in the whole sampling rate conversion according to the sizes of the input sampling rate and the output sampling rate, a calculated quantity and signal quality requirements, and establishing the cascading conversion for carrying out the sampling rate conversion on input signals. According to the sampling rate conversion method of the digital signal, disclosed by the invention, the integer conversion is matched with the small conversion in the process of signal sampling rate conversion, thus the lower calculated quantity for the sampling rate conversion of the digital signal can be realized, and signals obtained after conversion have higher quality.

Description

A kind of sampling rate converting method of digital signal and device
Technical field
The present invention relates to a kind of sampling rate converting method and device of digital signal, particularly to digital signals sampling rate cascade conversion method and device.
Background technology
The digital signal of discrete time be by analog to digital conversion circuit under certain operating frequency, with what quantize behind the continuous time analog signal sampling to obtain, the operating frequency of analog to digital conversion circuit is the sample frequency of digital signal (abbreviation sample rate).When digital signal is handled in digital system; Because the difference of processing requirements, the operating frequency of digital processing system tends to the sample frequency of signal itself inconsistent, at this moment; In order to make system's synchronous working normally, need be with the sample rate f of digital signal 1Be transformed into the operating frequency f of system 2, this work is realized by the sample rate conversion device.
Often (rise sample rate is Integer N to the sample rate conversion device by rising sampler; Mending N-1 zero through pointwise realizes), (the normalization cut-off frequency is min (1/M to low pass filter; (falling sample rate is integer M 1/N)), to fall sampler; Through extracting a realization at a distance from the M-1 point) constitute, this device can be with the sample rate f of digital signal 1=f sBe transformed into f 2=f sN/M promptly realizes the sample rate conversion of ratio of integers.The sampling rate converting method of this structure is a classic methods; Be that (passband that is filter has linear phase and constant amplitude under the situation of ideal filter at low pass filter; The transition band bandwidth is 0; Stopband attenuation is infinitely great), (when wherein high sampling rate was transformed into low sampling rate, the signal band that remains can't harm the sample rate conversion that can accomplish to can't harm; Low sampling rate is transformed into high sampling rate, and the signal whole frequency all can't harm).Based on the sample rate conversion device of this structure, specifically can use multiphase filter, cascade multiphase filter or IIR recursion filter are realized; Specifically can be with reference to the state's patent 200310123833.9,200480008710.3,200620154202.2 of passing the examination; 02822878.2,200610082000.6.
Except by rising sampler, low pass filter and falling the sample rate conversion structure that sampler forms, also has directly sample rate conversion structure through the signal interpolation realization.The data in a certain moment were used for output in the middle of sampled data before and after this structure utilization estimated.Chinese patent 98802865.4 has just adopted linear interpolation to realize the conversion of sample rate.
By rising sampler, low pass filter with the sample rate conversion structure that sampler is formed is fallen, the height of its switching signal quality (fidelity) mainly depends on the computation complexity of low pass filter.The computation complexity of low pass filter is high; Filter is near desirable; The quality of switching signal is just high so, but is accompanied by the increase of conversion equipment work load, if system is comparatively responsive to conversion equipment work load degree; So also can pass through the victim signal conversion quality, use the filter of low computation complexity.The complexity of the low pass filter that design sample rate conversion device is used is the ratio of integers f with sample rate 1: f 2=M: N is relevant, M wherein, and N does not have common factor, can not further reduce.If max (N, M) bigger, the cut-off frequency min (1/M of low pass filter so; 1/N) can be very low, designing high-quality low pass filter computation complexity can be very high, arrives 44100Hz such as the conversion of signals that with sample rate is 32000Hz; M: N=320: 441; The cut-off frequency of filter is 1/441, and the filter length requirement is 320 * 441 integral multiple, high (M: N=2: the 3 when computation complexity of low pass filter far arrives 48000Hz than the conversion of signals that with sample rate is 32000Hz; The cut-off frequency of filter is 1/3, and the filter length requirement is 2 * 3 integral multiple).Adopt the signal interpolation structure, can avoid the high computation complexity of low pass filter, but the conversion of signals quality is not good, have more serious sneak into noise, the distortion of signal aliasing harmonic.
Summary of the invention
The object of the present invention is to provide a kind of sampling rate converting method and device of digital signal, can realize with lower amount of calculation digital signals sampling rate conversion, and make the signal quality that obtains after the conversion higher.
For addressing the above problem, the invention provides a kind of sampling rate converting method of digital signal, this method comprises the steps:
Carry out the cascade transformational analysis earlier, according to input sampling rate f 1With output sampling rate f 2Between integer ratios M: the different situations of N, sample rate conversion is decomposed into the situation of only carrying out integer conversion, only carry out situation and the integer conversion of small conversion and the situation that small conversion is all carried out, be specially
(a) if the factor that M, N can effectively arrange decompose and make M 1* M 2* L * M K=M, N 1* N 2* L * N K=N, and satisfy
f 1 Π i = 1 I N i M i ≥ f 2 , i=1,2,L,K
K>=1,1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, carry out the cascade integer so and change signal sampling rate by f 1Convert f into 2
(b) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|>P Max, carry out so small conversion with signal sampling rate by f 1Convert f into 2, the small transfer ratio f of this moment 1: f 2=M: N=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.
(c) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|≤P Max, look for M 1* M 2* L * M K=M ', N 1* N 2* L * N K=N ' makes | N '/M '-N/M| is minimum, and satisfies the formula in (a), 1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, K>=1 is carried out the cascade integer so and is changed signal sampling rate by f 1Convert f ' into 2, carry out small conversion again with f ' 2Convert f into 2, the small transfer ratio f ' of this moment 2: f 2=MN ': NM '=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.
The building mode of described cascade conversion is by input sampling rate f 1, output sampling rate f 2Size and amount of calculation, demand on signal quality determines jointly: if f 1>f 2, and require amount of calculation little, then small conversion is placed at last; If f 1>f 2, and require the conversion of signals quality good, then be placed on small conversion before; If f 1<f 2, and require amount of calculation little, then be placed on small conversion before; If f 1>f 2, and require the conversion of signals quality good, then small conversion is placed at last; If the progression of integer conversion is greater than 1, small conversion also can be embedded in the integer conversion of cascade, if require the conversion of signals quality good, the sample rate that makes intergrade when making up cascade system so is greater than the target sample rate f 2If require amount of calculation little, the sample rate that makes intergrade when making up cascade system so is less than the target sample rate f 2
For addressing the above problem, the sample rate conversion device that the invention provides a kind of digital signal comprises: cascade transformational analysis module, and in order to according to input sampling rate f 1With output sampling rate f 2Between integer ratios M: the different situations of N, confirm only to carry out the situation of integer conversion, only carry out situation and the integer conversion of small conversion and the situation that small conversion is all carried out; The buffer input signal module is used to store input signal, and input signal is inputed to the integer modular converter or small modular converter is converted to the output signal according to the analysis result of cascade transformational analysis module; The sample rate conversion device of this digital signal also comprises integer conversion configurations module or small conversion configurations module simultaneously; Wherein integer conversion configurations module is in order to make up the integer transition matrix; And small conversion configurations module is in order to be used for the higher order polynomial interpolation small sample rate conversion; Make up small converting vector or matrix; The integer modular converter multiplies each other in order to the integer transition matrix of input signal that the buffer input signal module is carried and integer conversion configurations module construction and accomplishes the integer conversion thus, and the small transition matrix that small modular converter is sent the buffer input signal module to the input signal that comes and the small conversion configurations module construction small conversion of completion of multiplying each other.
Compared with prior art; The present invention is through analyzing the different situations of the integer ratios between input sampling rate and the output sampling rate; Sample rate conversion is decomposed into the situation of only carrying out the integer conversion, only carries out the situation of small conversion and the situation that integer is changed and small conversion is all carried out; And according to the size and the amount of calculation of input sampling rate, output sampling rate; Signal quality decides small conversion, the position of integer conversion in whole sample rate conversion jointly; Make up the cascade conversion input signal is carried out sample rate conversion; Can realize with lower amount of calculation digital signals sampling rate conversion, and make the signal quality that obtains after the conversion higher.
Description of drawings
Fig. 1 is the flow chart of sampling rate converting method of a kind of digital signal of embodiment of the present invention.
Fig. 2 is the cascade function mode sketch map of integer modular converter.
Fig. 3 is the frequency response chart of 1/10 low pass filter.
Fig. 4 is the quick small conversion sketch map of each grade.
Fig. 5 is the best small conversion sketch map of each grade piece output.
Fig. 6 is sparse transition matrix coefficient distribution map.
Fig. 7 is the first cascade conversion regime, and small conversion is at last cascade function mode sketch map.
Fig. 8 is the second cascade conversion regime, the cascade function mode sketch map of small conversion before.
Fig. 9 is that the third level connects conversion regime, and small conversion embeds the cascade function mode sketch map of cascade integer conversion.
Figure 10 A to Figure 10 E is the circuit module Organization Chart of sample rate conversion device of the digital signal of embodiment of the present invention.
Figure 11 is the total harmonic distortion comparison diagram of two kinds of small conversions.
To be three kinds of different sample rate conversion regimes be converted to the signal spectrum figure behind the 44100hz with the sample rate of a sine wave from 32000Hz to Figure 12, wherein exports sinusoidal signal frequency 2000Hz.
To be three kinds of different sample rate conversion regimes be converted to the signal spectrum figure behind the 44100hz with the sample rate of a sine wave from 32000Hz to Figure 13, wherein exports sinusoidal signal frequency 12000Hz.
To be three kinds of different sample rate conversion regimes be converted to the signal time-frequency figure behind the 44100hz with the sample rate of one section music from 32000Hz to Figure 14.
To be three kinds of different sample rate conversion regimes be converted to the spectrogram of the signal synchronization behind the 44100Hz with the sample rate of one section music to Figure 15 from 32000Hz.
Embodiment
Specify below in conjunction with the sampling rate converting method of accompanying drawing a kind of digital signal of embodiment of the present invention.
See also shown in Figure 1ly, Fig. 1 is the flow chart of sampling rate converting method of a kind of digital signal of embodiment of the present invention, comprises following steps:
Step S101, the cascade transformational analysis;
Input sampling rate f 1With output sampling rate f 2Between have integer ratios M: N and make f 2=f 1N/M, wherein M, N do not have further abbreviation of common factor.According to input sampling rate f 1With output sampling rate f 2Between integer ratios M: the different situations of N are decomposed into following three kinds of situation with sample rate conversion:
(a) only carry out the situation of integer conversion: if the factor that M, N can effectively arrange is decomposed and made M 1* M 2* L * M K=M, N 1* N 2* L * N K=N, and satisfy
f 1 Π i = 1 I N i M i ≥ f 2 , I=1,2, L, K (formula 1)
K>=1,1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, carry out the cascade integer so and change signal sampling rate by f 1Convert f into 2
(b) only carry out the situation of small conversion: if M, N can not carry out the factor described in (a) and decompose, but min (M, N)/| M-N|>P Max, carry out so small conversion with signal sampling rate by f 1Convert f into 2, the small transfer ratio f of this moment 1: f 2=M: N=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.
(c) integer conversion and the small conversion situation of all carrying out: if M, N can not carry out the factor decomposition described in (a), but min (M, N)/| M-N|≤P Max, look for M 1* M 2* L * M K=M ', N 1* N 2* L * N K=N ' makes | N '/M '-N/M| is minimum, and satisfies (formula 1), 1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, K>=1 is carried out the cascade integer so and is changed signal sampling rate by f 1Convert f ' into 2, carry out small conversion again with f ' 2Convert f into 2, the small transfer ratio f ' of this moment 2: f 2=MN ': NM '=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.Wherein above-mentioned (a), (b), the P in (c) MaxInterval be [20,30], be generally 20.
If the result of step S101 cascade transformational analysis is for only carrying out the situation of integer conversion, execution in step S102 so, at first carry out cascade integer conversion configurations:
Consider the k level of integer conversion, the frequency inverted ratio of integers of this one-level is M k: N kThe elementary cell of integer conversion is a N k* M kl kInteger transition matrix A k, input signal is placed on M kI kIn the some buffering.It is periodic that the output of integer conversion is calculated, order
Figure BSA00000424969400081
Be buffer input signal,, use A in the j time output of one-period kThe capable x of multiply by of j obtain 1 output signal, upgrade int [jM then k/ N k]-int [(j-1) M k/ N k] individual input, if int [jM k/ N k]-int [(j-1) M k/ N k] be 0, then do not upgrade, accomplish N kIndividual output back j returns the new cycle of 1 beginning.
The integer transition matrix is that the extraction through low pass filter makes up, and the low pass filter vector is h k=[h k(0), h k(1), h k(2), h k(3), h k(4), h k(5), L, h k(M kl kN k-1)], its length is M kl kN k, its stopband attenuation is controlled at about 80 to 100dB, wherein l kThe length that is used for control filters, generally about 30, cut-off frequency is 1/max (M for it k, N k), but, need stay certain redundancy in order to reduce the influence of transition band aliasing, can cut-off frequency be compressed to originally about 0.95 downwards, promptly cut-off frequency is 0.95/max (M k, N k).
Be illustrated in figure 2 as the through transport of integer switching stage and make the mode sketch map, the integer transition matrix A of each grade kBy low pass filter vector h kExtract and obtain
A k = h k ( 0 ) h k ( N k ) h k ( 2 N k ) h k ( 3 N k ) h k ( 4 N k ) L h k ( M k l k N k - N k ) h k ( 1 ) h k ( N k + 1 ) h k ( 2 N k + 1 ) h k ( 3 N k + 1 ) h k ( 4 N k + 1 ) L h k ( M k l k N k + 1 - N k ) h k ( 2 ) h k ( N k + 2 ) h k ( 2 N k + 2 ) h k ( 3 N k + 2 ) h k ( 4 N k + 2 ) L h k ( M k l k N k + 2 - N k ) h k ( 3 ) h k ( N k + 3 ) h k ( 2 N k + 3 ) h k ( 3 N k + 3 ) h k ( 4 N k + 3 ) L h k ( M k l k N k + 3 - N k ) h k ( 4 ) h k ( N k + 4 ) h k ( 2 N k + 4 ) h k ( 3 N k + 4 ) h k ( 4 N k + 4 ) L h k ( M k l k N k + 4 - N k ) M M M M M O M h k ( N k - 1 ) h k ( 2 N k - 1 ) h k ( 3 N k - 1 ) h 4 ( 4 N k - 1 ) h k ( 5 N k - 1 ) L h k ( M k l k N k - 1 )
(formula 2)
Be illustrated in figure 3 as one through the design of 256 Chebyshev window; Frequency response chart with 1/10 low pass filter instance of 90dB stopband attenuation; Wherein fine rule is the prototype filter frequency response that Floating-point Computation obtains, and thick line is the filter freguency response after precision reduces (15 precision).
If the result of step S101 cascade transformational analysis is for only carrying out the situation of small conversion, execution in step S103 so, at first carry out small conversion configurations:
The higher order polynomial interpolation is adopted in small conversion, and the condition that satisfies according to higher order polynomial is different, can be divided into quick small conversion and two kinds of situation of best small conversion, describes respectively below:
(a) quick small conversion
The higher order polynomial function can obtain more level and smooth curve, and n rank polynomial function does
F (x)=a nx n+ a N-1x N-1+ L+a 1X+a 0(formula 3)
Known f (t j)=x j, j=0,1, K, n, coefficient a so 0, a 1, a 2, K, a nCan confirm through matrix form
a n a n - 1 M a 0 = t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n (formula 4)
The functional value y corresponding for unknown t place just can come out through polynomial computation, promptly
y = t n t n - 1 L t 0 a n a n - 1 L a 0 T
= t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n (formula 5)
= w x 0 x 1 L x n T
w = t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 (formula 6)
At this moment functional value y is converted into vectorial w and n+1 point input signal vector multiplies each other, and w and unknown t and input matrix is relevant constantly.
The higher order polynomial interpolation is used for small sample rate conversion, and input signal is an equal interval sampling.In order to obtain more level and smooth function curve and output reliably, to a series of input signal x i, x I+1, x I+2, K need be each [x I-int [n/2], K, x i, x I+1, K, x I+int [n/2+0.5]] set up a function f separately i(x), i.e. segmentation makes up higher order polynomial, obtains a series of w i, and use function f i(x) mid portion [x i, x I+1] curve of section is used for interpolation output.At this moment, absolute i is constantly taken out, the input time matrix can be considered as constant
t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 = ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
(formula 7)
The relative moment of output is t, and t has periodically, and the cycle is s 2, promptly the relative output time of one-period does
t j=js 1/ s 2-int [js 1/ s 2], j=1,2, L, s 2(formula 8)
Corresponding with it w jAlso has periodically w jFor
w j = [ t j n , t j n - 1 , L , t j 1 , 1 ] ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
(formula 9)
Be illustrated in figure 4 as the sketch map of quick small conversion, through w jThe concrete grammar that obtains small converted output signal is: suppose that input signal has the n+1 point, with x=[x 0, x 1, x 2, L, x n] TExpression in the j time output of one-period, is used w jMultiply by x and obtain 1 output signal, upgrade int [js then 1/ s 2]-int [(j-1) s 1/ s 2] individual input, int [js 1/ s 2]-int [(j-1) s 1/ s 2] value be 1 and upgrade 1 input, be 0 and do not upgrade, accomplish s 2Individual output back j returns the new cycle of 1 beginning.
(b) best small conversion
Best small conversion is based on the polynomial interopolation algorithm that divides the intersegmental high-order condition of continuity, and it defines s 1Individual input interval [0,1], [1,2], L, [i, i+1], L, [s 1-1, s 1] corresponding s 1Individual piecewise function f j(x) be polynomial of degree n, wherein the corresponding value x of the i of institute at interval border place iKnown, require f j(x) satisfy following constraints:
(1) for j=1,2, K, s 1, f j(1)=x j, f 1(0)=x 0
(2) for j=1,2, K, s 1,
Figure BSA00000424969400111
Subscript (r) representative function f wherein j(x) r subderivative, r=0,1, K, n-1;
(3) boundary condition satisfies n-1 in following 2 (n-1) set condition
Figure BSA00000424969400112
Figure BSA00000424969400113
R=1, K, n-1, c R1, c R2Be constant, generally can make it is 0;
Consider computational efficiency, generally make function f j(x) be 3 order polynomials, i.e. f j(x)=a kx 3+ b kx 2+ c kX+d kIn a change-over period, input signal overlaps with the head and the tail end points of output signal, i.e. input signal x 0=output signal y 0, input signal
Figure BSA00000424969400114
Output signal y 0,
Figure BSA00000424969400115
Between point utilize they input interval [0, s 1] in relative position and f j(x) obtain.Consider s 1, s 2Known and fixing, output signal input interval [0, s 1] in the absolute position [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] also known and fixing, small conversion can convert a row input signal x and a s into 2* (s 1+ 1) sparse transition matrix B multiplies each other and obtains the process of a row output signal y, sparse transition matrix B only with s 1, s 2And f j(x) the column constraint condition that is satisfied is relevant.
The concrete computational process of sparse transition matrix B is: at first calculate relative output time t=[t 0, t 1, L, t S2]=[0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1]-int [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] (formula 10) sparse transition matrix B is the part of matrix Q, Q takes advantage of acquisition by the anti-phase of location matrix T and conditional matrix C, i.e. Q=TC -, Q is s 2* (n+1) s 1Matrix, sparse transition matrix B are the preceding s of Q 1+ 1 row, T is s 2* (n+1) s 1Matrix, C are (n+1) s 1* (n+1) s 1Matrix.T is specially
[ t 0 n , L , t 0 2 , t 0 1 , 1 ] 0.0 0 [ t 1 n , L , t 1 2 , t 1 1 , 1 ] 1 , int [ s 1 / s 2 ] O 0 [ t s 2 - 1 n , L , t s 2 - 1 2 , t s 2 - 1 1 , 1 ] s 2 , s 1 S 2 × ( n + 1 ) s 1
(formula 11)
Its reality is by 1 * (n+1) vector Constitute s as an integral unit 2* s 1Quasi-diagonal matrix,
Figure BSA00000424969400123
The position at the capable int [js of j 1/ s 2] row, int [] expression rounds.C specifically is made up of the n+1 sub-matrices
C = C 0 C 1 C 2 M C n C n + 1 (formula 12)
C wherein 0Be (s 1+ 1) * (s 1(n+1)) matrix, C 1..., C nBe (s 1-1) * (s 1(n+1)) matrix, C N+1Be (n-2) * (s 1(n+1)) matrix, C 0Corresponding f j(x) constraints (1) is specially
0 1 × n 1 0 1 × n 1 O 0 1 × n 1 0 1 × n 1 0 1 × n 1 (formula 13)
C j, j=1,2, L, the corresponding f of n j(x) constraints (2), for
[ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 O O [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0
(formula 14)
Wherein
[x n, x N-1, L, 1] (j) v(formula 15)
Expression
x n, x N-1, L, 1 (formula 16)
In the j at v place subderivative
C N+1Corresponding f j(x) constraints (3) can be chosen wantonly
Figure BSA00000424969400133
Figure BSA00000424969400134
R=1,2, L, the n-1 in this 2 (n-1) set condition of n-1, if select
Figure BSA00000424969400135
As C N+1In the capable condition of k, C so N+1In the k behavior
[[x n, x N-1, L, 1] (r) 0, 0] and (formula 17)
If select
Figure BSA00000424969400141
As C N+1In the capable condition of k, C so N+1In the k behavior
[0, [x n, x N-1, L, 1] (r) 1] (formula 18)
Sparse transition matrix B does
Q = T C - = [ B s 2 × ( s 1 + 1 ) , D s 2 × ( Ns 1 - 1 ) ] s 2 × ( n + 1 ) s 1 (formula 19)
Be illustrated in figure 5 as the best small conversion sketch map of each grade piece output, the concrete grammar that obtains the output signal of small conversion through sparse transition matrix B is: suppose that input signal has s 1+ 1 point upgrades s at every turn 1The point input signal, output s 2The point signal, then
y s 2 × 1 = [ y 0 , y 1 , y 2 , L , y s 2 - 1 ] T = Bx ( s 1 + 1 ) × 1 = B [ x 0 , x 1 , x 2 , L , x s 1 ] T (formula 20)
Consider the characteristic of sparse matrix, this part output procedure can be revised as pointwise output, and buffer length at this moment reduces, and needs pointwise to upgrade.
Because sparse transition matrix B has only diagonal finite element non-zero (look the data precision decision of calculating required reservation, every row is about 10 to 16 nonzero elements) on every side, promptly B is a sparse matrix, and the memory space of B will be much smaller than s 2* (s 1+ 1), the amount of calculation of the matrix multiplication of it and input buffering simultaneously also will be much smaller than s 2* (s 1+ 1).Be illustrated in figure 6 as s 1=40, s 2=41, n=3, the coefficient distribution map of the sparse transition matrix after 15 quantifications, wherein black partly is 0, has only in leftmost 41 * 41 the submatrix diagonal angle subparticipation output to calculate.
If the result of step S101 cascade transformational analysis is the situation that integer is changed and small conversion is all carried out, execution in step S104 makes up the cascade conversion signal is carried out sample rate conversion so.
The cascade system of sample rate conversion is by input sampling rate f 1, output sampling rate f 2Size and amount of calculation, the conversion of signals quality determines jointly, and is specific as follows:
(1) if f 1>f 2, and require amount of calculation little, and then small conversion is placed at last, as shown in Figure 7;
(2) if f 1>f 2, and require the conversion of signals quality good, then be placed on small conversion before, as shown in Figure 8;
If f 1<f 2, and require amount of calculation little, then be placed on small conversion before, as shown in Figure 8;
(4) if f 1<f 2, and require the conversion of signals quality good, and then small conversion is placed at last, as shown in Figure 7;
(5) small conversion also can be embedded in the integer conversion of cascade (progression of integer conversion is greater than 1), and is as shown in Figure 9, if require the conversion of signals quality good, can design so make intergrade sample rate greater than the target sample rate f 2If require amount of calculation little, can design so make intergrade sample rate less than the target sample rate f 2
Figure 10 is the circuit module figure of sample rate conversion device of a kind of digital signal of embodiment of the present invention, and the function declaration of each module that it comprises is following:
Cascade transformational analysis module 201: according to input sampling rate f 1With output sampling rate f 2Between integer ratios M: the different situations of N, for only carrying out the situation of integer conversion, only carry out situation and the integer conversion of small conversion and the situation that small conversion is all carried out;
Buffer input signal module 202: be used to store input signal, and input signal is sent into integer modular converter or small modular converter be converted to the output signal;
Integer conversion configurations module 203: make up the integer transition matrix;
Integer modular converter 204; The integer transition matrix of the buffer input signal module being sent to the input signal that comes and integer conversion configurations module construction multiplies each other and accomplishes integer conversion;
Small conversion configurations module 205: the higher order polynomial interpolation is used for small sample rate conversion, makes up small converting vector or matrix;
Small modular converter 206: the small transition matrix of the buffer input signal module being sent to the input signal that comes and the small conversion configurations module construction small conversion of completion of multiplying each other;
201 pairs of sample rate conversion of cascade transformational analysis module are decomposed, and sample rate conversion is decomposed into the situation of only carrying out the integer conversion, only carry out the situation of small conversion and the situation that integer is changed and small conversion is all carried out, and are specially:
(a) if the factor that M, N can effectively arrange decompose and make M 1* M 2* L * M K=M, N 1* N 2* L * N K=N, and satisfy
f 1 Π i = 1 I N i M i ≥ f 2 , I=1,2,L,K
K>=1,1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, carry out the cascade integer so and change signal sampling rate by f 1Convert f into 2
(b) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|>P Max, carry out so small conversion with signal sampling rate by f 1Convert f into 2, the small transfer ratio f of this moment 1: f 2=M: N=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.
(c) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|≤P Max, look for M 1* M 2* L * M K=M ', N 1* N 2* L * N K=N ' makes | N '/M '-N/M| is minimum, and satisfies the formula in (a), 1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, K>=1 is carried out the cascade integer so and is changed signal sampling rate by f 1Convert f ' into 2, carry out small conversion again with f ' 2Convert f into 2, the small transfer ratio f ' of this moment 2: f 2=MN ': NM '=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.Wherein (a), (b), the P in (c) MaxInterval be [20,30], be generally 20.
Integer conversion configurations module 203 makes up the integer transition matrix, and the integer transition matrix of each grade is to make up through the vectorial extraction of low pass filter, and the frequency inverted ratio of integers of the k level of integer conversion is M k: N k, integer transition matrix A kBe that a size is N k* M kl kMatrix, be expressed from the next:
A k = h k ( 0 ) h k ( N k ) h k ( 2 N k ) h k ( 3 N k ) h k ( 4 N k ) L h k ( M k l k N k - N k ) h k ( 1 ) h k ( N k + 1 ) h k ( 2 N k + 1 ) h k ( 3 N k + 1 ) h k ( 4 N k + 1 ) L h k ( M k l k N k + 1 - N k ) h k ( 2 ) h k ( N k + 2 ) h k ( 2 N k + 2 ) h k ( 3 N k + 2 ) h k ( 4 N k + 2 ) L h k ( M k l k N k + 2 - N k ) h k ( 3 ) h k ( N k + 3 ) h k ( 2 N k + 3 ) h k ( 3 N k + 3 ) h k ( 4 N k + 3 ) L h k ( M k l k N k + 3 - N k ) h k ( 4 ) h k ( N k + 4 ) h k ( 2 N k + 4 ) h k ( 3 N k + 4 ) h k ( 4 N k + 4 ) L h k ( M k l k N k + 4 - N k ) M M M M M O M h k ( N k - 1 ) h k ( 2 N k - 1 ) h k ( 3 N k - 1 ) h 4 ( 4 N k - 1 ) h k ( 5 N k - 1 ) L h k ( M k l k N k - 1 )
Wherein, the low pass filter vector is h k=[h k(0), h k(1), h k(2), h k(3), h k(4), h k(5), L, h k(M kl kN k-1)], its length is M kl kN k, its stopband attenuation is controlled at about 80 to 100dB; l kThe length that is used for control filters, general value is about 30, cut-off frequency is 1/max (M k, N k).But in order to reduce the influence of transition band aliasing, need stay certain redundancy, can cut-off frequency be compressed to originally about 0.95 downwards, promptly cut-off frequency is 0.95/max (M k, N k).
Be depicted as the through transport of integer switching stage like Figure 10 A and make the mode sketch map, the conversion of the integer of each grade obtains exporting the signal realization through input signal and integer transition matrix are multiplied each other, and its detailed process is:
The calculating of integer converted output signal is periodic, if each input signal of participating in calculating has M kl kPoint is used
Figure BSA00000424969400181
Expression is stored in the input buffering module 202, in the j time output of one-period, with integer transition matrix A kThe capable x of multiply by of j obtain 1 output signal, upgrade int [jN then k/ M k]-int [(j-1) N k/ M k] individual input, if int [jM k/ N k]-int [(j-1) M k/ N k] be 0, then do not upgrade, accomplish N kIndividual output back j returns the new calculating of 1 beginning.
Small conversion configurations module 205 adopts the higher order polynomial interpolation to make up small transition matrix or vector, and the condition that satisfies based on higher order polynomial is different, can be divided into quick small conversion and two kinds of situation of best small conversion.
If adopt the higher order polynomial interpolation, and input signal is equal interval sampling, and so small conversion configurations module 205 adopts quick small conversion, makes up small converting vector w j, its computational methods are:
In order to obtain more level and smooth function curve and output reliably, to a series of input signal x i, x I+1, x I+2, L need be each [x I-int [n/2], L, x i, x I+1, L, x I+int [n/2+0.5]] set up a function f separately i(x), i.e. segmentation makes up higher order polynomial, obtains a series of vectorial w i, and use function f i(x) mid portion [x i, x I+1] curve of section is used for interpolation output, then absolute i constantly taken out, input matrix constantly can be regarded as constant
t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 = ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
The relative moment of output then is t=is 1/ s 2-int [is 1/ s 2], t has periodically, and the cycle is s 2, promptly the relative output time of one-period does
t j=js 1/s 2-int[js 1/s 2],j=1,2,L,s 2
The vectorial w that it is corresponding jAlso has periodically w jFor
w j = [ t j n , t j n - 1 , L , t j 1 , 1 ] ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
N rank polynomial function does
f(x)=a nx n+a n-1x n-1+L+a 1x+a 0
Known f (t j)=x j, j=0,1, K, n, coefficient a so 0, a 1, a 2, K, a nCan confirm through matrix form
a n a n - 1 M a 0 = t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n
The functional value y corresponding for unknown t place just can come out through polynomial computation, promptly
y = t n t n - 1 L t 0 a n a n - 1 L a 0 T
= t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n
= w x 0 x 1 L x n T
w = t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1
At this moment functional value y is converted into vectorial w and n+1 point input signal vector multiplies each other, and w and unknown t and input matrix is relevant constantly.
Be depicted as small transition operation mode sketch map like Figure 10 B, small modular converter wherein obtains exporting signal through input signal and small converting vector are multiplied each other and realizes that its detailed process is: input signal has the n+1 point, with x=[x 0, x 1, x 2, L, x n] TExpression is stored in the input buffering module 202, in the j time output of one-period, with small converting vector w jMultiply by x and obtain 1 output signal, upgrade int [js then 1/ s 2]-int [(j-1) s 1/ s 2] individual input, int [js 1/ s 2]-int [(j-1) s 1/ s 2] value be 1 and upgrade 1 input, be 0 and do not upgrade, accomplish s 2Individual output back j returns the new cycle of 1 beginning.
If adopt based on the polynomial interopolation algorithm that divides the intersegmental high-order condition of continuity, 205 of so small conversion configurations moulds adopt best small conversion, make up small transition matrix; This algorithm definition s 1Individual input interval [0,1], [1,2], L, [i, i+1], L, [s 1-1, s 2] corresponding s 1Individual piecewise function f j(x) be polynomial of degree n, wherein the corresponding value x of the i of institute at interval border place iKnown, require f j(x) satisfy following constraints:
(1) for j=1,2, K, s 1, f j(1)=x j, f 1(0)=x 0
(2) for j=1,2, K, s 1-1,
Figure BSA00000424969400201
Subscript (r) representative function f wherein j(x) r subderivative, r=0,1, K, n-1;
(3) boundary condition satisfies n-1 in following 2 (n-1) set condition
Figure BSA00000424969400202
Figure BSA00000424969400203
R=1, K, n-1, c R1, c R2Be constant, generally can make it is 0.
Piecewise function f j(x) be generally 3 order polynomials, i.e. f j(x)=a kx 3+ b kx 2+ c kX+d kIn a change-over period, input signal overlaps with the head and the tail end points of output signal, i.e. input signal x 0=output signal y 0, input signal
Figure BSA00000424969400204
Output signal y 0,
Figure BSA00000424969400205
Between point utilize they input interval [0, s 1] in relative position and f j(x) obtain.Consider s 1, s 2Known and fixing, output signal input interval [0, s 1] in the absolute position [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] also known and fixing, small conversion can convert a row input signal x and a s into 2* (s 1+ 1) sparse transition matrix B multiplies each other and obtains the process of a row output signal y, sparse transition matrix B only with s 1, s 2And f j(x) the column constraint condition that is satisfied is relevant.
The concrete computational process of sparse transition matrix B is:
At first calculate relative output time
T=[t 0, t 1, L, t S2]=[0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1]-int [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] sparse transition matrix B is the part of matrix Q, Q takes advantage of acquisition by the anti-phase of location matrix T and conditional matrix C, i.e. Q=TC -, Q is s 2* (n+1) s 1Matrix, sparse transition matrix B are the preceding s of Q 1+ 1 row, T is s 2* (n+1) s 1Matrix, C are (n+1) s 1* (n+1) s 1Matrix;
T representes with following formula:
[ t 0 n , L , t 0 2 , t 0 1 , 1 ] 0.0 0 [ t 1 n , L , t 1 2 , t 1 1 , 1 ] 1 , int [ s 1 / s 2 ] O 0 [ t s 2 - 1 n , L , t s 2 - 1 2 , t s 2 - 1 1 , 1 ] s 2 , s 1 S 2 × ( n + 1 ) s 1
Its reality is by 1 * (n+1) vector
Figure BSA00000424969400212
Constitute s as an integral unit 2* s 1Quasi-diagonal matrix,
Figure BSA00000424969400213
The position at the capable int [js of j 1/ s 2] row, int [] expression rounds;
C is made up of the n+1 sub-matrices
C = C 0 C 1 C 2 M C n C n + 1
C wherein 0Be (s 1+ 1) * (s 1(n+1)) matrix, C 1..., C nBe (s 1-1) * (s 1(n+1)) matrix, C N+1Be (n-2) * (s 1(n+1)) matrix,
C 0Corresponding f j(x) constraints (1) is expressed from the next:
0 1 × n 1 0 1 × n 1 O 0 1 × n 1 0 1 × n 1 0 1 × n 1
C j, j=1,2, L, the corresponding f of n j(x) constraints (2) is expressed from the next:
[ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 O O [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0
[x wherein n, x N-1, L, 1] (j) vExpression x n, x N-1, L, 1 in the j at v place subderivative;
C N+1Corresponding f j(x) constraints (3) can be chosen wantonly
Figure BSA00000424969400223
Figure BSA00000424969400224
R=1,2, L, the n-1 in this 2 (n-1) set condition of n-1, if select As C N+1In the capable condition of k, C so N+1In the k behavior
[[x n,x n-1,L,1] (r) 0,0]
If select As C N+1In the capable condition of k, C so N+1In the k behavior
[0,[x n,x n-1,L,1] (r) 1]
Sparse transition matrix B does
Q = T C - = [ B s 2 × ( s 1 + 1 ) , D s 2 × ( ns 1 - 1 ) ] s 2 × ( n + 1 ) s 1
Be depicted as small transition operation mode sketch map like Figure 10 B, small modular converter wherein obtains exporting signal through sparse transition matrix B and input signal are multiplied each other and realizes that its concrete grammar is:
Input signal has s 1+ 1 point upgrades s at every turn 1The point input signal, output s 2The point signal
y s 2 × 1 = [ y 0 , y 1 , y 2 , L , y s 2 - 1 ] T = B x ( s 1 + 1 ) × 1 = B [ x 0 , x 1 , x 2 , L , x s 1 ] T
Consider the characteristic of sparse matrix, this part output procedure can be revised as pointwise output, and buffer length at this moment reduces, and needs pointwise to upgrade.
The analysis result of cascade transformational analysis module 201 is integer conversion when all carrying out with small conversion, and the connected mode that cascade is changed is by input sampling rate f 1, output sampling rate f 2Size and amount of calculation, demand on signal quality determines jointly.
(1) if f 1>f 2, and require amount of calculation little, then small conversion is placed at last, shown in Figure 10 C;
(2) if f 1>f 2, and require the conversion of signals quality good, then be placed on small conversion before, shown in Figure 10 D;
(3) if f 1<f 2, and require amount of calculation little, then be placed on small conversion before, shown in Figure 10 D;
(4) if f 1>f 2, and require the conversion of signals quality good, then small conversion is placed at last, shown in Figure 10 C;
(5) small conversion also can be embedded in the integer conversion of cascade, and shown in Figure 10 E, and the progression of integer conversion is greater than 1, if require the conversion of signals quality good, the sample rate that makes intergrade when making up cascade system so is greater than the target sample rate f 2If require amount of calculation little, the sample rate that makes intergrade when making up cascade system so is less than the target sample rate f 2
Forwarding the signal of 32000Hz to 44100Hz is processing common in the digital audio processing, the M that signal sampling rate is corresponding, and N is respectively 320,441.If adopt traditional bank of filters mode; The length of filter is that (if require excess bandwidth is 1/10 of passband to 320 * 441 * l; L must be greater than 20 so), so long filter, each sample mean consumes 320l multiplication; Per second consumes 44100 * 320l time multiplication, and the height of this amount of calculation almost is unacceptable.
And employing the present invention forwards the signal of 32000Hz to 44100Hz, and the signal that can change into 32000Hz forwards 44000Hz to; The conversion of use integer, corresponding M ', N ' is respectively 8; 11, the length of filter is 8 * 11 * l, and per second consumes 44000 * 8l time multiplication; Small conversion is transformed into 44100Hz with 44000Hz, s in the cascade 1, s 2Be respectively 440,441, if adopt quick small conversion (3 rank), per second consumes multiplication approximately 44100 * 4 times so, if adopt best small conversion (3 rank), per second consumes multiplication approximately 44100 * 12 times.After the cascade altogether per second consume 44000 * 8l+44000 * 4 time multiplication or 44000 * 8l+44000 * 12 time multiplication, be far smaller than and adopt the conventional filter group of methods.
Quick small conversion provides different switching signal quality with best small conversion, and this quality is mainly weighed with harmonic distortion.Total harmonic wave harmonic distortion is defined as input sine wave, the size of the relative incoming frequency component of harmonic component in the output signal, and total harmonic wave harmonic distortion is big more, and harmonic component is strong more, and distorted signals is big more.Figure 11 has provided quick small conversion (3 rank) and best small conversion (3 rank) under different input frequency signal situation, and signal is transformed into the total harmonic distortion (dB metering) behind the 44100Hz from 44000Hz.Harmonic distortion (solid line among the figure) all faster small conversion (dotted line among the figure) on all frequencies that can see best small conversion has certain advantage, the quick relatively small conversion of best small conversion, and signal fidelity is higher.
Figure 12 and Figure 13 have provided three kinds of different sample rate conversion regimes the sample rate of a sine wave have been converted to the signal spectrum figure behind the 44100hz from 32000Hz; The output sinusoidal signal frequency 2000Hz of Figure 12 wherein; The output sinusoidal signal frequency 12000Hz of Figure 13; The left side is the method (method 1) that directly adopts cubic curve property interpolation among two figure; The centre is the method (method 2) that the conversion of cascade integer combines quick small conversion, and the right is the method (method 3) that the conversion of cascade integer combines best small conversion.Can see from Figure 12; Method 1 has a large amount of harmonic waves and noise profile on frequency axis; The harmonic wave of method 2 and noise have had certain decay away from center signal the time, the harmonic wave of method 3 and noise are decayed away from center signal the time fast, and its harmonic wave and noise also are less than method 2.Can see that from Figure 13 harmonic wave and noise have increase tendency, method 1 is available hardly, and the harmonic wave of method 2 and noise are also bigger, and method 3 can provide relative higher signal quality.
Figure 14 and Figure 15 have provided three kinds of different sample rate conversion regimes the sample rate of one section music have been converted to signal time-frequency figure and the spectrogram of signal synchronization behind the 44100hz from 32000Hz; The left side is the method (method 1) that directly adopts cubic curve property interpolation among Figure 14; The centre is the method (method 2) that the conversion of cascade integer combines quick small conversion, and the right is the method (method 3) that the conversion of cascade integer combines best small conversion.Light ash among Figure 15, the signal after dark-grey and black difference corresponding method 1, method 2 are handled with method 3.Can see from Figure 14; The much noise disperse that method 1 is produced is on whole frequency axis; Seriously reduced signal quality; Method 2 and method 3 have all been controlled the diffusion of noise well at stopband (16kHz is to 22kHz), and this also has good embodiment in Figure 15, and wherein method 3 is littler at the noise of stopband.Actual audition shows that method 3 will have higher fidelity than method 2.
Compared with prior art; The present invention is through analyzing the different situations of the integer ratios between input sampling rate and the output sampling rate; Sample rate conversion is decomposed; And make up the cascade conversion according to the size of quality requirement and input sampling rate, output sampling rate the sample rate of input signal is transformed, can realize with lower amount of calculation digital signals sampling rate conversion, and make the signal quality that obtains after the conversion higher.
It is understandable that, concerning those of ordinary skills, can be equal to replacement or change according to technical scheme of the present invention and inventive concept thereof, and all these changes or replacement all should belong to the protection range of the appended claim of the present invention.

Claims (36)

1. the sampling rate converting method of a digital signal is characterized in that this method comprises the steps:
Carry out the cascade transformational analysis earlier, according to input sampling rate f 1With output sampling rate f 2Between integer ratios M: the different situations of N, sample rate conversion is decomposed into the situation of only carrying out integer conversion, only carries out situation and the integer conversion of small conversion and the situation that small conversion is all carried out, be specially:
(a) if the factor that M, N can effectively arrange decompose and make M 1* M 2* L * M K=M, N 1* N 2* L * N K=N, and satisfy:
f 1 Π i = 1 I N i M i ≥ f 2 , i=1,2,L,K
K>=1,1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, carry out the cascade integer so and change signal sampling rate by f 1Convert f into 2
(b) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|>P Max, carry out so small conversion with signal sampling rate by f 1Convert f into 2, the small transfer ratio f of this moment 1: f 2=M: N=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor;
(c) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|≤P Max, look for M 1* M 2* L * M K=M ', N 1* N 2* L * N K=N ' makes | N '/M '-N/M| is minimum, and satisfies the formula in (a), 1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, K>=1 is carried out the cascade integer so and is changed signal sampling rate by f 1Convert f ' into 2, carry out small conversion again with f ' 2Convert f into 2, the small transfer ratio f ' of this moment 2: f 2=MN ': NM '=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.
2. the sampling rate converting method of digital signal as claimed in claim 1 is characterized in that: described parameter P MaxInterval be [20,30], its representative value is 20.
3. the sampling rate converting method of digital signal as claimed in claim 1 is characterized in that: described execution cascade integer conversion with signal sampling rate by input sampling rate f 1Convert output sampling rate f into 2, each grade integer conversion obtains exporting the signal realization through input signal and integer transition matrix are multiplied each other, and its detailed process is:
The calculating of integer converted output signal is periodic, if each input signal of participating in calculating has M kl kPoint is used
Figure FSA00000424969300021
Expression is in the j time output of one-period, with integer transition matrix A kThe capable x of multiply by of j obtain 1 output signal, upgrade int [jM then k/ N k]-int [(j-1) M k/ N k] individual input, if int [jM k/ N k]-int [(j-1) M k/ N k] be 0, then do not upgrade, accomplish N kIndividual output back j returns the new calculating of 1 beginning.
4. the sampling rate converting method of digital signal as claimed in claim 3 is characterized in that: the integer transition matrix of described each grade is that the extraction through the low pass filter vector makes up, and the frequency inverted ratio of integers of the k level of integer conversion is M k: N k, integer transition matrix A kBe that a size is N k* M kl kMatrix, be expressed from the next:
A k = h k ( 0 ) h k ( N k ) h k ( 2 N k ) h k ( 3 N k ) h k ( 4 N k ) L h k ( M k l k N k - N k ) h k ( 1 ) h k ( N k + 1 ) h k ( 2 N k + 1 ) h k ( 3 N k + 1 ) h k ( 4 N k + 1 ) L h k ( M k l k N k + 1 - N k ) h k ( 2 ) h k ( N k + 2 ) h k ( 2 N k + 2 ) h k ( 3 N k + 2 ) h k ( 4 N k + 2 ) L h k ( M k l k N k + 2 - N k ) h k ( 3 ) h k ( N k + 3 ) h k ( 2 N k + 3 ) h k ( 3 N k + 3 ) h k ( 4 N k + 3 ) L h k ( M k l k N k + 3 - N k ) h k ( 4 ) h k ( N k + 4 ) h k ( 2 N k + 4 ) h k ( 3 N k + 4 ) h k ( 4 N k + 4 ) L h k ( M k l k N k + 4 - N k ) M M M M M O M h k ( N k - 1 ) h k ( 2 N k - 1 ) h k ( 3 N k - 1 ) h 4 ( 4 N k - 1 ) h k ( 5 N k - 1 ) L h k ( M k l k N k - 1 )
Wherein, the low pass filter vector is h k=[h k(0), h k(1), h k(2), h k(3), h k(4), h k(5), L, h k(M kl kN k-1)], its length is M kl kN k, its stopband attenuation is controlled at about 80 to 100dB; l kThe length that is used for control filters, general value is about 30, cut-off frequency is 1/max (M k, N k).
5. the sampling rate converting method of digital signal as claimed in claim 1, it is characterized in that: quick small conversion is adopted in described small conversion, with signal sampling rate by input sampling rate f 1Convert output sampling rate f into 2, obtain exporting signal through input signal and quick small converting vector are multiplied each other and realize that its detailed process is:
Input signal has the n+1 point, with x=[x 0, x 1, x 2, L, x n] TExpression is in the j time output of one-period, with quick small converting vector w jMultiply by x and obtain 1 output signal, upgrade int [js then 1/ s 2]-int [(j-1) s 1/ s 2] individual input, int [js 1/ s 2]-int [(j-1) s 1/ s 2] value be 1 and upgrade 1 input, be 0 and do not upgrade, accomplish s 2Individual output back j returns the new cycle of 1 beginning.
6. the sampling rate converting method of digital signal as claimed in claim 5 is characterized in that: if adopt the higher order polynomial interpolation, and input signal is equal interval sampling, so quick small converting vector w jCalculate through following method:
In order to obtain more level and smooth function curve and output reliably, to a series of input signal x i, x I+1, x I+2, L need be each [x I-int [n/2], L, x i, x I+1, L, x I+int [n/2+0.5]] set up a function f separately i(x), i.e. segmentation makes up higher order polynomial, obtains a series of vectorial w i, and use function f i(x) mid portion [x i, x I+1] curve of section is used for interpolation output, then absolute i constantly taken out, input matrix constantly can be regarded as constant;
t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 = ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
The relative moment of output then is t=is 1/ s 2-int [is 1/ s 2], t has periodically, and the cycle is s 2, promptly the relative output time of one-period is:
t j=js 1/s 2-int[js 1/s 2],j=1,2,L,s 2
The vectorial w that it is corresponding jAlso has periodically w jFor:
w j = [ t j n , t j n - 1 , L , t j 1 , 1 ] ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
7. the sampling rate converting method of digital signal as claimed in claim 6 is characterized in that: described vectorial w i, w jThe calculating principle be:
N rank polynomial function does
f(x)=a nx n+a n-1x n-1+L+a 1x+a 0
Known f (t j)=x j, j=0,1, K, n, coefficient a so 0, a 1, a 2, K, a nCan confirm through matrix form:
a n a n - 1 M a 0 = t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n
The functional value y corresponding for unknown t place just can come out through polynomial computation, promptly
y = t n t n - 1 L t 0 a n a n - 1 L a 0 T
= t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n
= w x 0 x 1 L x n T
w = t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1
At this moment functional value y is converted into vectorial w and n+1 point input signal vector multiplies each other, and w and unknown t and input matrix is relevant constantly.
8. the sampling rate converting method of digital signal as claimed in claim 1, it is characterized in that: best small conversion is adopted in described small conversion, with signal sampling rate by input sampling rate f 1Convert output sampling rate f into 2, obtain exporting signal through the sparse transition matrix B of the small conversion of the best and input signal are multiplied each other and realize that its concrete grammar is:
Input signal has s 1+ 1 point upgrades s at every turn 1The point input signal, output s 2The point signal
Figure FSA00000424969300055
and the concrete computational process of described sparse transition matrix B are:
At first calculate relative output time
T=[t 0, t 1, L, t S2]=[0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1]-int [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] sparse transition matrix B is the part of matrix Q, Q takes advantage of acquisition by the anti-phase of location matrix T and conditional matrix C, i.e. Q=TC -, Q is s 2* (n+1) s 1Matrix, sparse transition matrix B are the preceding s of Q 1+ 1 row,
T is s 2* (n+1) s 1Matrix, C are (n+1) s 1* (n+1) s 1Matrix;
T representes with following formula:
[ t 0 n , L , t 0 2 , t 0 1 , 1 ] 0.0 0 [ t 1 n , L , t 1 2 , t 1 1 , 1 ] 1 , int [ s 1 / s 2 ] O 0 [ t s 2 - 1 n , L , t s 2 - 1 2 , t s 2 - 1 1 , 1 ] s 2 , s 1 S 2 × ( n + 1 ) s 1
Its reality is by 1 * (n+1) vector
Figure FSA00000424969300062
Constitute s as an integral unit 2* s 1Quasi-diagonal matrix, The position at the capable int [js of j 1/ s 2] row, int [] expression rounds;
C is made up of the n+1 sub-matrices
C = C 0 C 1 C 2 M C n C n + 1
C wherein 0Be (s 1+ 1) * (s 1(n+1)) matrix, C 1..., C nBe (s 1-1) * (s 1(n+1)) matrix, C N+1Be (n-2) * (s 1(n+1)) matrix,
C 0Corresponding f j(x) constraints (1) is expressed from the next:
0 1 × n 1 0 1 × n 1 O 0 1 × n 1 0 1 × n 1 0 1 × n 1
C j, j=1,2, L, the corresponding f of n j(x) constraints (2) is expressed from the next:
[ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 O O [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0
[x wherein n, x N-1, L, 1] (j) rExpression x n, x N-1, L, 1 in the j at v place subderivative;
C N+1Corresponding f j(x) constraints (3) can be chosen wantonly
Figure FSA00000424969300072
Figure FSA00000424969300073
R=1,2, L, the n-1 in this 2 (n-1) set condition of n-1, if select As C N+1In the capable condition of k, C so N+1In the k behavior
[[x n,x n-1,L,1] (r) 0,0]
If select
Figure FSA00000424969300075
As C N+1In the capable condition of k, C so N+1In the k behavior
[0,[x n,x n-1,L,1] (r) 1]
Sparse transition matrix B does
Q = T C - = [ B s 2 × ( s 1 + 1 ) , D s 2 × ( ns 1 - 1 ) ] s 2 × ( n + 1 ) s 1 .
9. the sampling rate converting method of digital signal as claimed in claim 8 is characterized in that, described output signal carries out pointwise to be upgraded.
10. the sampling rate converting method of digital signal as claimed in claim 9 is characterized in that: described small conversion is adopted based on the polynomial interopolation algorithm that divides the intersegmental high-order condition of continuity, and it defines s 1Individual input interval [0,1], [1,2], L, [i, i+1], L, [s 1-1, s 1] corresponding s 1Individual piecewise function f j(x) be polynomial of degree n, wherein the corresponding value x of the i of institute at interval border place iKnown, require f j(x) satisfy following constraints:
(1) for j=1,2, K, s 1, f j(1)=x j, f 1(0)=x 0
(2) for j=1,2, K, s 1-1,
Figure FSA00000424969300081
Subscript (r) representative function f wherein j(x) r subderivative, r=0,1, K, n-1;
(3) boundary condition satisfies n-1 in following 2 (n-1) set condition
Figure FSA00000424969300082
Figure FSA00000424969300083
R=1, K, n-1, c R1, c R2Be constant, generally can make it is 0.
11. the sampling rate converting method of digital signal as claimed in claim 10 is characterized in that: described piecewise function f j(x) be generally 3 order polynomials, i.e. f j(x)=a kx 3+ b kx 2+ c kX+d kIn a change-over period, input signal overlaps with the head and the tail end points of output signal, i.e. input signal x 0=output signal y 0, input signal
Figure FSA00000424969300084
Output signal y 0,
Figure FSA00000424969300085
Between point utilize they input interval [0, s 1] in relative position and f j(x) obtain.Consider s 1, s 2Known and fixing, output signal input interval [0, s 1] in the absolute position [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] also known and fixing, small conversion can convert a row input signal x and a s into 2* (s 1+ 1) sparse transition matrix B multiplies each other and obtains the process of a row output signal y, sparse transition matrix B only with s 1, s 2And f j(x) the column constraint condition that is satisfied is relevant.
12. the sampling rate converting method of digital signal as claimed in claim 1 is characterized in that: the building mode of described cascade conversion is by input sampling rate f 1, output sampling rate f 2Size and amount of calculation, demand on signal quality determines jointly.
13. the sampling rate converting method of digital signal as claimed in claim 12 is characterized in that: if f 1>f 2, and require amount of calculation little, then small conversion is placed at last.
14. the sampling rate converting method of digital signal as claimed in claim 12 is characterized in that: if f 1>f 2, and require the conversion of signals quality good, then be placed on small conversion before.
15. the sampling rate converting method of digital signal as claimed in claim 12 is characterized in that: if f 1<f 2, and require amount of calculation little, then be placed on small conversion before.
16. the sampling rate converting method of digital signal as claimed in claim 12 is characterized in that: if f 1>f 2, and require the conversion of signals quality good, then small conversion is placed at last.
17. the sampling rate converting method of digital signal as claimed in claim 12; It is characterized in that: small conversion also can be embedded in the integer conversion of cascade; And the progression of integer conversion is greater than 1; If require the conversion of signals quality good, the sample rate that makes intergrade when making up cascade system so is greater than the target sample rate f 2If require amount of calculation little, the sample rate that makes intergrade when making up cascade system so is less than the target sample rate f 2
18. the sample rate conversion device of a digital signal is characterized in that it comprises: cascade transformational analysis module, in order to according to input sampling rate f 1With output sampling rate f 2Between integer ratios M: the different situations of N, confirm only to carry out the situation of integer conversion, only carry out situation and the integer conversion of small conversion and the situation that small conversion is all carried out; The buffer input signal module is used to store input signal, and input signal is inputed to the integer modular converter or small modular converter is converted to the output signal according to the analysis result of cascade transformational analysis module; The sample rate conversion device of this digital signal also comprises integer conversion configurations module or small conversion configurations module simultaneously; Wherein integer conversion configurations module is in order to make up the integer transition matrix; And small conversion configurations module is in order to be used for the higher order polynomial interpolation small sample rate conversion; Make up small converting vector or matrix; The integer modular converter multiplies each other in order to the integer transition matrix of input signal that the buffer input signal module is carried and integer conversion configurations module construction and accomplishes the integer conversion thus, and the small transition matrix that small modular converter is sent the buffer input signal module to the input signal that comes and the small conversion configurations module construction small conversion of completion of multiplying each other.
19. the sample rate conversion device of digital signal as claimed in claim 18; It is characterized in that, described cascade transformational analysis module confirm only to carry out the situation of integer conversion, only carry out situation and the integer conversion of small conversion and foundation that small conversion is all carried out be:
(a) if the factor that M, N can effectively arrange decompose and make M 1* M 2* L * M K=M, N 1* N 2* L * N K=N, and satisfy
f 1 Π i = 1 I N i M i ≥ f 2 , i=1,2,L,K
K>=1,1≤M wherein 1, M 2, L, M K, N 1, N 2, L, N K<P Max, carry out the cascade integer so and change signal sampling rate by f 1Convert f into 2
(b) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|>P Max, carry out so small conversion with signal sampling rate by f 1Convert f into 2, the small transfer ratio f of this moment 1: f 2=M: N=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor;
(c) if M, N can not carry out the factor described in (a) to be decomposed, but min (M, N)/| M-N|≤P Max, look for M 1* M 2* L * M K=M ', N 1* N 2* L * N K=N ' makes | N '/M '-N/M| is minimum, and satisfies the formula in (a), 1≤M wherein 1, M 2, L, N K, N 1, N 2, L, N K<P Max, K>=1 is carried out the cascade integer so and is changed signal sampling rate by f 1Convert f ' into 2, carry out small conversion again with f ' 2Convert f into 2, the small transfer ratio f ' of this moment 2: f 2=MN ': NM '=s 1: s 2, s wherein 1, s 2There is not further abbreviation of common factor.
20. the sample rate conversion device of digital signal as claimed in claim 19 is characterized in that, described parameter P MaxInterval be [20,30], its representative value is 20.
21. the sample rate conversion device of digital signal as claimed in claim 18; It is characterized in that; Described integer conversion configurations module construction integer transition matrix; The integer transition matrix of each grade is to make up through the vectorial extraction of low pass filter, and the frequency inverted ratio of integers of the k level of integer conversion is M k: N k, integer transition matrix A kBe that a size is N k* M kl kMatrix, be expressed from the next:
A k = h k ( 0 ) h k ( N k ) h k ( 2 N k ) h k ( 3 N k ) h k ( 4 N k ) L h k ( M k l k N k - N k ) h k ( 1 ) h k ( N k + 1 ) h k ( 2 N k + 1 ) h k ( 3 N k + 1 ) h k ( 4 N k + 1 ) L h k ( M k l k N k + 1 - N k ) h k ( 2 ) h k ( N k + 2 ) h k ( 2 N k + 2 ) h k ( 3 N k + 2 ) h k ( 4 N k + 2 ) L h k ( M k l k N k + 2 - N k ) h k ( 3 ) h k ( N k + 3 ) h k ( 2 N k + 3 ) h k ( 3 N k + 3 ) h k ( 4 N k + 3 ) L h k ( M k l k N k + 3 - N k ) h k ( 4 ) h k ( N k + 4 ) h k ( 2 N k + 4 ) h k ( 3 N k + 4 ) h k ( 4 N k + 4 ) L h k ( M k l k N k + 4 - N k ) M M M M M O M h k ( N k - 1 ) h k ( 2 N k - 1 ) h k ( 3 N k - 1 ) h 4 ( 4 N k - 1 ) h k ( 5 N k - 1 ) L h k ( M k l k N k - 1 )
Wherein, the low pass filter vector is h k=[h k(0), h k(1), h k(2), h k(3), h k(4), h k(5), L, h k(M kl kN k-1)], its length is M kl kN k, its stopband attenuation is controlled at about 80 to 100dB; l kThe length that is used for control filters, general value is about 30, cut-off frequency is 1/max (M k, N k).
22. the sample rate conversion device of digital signal as claimed in claim 18 is characterized in that, described integer modular converter with signal sampling rate by input sampling rate f 1Convert output sampling rate f into 2, each grade integer conversion obtains exporting the signal realization through input signal and integer transition matrix are multiplied each other, and its detailed process is:
The calculating of integer converted output signal is periodic, if each input signal of participating in calculating has M kl kPoint is used
Figure FSA00000424969300112
Expression is in the j time output of one-period, with integer transition matrix A kThe capable x of multiply by of j obtain 1 output signal, upgrade int [jM then k/ N k]-int [(j-1) M k/ N k] individual input, if int [jM k/ N k]-int [(j-1) M k/ N k] be 0, then do not upgrade, accomplish N kIndividual output back j returns the new calculating of 1 beginning.
23. the sample rate conversion device of digital signal as claimed in claim 18; It is characterized in that; Described small conversion configurations module adopts the higher order polynomial interpolation to make up small transition matrix or vector; The condition that satisfies according to higher order polynomial is different, is divided into quick small conversion and two kinds of situation of best small conversion.
24. the sample rate conversion device of digital signal as claimed in claim 23 is characterized in that, if adopt the higher order polynomial interpolation, and input signal is equal interval sampling, and so small conversion configurations module adopts quick small conversion, makes up small converting vector w j, its computational methods are:
In order to obtain more level and smooth function curve and output reliably, to a series of input signal x i, x I+1, x I+2, L need be each [x I-int [n/2], L, x i, x I+1, L, x I+int [n/2+0.5]] set up a function f separately i(x), i.e. segmentation makes up higher order polynomial, obtains a series of vectorial w i, and use function f i(x) mid portion [x i, x I+1] curve of section is used for interpolation output, then absolute i constantly taken out, input matrix constantly can be regarded as constant
t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 = ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
The relative moment of output then is t=is 1/ s 2-int [is 1/ s 2], t has periodically, and the cycle is s 2, promptly the relative output time of one-period does
t j=js 1/s 2-int[js 1/s 2],j=1,2,L,s 2
The vectorial w that it is corresponding jAlso has periodically w jFor
w j = [ t j n , t j n - 1 , L , t j 1 , 1 ] ( - int [ n / 2 ] ) n ( - int [ n / 2 ] ) n - 1 L ( - int [ n / 2 ] ) 0 ( 1 - int [ n / 2 ] ) n ( 1 - int [ n / 2 ] ) n - 1 L ( 1 - int [ n / 2 ] ) 0 M M O M ( int [ n / 2 + 0.5 ] ) n ( int [ n / 2 + 0.5 ] ) n - 1 L ( int [ n / 2 + 0.5 ] ) 0 - 1
25. the sample rate conversion device of digital signal as claimed in claim 24 is characterized in that, described small converting vector w i, w jThe calculating principle be:
N rank polynomial function does
f(x)=a nx n+a n-1x n-1+L+a 1x+a 0
Known f (t j)=x j, j=0,1, K, n, coefficient a so 0, a 1, a 2, K, a nCan confirm through matrix form
a n a n - 1 M a 0 = t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n
The functional value y corresponding for unknown t place just can come out through polynomial computation, promptly
y = t n t n - 1 L t 0 a n a n - 1 L a 0 T
= t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1 x 0 x 1 M x n
= w x 0 x 1 L x n T
w = t n t n - 1 L t 0 t 0 n t 0 n - 1 L t 0 0 t 1 n t 1 n - 1 L t 1 0 M M O M t n n t n n - 1 L t n 0 - 1
At this moment functional value y is converted into vectorial w and n+1 point input signal vector multiplies each other, and w and unknown t and input matrix is relevant constantly.
26. the sample rate conversion device of digital signal as claimed in claim 18 is characterized in that, if adopt based on the polynomial interopolation algorithm that divides the intersegmental high-order condition of continuity, so small conversion configurations module adopts best small conversion, makes up small transition matrix; This algorithm definition s 1Individual input interval [0,1], [1,2], L, [i, i+1], L, [s 1-1, s 1] corresponding s 1Individual piecewise function f j(x) be polynomial of degree n, wherein the corresponding value x of the i of institute at interval border place iKnown, require f j(x) satisfy following constraints:
(1) for j=1,2, K, s 1, f j(1)=x j, f 1(0)=x 0
(2) for j=1,2, K, s 1-1,
Figure FSA00000424969300141
Subscript (r) representative function f wherein j(x) r subderivative, r=0,1, K, n-1;
(3) boundary condition satisfies n-1 in following 2 (n-1) set condition
Figure FSA00000424969300142
Figure FSA00000424969300143
R=1, K, n-1, c R1, c R2Be constant, generally can make it is 0.
27. the sample rate conversion device of digital signal as claimed in claim 26 is characterized in that, described piecewise function f j(x) be generally 3 order polynomials, i.e. f j(x)=a kx 3+ b kx 2+ c kX+d kIn a change-over period, input signal overlaps with the head and the tail end points of output signal, i.e. input signal x 0=output signal y 0, the input mark Output signal y 0,
Figure FSA00000424969300145
Between point utilize they input interval [0, s 1] in relative position and f j(x) obtain.Consider s 1, s 2Known and fixing, output signal input interval [0, s 1] in the absolute position [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] also known and fixing, small conversion can convert a row input signal x and a s into 2* (s 1+ 1) sparse transition matrix B multiplies each other and obtains the process of a row output signal y, sparse transition matrix B only with s 1, s 2And f j(x) the column constraint condition that is satisfied is relevant, and the concrete computational process of described sparse transition matrix B is:
At first calculate relative output time
T=[t 0, t 1, L, t S2]=[0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1]-int [0, s 1/ s 2, 2s 1/ s 2, 3s 1/ s 2, L, s 1] sparse transition matrix B is the part of matrix Q, Q takes advantage of acquisition by the anti-phase of location matrix T and conditional matrix C, i.e. Q=TC -, Q is s 2* (n+1) s 1Matrix, sparse transition matrix B are the preceding s of Q 1+ 1 row, T is s 2* (n+1) s 1Matrix, C are (n+1) s 1* (n+1) s 1Matrix;
T representes with following formula:
[ t 0 n , L , t 0 2 , t 0 1 , 1 ] 0.0 0 [ t 1 n , L , t 1 2 , t 1 1 , 1 ] 1 , int [ s 1 / s 2 ] O 0 [ t s 2 - 1 n , L , t s 2 - 1 2 , t s 2 - 1 1 , 1 ] s 2 , s 1 S 2 × ( n + 1 ) s 1
Its reality is by 1 * (n+1) vector
Figure FSA00000424969300152
Constitute s as an integral unit 2* s 1Quasi-diagonal matrix,
Figure FSA00000424969300153
The position at the capable int [js of j 1/ s 2] row, int [] expression rounds;
C is made up of the n+1 sub-matrices:
C = C 0 C 1 C 2 M C n C n + 1
C wherein 0Be (s 1+ 1) * (s 1(n+1)) matrix, C 1..., C nBe (s 1-1) * (s 1(n+1)) matrix, C N+1Be (n-2) * (s 1(n+1)) matrix,
C 0Corresponding f j(x) constraints (1) is expressed from the next:
0 1 × n 1 0 1 × n 1 O 0 1 × n 1 0 1 × n 1 0 1 × n 1
C j, j=1,2, L, the corresponding f of n j(x) constraints (2) is expressed from the next:
[ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 O O [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0 0 [ x n , x n - 1 , L , 1 ] ( j ) 1 - [ x n , x n - 1 , L , 1 ] ( j ) 0
[x wherein n, x N-1, L, 1] (j) rExpression x n, x N-1, L, 1 in the j at v place subderivative;
C N+1Corresponding f j(x) constraints (3) can be chosen wantonly
Figure FSA00000424969300162
Figure FSA00000424969300163
R=1,2, L, the n-1 in this 2 (n-1) set condition of n-1, if select
Figure FSA00000424969300164
As C N+1In the capable condition of k, C so N+1In the k behavior:
[[x n,x n-1,L,1] (r) 0,0]
If select
Figure FSA00000424969300165
As C N+1In the capable condition of k, C so N+1In the k behavior:
[0,[x n,x n-1,L,1] (r) 1]
Sparse transition matrix B is:
Q = T C - = [ B s 2 × ( s 1 + 1 ) , D s 2 × ( ns 1 - 1 ) ] s 2 × ( n + 1 ) s 1
28. the sample rate conversion device of digital signal as claimed in claim 18 is characterized in that, described quick small modular converter with signal sampling rate by input sampling rate f 1Convert output sampling rate f into 2, small conversion obtains exporting signal through input signal and small converting vector are multiplied each other and realizes that its detailed process is:
Input signal has the n+1 point, with x=[x 0, x 1, x 2, L, x n] TExpression is in the j time output of one-period, with small converting vector w jMultiply by x and obtain 1 output signal, upgrade int [js then 1/ s 2]-int [(j-1) s 1/ s 2] individual input, int [js 1/ s 2]-int [(j-1) s 1/ s 2] value be 1 and upgrade 1 input, be 0 and do not upgrade, accomplish s 2Individual output back j returns the new cycle of 1 beginning.
29. the sample rate conversion device of digital signal as claimed in claim 18 is characterized in that, the small modular converter of described the best with signal sampling rate by input sampling rate f 1Convert output sampling rate f into 2, small conversion obtains exporting signal through sparse transition matrix B and input signal are multiplied each other and realizes that its concrete grammar is:
Input signal has s 1+ 1 point upgrades s at every turn 1The point input signal, output s 2The point signal
y s 2 × 1 = [ y 0 , y 1 , y 2 , L , y s 2 - 1 ] T = Bx ( s 1 + 1 ) × 1 = B [ x 0 , x 1 , x 2 , L , x s 1 ] T
30. the sampling rate converting method of digital signal as claimed in claim 29 is characterized in that, described output signal carries out pointwise to be upgraded.
31. the sample rate conversion device of digital signal as claimed in claim 18 is characterized in that, the analysis result of cascade transformational analysis module is integer conversion when all carrying out with small conversion, and the connected mode that cascade is changed is by input sampling rate f 1, output sampling rate f 2Size, amount of calculation and demand on signal quality determine jointly.
32. the sample rate conversion device of digital signal as claimed in claim 31 is characterized in that, if f 1>f 2, and require amount of calculation little, then small conversion is placed at last.
33. the sample rate conversion device of digital signal as claimed in claim 31 is characterized in that, if f 1>f 2, and require the conversion of signals quality good, then be placed on small conversion before.
34. the sample rate conversion device of digital signal as claimed in claim 31 is characterized in that, if f 1<f 2, and require amount of calculation little, then be placed on small conversion before.
35. the sample rate conversion device of digital signal as claimed in claim 31 is characterized in that, if f 1>f 2, and require the conversion of signals quality good, then small conversion is placed at last.
36. the sample rate conversion device of digital signal as claimed in claim 31; It is characterized in that; Small conversion also can be embedded in the integer conversion of cascade; And the progression of integer conversion is greater than 1, if require the conversion of signals quality good, the sample rate that makes intergrade when making up cascade system so is greater than the target sample rate f 2If require amount of calculation little, the sample rate that makes intergrade when making up cascade system so is less than the target sample rate f 2
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