CN102420575B - Error amplifier - Google Patents
Error amplifier Download PDFInfo
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- CN102420575B CN102420575B CN201110427919.5A CN201110427919A CN102420575B CN 102420575 B CN102420575 B CN 102420575B CN 201110427919 A CN201110427919 A CN 201110427919A CN 102420575 B CN102420575 B CN 102420575B
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Abstract
The invention relates to an error amplifier, which comprises an operational transconductance amplifier (OTA) circuit and a slew rate increasing circuit, wherein the slew rate increasing circuit comprises a current detection circuit and a driving circuit; the current detection circuit comprises a first detection circuit and a second detection circuit; the first detection circuit and the second detection circuit are respectively connected with loads at a positive input end and a negative input end of the OTA circuit; the driving circuit comprises a first phase inverter group which is connected with an output end of the first detection circuit, a second phase inverter group which is connected with the output end of the second detection circuit, a first driving tube which is connected with the output end of the first phase inverter group, and a second driving tube which is connected with the output end of the second phase inverter group; and the output ends of the first driving tube and the second driving tube are respectively connected with the output end of the OTA circuit. The error amplifier has higher slew rate, and a technical effect of greatly shortening the transient process of a quick response buck system is achieved.
Description
Technical field
The present invention relates to a kind of error amplifier, particularly a kind of error amplifier with high Slew Rate.
Background technology
Error amplifier is the core of voltage control loop in the direct-current switch power supply system, and its performance quality directly affects the stability of whole direct-current switch power supply system, particularly quick response system and often error amplifier had to higher Slew Rate requirement.A kind of error amplifier of the prior art, as shown in Figure 1, it mainly comprises that core amplifier and Slew Rate increase circuit two parts, wherein Slew Rate increase circuit comprises current detection circuit and drive circuit.Under normal operation, Slew Rate increases circuit and does not work; When input has in the situation of large saltus step, Slew Rate increases circuit working, produces the additional electric current I in a road
dynamicflow to C
l, Slew Rate is improved greatly.
A kind of based on the above-mentioned physical circuit enforcement structure that increases the error amplifier of circuit with Slew Rate, as shown in Figure 2:
Core amplifier is comprised of NMOS pipe M101-114, is a kind of two-stage calculation amplifier, and the first order is the difference input, and the second level is cascade output, and this dual-stage amplifier can provide very high gain;
Slew Rate increases circuit and is comprised of NMOS pipe M115-120 and NMOS pipe M1n, PMOS pipe M1p, and M115 and M119 are the current detecting pipes, detect the electric current of M103 and M104, and M117, M120 are respectively M118, M119 provides bias current, and M1n and 1Mp are switching tubes.
The operation principle of the circuit shown in Fig. 2 is as follows: under normal operation, when the positive negative input of core amplifier is equal, electric current I 1>I2 that M117 provides, cause the grid voltage current potential of M1p very high, and M1p turn-offs; In addition, electric current I 4>I3 that M120 provides, cause the grid potential of M1n very low, and M1n also turn-offs, and the branch road that M1n and M1p form does not have electric current to flow through.When huge saltus step occurs in the quick response system load, just (or negative) input of core amplifier also can produce very large saltus step, cause the electric current of M104 (or M103) to become large, by current sampling circuit M115,116,117,118 (or M119,120) n1 point current potential is descended (or n2 point current potential improves), last M1p (or M1n) conducting, produce new CL and fill (putting) electric loop, make Slew Rate be improved.
Fig. 5 of the prior artly increases circuit and with Slew Rate increase circuit error amplifier, is not applied to respectively respond fast the simulation result of buck system transient modelling process with Slew Rate: a load saltus step is arranged at the 20us place in Fig. 5, curve 1 is the buck system output voltage waveforms with Slew Rate increase circuit error amplifier, and curve 2 is for using the buck system output voltage waveforms that with Slew Rate, does not increase the circuit error amplifier; Clearly, the transient process that use increases the buck system of circuit error amplifier with Slew Rate shortens greatly.
Yet, in the switching in normal mode of operation (the core amplifier positive-negative input end equates) and load saltus step pattern, the grid potential constant interval of driving tube little (non-rail-to-rail), so driving tube can not provide for the load of core amplifier enough large extracurrent under the saltus step pattern, the ability that whole error amplifier Slew Rate is improved is limited.Prior art does not have to propose a kind of error amplifier that has larger Slew Rate.
Summary of the invention
The invention provides a kind of error amplifier, the error amplifier of prior art is improved, can be applied to respond fast the buck system, obtained larger Slew Rate, thereby made the transient process of quick response buck system shorter.
A kind of error amplifier, comprise that OTA circuit and Slew Rate increase circuit, described Slew Rate increases circuit and comprises current detection circuit and drive circuit, and the load of the input of the input of described current detection circuit and OTA circuit is joined, the input of output and drive circuit joins; Described drive circuit is exported the output of extra current to the OTA circuit, it is characterized in that,
Described current detection circuit comprises the first testing circuit of joining with the load of the positive input terminal of OTA circuit and the second testing circuit joined with the load of the negative input end of OTA circuit;
The second driving tube that the first driving tube that described drive circuit comprises the first inverter group be connected with the first testing circuit output, the second inverter group be connected with the second testing circuit output, be connected with the output of the first inverter group is connected with the output with the second inverter group; The output of described the first driving tube and the second driving tube all joins with the output of OTA circuit.
Below introduce the optimal technical scheme of a kind of error amplifier of the present invention.
Further, described the first testing circuit comprises the metal-oxide-semiconductor M215 that metal-oxide-semiconductor M212, the metal-oxide-semiconductor M213 leaked altogether with metal-oxide-semiconductor M212, the metal-oxide-semiconductor M214 be connected with metal-oxide-semiconductor M213 current mirror and grid connect external bias voltage; Metal-oxide-semiconductor M213 forms current mirror with the positive input terminal of OTA circuit and is connected, the common drain terminal that the output of the first testing circuit is metal-oxide-semiconductor M212 and metal-oxide-semiconductor M213;
Described the second testing circuit comprises metal-oxide-semiconductor M221, metal-oxide-semiconductor M222, the metal-oxide-semiconductor M223 leaked altogether with metal-oxide-semiconductor M222, the metal-oxide-semiconductor M225 be connected with metal-oxide-semiconductor M223 formation current mirror and the metal-oxide-semiconductor M224 leaked altogether with metal-oxide-semiconductor M225; Described metal-oxide-semiconductor M221 forms current mirror with the negative input end of OTA circuit and is connected, and the grid of described metal-oxide-semiconductor M224 connects external bias voltage; The common drain terminal that the output of the second testing circuit is metal-oxide-semiconductor M222 and metal-oxide-semiconductor M223.
Further, described the first inverter group and the second inverter group form by the two-stage inverter.Specifically can be:
Described the first inverter group comprise metal-oxide-semiconductor M216, with metal-oxide-semiconductor M216 leak altogether common grid metal-oxide-semiconductor M217, metal-oxide-semiconductor M218, leak altogether the metal-oxide-semiconductor M19 of common grid with metal-oxide-semiconductor M218; The common grid end of described metal-oxide-semiconductor M216 and M217 and the common drain terminal of metal-oxide-semiconductor M212 and M213 join, and the common drain terminal of metal-oxide-semiconductor M218 and M219 and the input of the first driving tube join; The common grid end of the common drain terminal of described metal-oxide-semiconductor M216 and M217 and metal-oxide-semiconductor M218 and M219 joins;
Described the second inverter group comprise metal-oxide-semiconductor M226, with metal-oxide-semiconductor M226 leak altogether common grid metal-oxide-semiconductor M227, metal-oxide-semiconductor M228, leak altogether the metal-oxide-semiconductor M229 of common grid with metal-oxide-semiconductor M228; The common grid end of described metal-oxide-semiconductor M226 and metal-oxide-semiconductor M227 and the common drain terminal of metal-oxide-semiconductor M222 and metal-oxide-semiconductor M223 join, and the common drain terminal of metal-oxide-semiconductor M228 and metal-oxide-semiconductor M229 and the input of the second driving tube join; The common grid end of the common drain terminal of described metal-oxide-semiconductor M226 and metal-oxide-semiconductor M227 and metal-oxide-semiconductor M228 and metal-oxide-semiconductor M229 joins.
The drain electrode of metal-oxide-semiconductor M212 and M213 drives the first driving tube through the two-stage inverter, because the output characteristic of inverter is rail-to-rail, make the first driving tube that very large Vgs be arranged under conducting state, so just there is very large electric current to flow through the error amplifier load, the Slew Rate of whole error amplifier improves greatly, and then has shortened the transient process of whole quick response buck system.
The drain electrode of metal-oxide-semiconductor M222 and M223 drives the second driving tube through the two-stage inverter, because the output characteristic of inverter is rail-to-rail, make the second driving tube that very large Vgs be arranged under conducting state, so just there is very large electric current to flow through the error amplifier load, the Slew Rate of whole error amplifier improves greatly, and then has shortened the transient process of whole quick response buck system.
Further, described the first driving tube is NMOS pipe M2p, and described the second driving tube is PMOS pipe M2n; The common drain terminal of the grid of described the first driving tube and metal-oxide-semiconductor M218 and metal-oxide-semiconductor M219 joins; The common drain terminal of the grid of described the second driving tube and metal-oxide-semiconductor M228 and metal-oxide-semiconductor M229 joins; The drain electrode of described the first driving tube and the second driving tube is all joined with the output of OTA circuit.
The present invention utilizes the output characteristic of inverter, for driving tube provides a rail-to-rail output, make the grid of driving tube vary widely scope, therefore can provide for the load of core amplifier enough large extracurrent, relative to existing technologies, greatly improved the Slew Rate of error amplifier.
The present invention further improves the error amplifier of prior art, has increased the inverter group structure that comprises the two-stage inverter; The structure of this inverter group makes the input of the first driving tube and the second driving tube that larger voltage swing be arranged, thereby produce the error amplifier load of flowing through of larger charging or discharging current, therefore error amplifier can obtain larger Slew Rate, reaches the technique effect that the transient process of quick response buck system shortens greatly.
The accompanying drawing explanation
The structural representation that Fig. 1 is a kind of error amplifier of the prior art;
The particular circuit configurations schematic diagram that Fig. 2 is the prior art error amplifier;
The structural representation that Fig. 3 is a kind of error amplifier of the present invention;
The particular circuit configurations schematic diagram that Fig. 4 is error amplifier embodiment of the present invention;
Fig. 5 increases circuit and with the error amplifier of Slew Rate increase circuit, is not applied to respectively respond fast the Transient simulation figure of buck system with Slew Rate in prior art;
Fig. 6 be in error amplifier of the present invention and prior art not with Slew Rate increase circuit error amplifier Slew Rate simulation waveform figure;
Fig. 7 is applied to respectively respond fast the Transient simulation figure of buck system with the error amplifier of Slew Rate increase circuit in error amplifier of the present invention and prior art.
Embodiment
Introduce in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
A kind of error amplifier, comprise that OTA circuit and Slew Rate increase circuit, and described Slew Rate increases circuit and comprises current detection circuit and drive circuit, and as shown in Figure 3, concrete structure is:
Current detection circuit, comprise the first testing circuit of joining with the load of the positive input terminal of OTA circuit and the second testing circuit joined with the load of the negative input end of OTA circuit;
Drive circuit, the second driving tube that the first driving tube that comprise the first inverter group be connected with the first testing circuit output, the second inverter group be connected with the second testing circuit output, with the output of the first inverter group, is connected is connected with the output with the second inverter group; The output of described the first driving tube and the second driving tube all joins with the output of OTA circuit.
The particular circuit configurations of error amplifier in the present embodiment can be as shown in Figure 4:
The OTA circuit comprises that metal-oxide-semiconductor M201-211:MOS pipe M201 and M202 connect respectively positive input terminal and the negative input end of power supply, and the source class of metal-oxide-semiconductor M201 and M202 is connected together, and joins with the drain electrode of metal-oxide-semiconductor M205, and the grid of metal-oxide-semiconductor M205 meets external bias Vbias; The drain electrode of metal-oxide-semiconductor M201 and M202 connects respectively metal-oxide-semiconductor M203 and M204 drain electrode (drain and gate of metal-oxide-semiconductor M203 and M204 joins), the grid of metal-oxide-semiconductor M203 and M204 connects respectively the grid of M208 and M209, the drain electrode of M208 and M209 is joined with the drain electrode of M206 and M207 respectively, and wherein the grid of M207 and drain electrode are joined; The source electrode of metal-oxide-semiconductor M205, M206 and M207 meets power supply VCC, and the drain electrode of M206 and M208 connects output.In the OTA of the present embodiment circuit, the metal-oxide-semiconductor M210 that current mirror connects and the drain electrode of M211 are joined with the drain electrode of M203 and M204 respectively, and this structure has improved the gain of error amplifier of the present invention.
The first testing circuit comprises that metal-oxide-semiconductor M212-M215:MOS pipe M213 forms current mirror with M203 and is connected, be the size of current of M213 for detection of M203, the drain electrode of metal-oxide-semiconductor M213 and M212 is joined, metal-oxide-semiconductor M212 forms current mirror with M214 and is connected, the drain electrode of metal-oxide-semiconductor M214 and M215 is joined, and the grid of M215 connects external bias.
The second testing circuit comprises that metal-oxide-semiconductor M220-M225:MOS pipe M204 forms current mirror with M221 and is connected, and M221 is for detection of the size of current of M204; The drain electrode of metal-oxide-semiconductor M222 and M223 is joined, and metal-oxide-semiconductor M223 forms current mirror with M225 and is connected, and the drain electrode of metal-oxide-semiconductor M224 and M225 is joined, and the grid of M224 connects external bias.
The first driving tube is NMOS pipe M2p in the present embodiment.
The first inverter group comprises that the drain-gate of metal-oxide-semiconductor M216-219:MOS pipe M216 and the drain-gate of M217 join, the drain-gate of metal-oxide-semiconductor M218 and the drain-gate of M219 join, the drain electrode of the grid of metal-oxide-semiconductor M218 and M219 and M216 and M217 is joined, the drain electrode of the grid of metal-oxide-semiconductor M216 and M217 and M212 and M213 is joined, and the grid of the drain electrode of metal-oxide-semiconductor M218 and M219 and NMOS pipe M2p joins.
The drain electrode of metal-oxide-semiconductor M212 and M213 carrys out driving N metal-oxide-semiconductor M2p through the two-stage inverter, has added the ON time that makes NMOS manage M2p after this two-stage inverter and has shortened, and then shortened the transient process of whole quick response system.
The second driving tube is PMOS pipe M2n in the present embodiment.
The second inverter group comprises that the drain-gate of metal-oxide-semiconductor M226-229:MOS pipe M226 and the drain-gate of M227 join, the drain-gate of metal-oxide-semiconductor M228 and the drain-gate of M229 join, the drain electrode of the grid of metal-oxide-semiconductor M228 and M229 and M226 and M227 is joined, the drain electrode of the grid of metal-oxide-semiconductor M226 and M227 and M222 and M223 is joined, and the grid of the drain electrode of metal-oxide-semiconductor M228 and M229 and PMOS pipe M2n joins.
The drain electrode of metal-oxide-semiconductor M222 and M223 drives PMOS pipe M2n through the two-stage inverter, has added the ON time that makes PMOS manage M2n after this two-stage inverter and has shortened, and then shortened the transient process of whole quick response system.
When the error amplifier with Slew Rate increase circuit of the present embodiment is applied to respond fast the buck system, when load has in the situation of large saltus step, Slew Rate increases the inner meeting of circuit and produces a corresponding pipe of pulsed drive, make the load of one extra current direction error amplifier, significantly improve the Slew Rate of error amplifier, and then shortened the transient process of response buck system fast.
In the error amplifier of the present embodiment, metal-oxide-semiconductor M213 and M221 are the current detecting pipe, form current mirror with M203 and M204 respectively and are connected, and detect the load current of OTA circuit; NMOS pipe M2p and PMOS pipe M2n are driving tubes, and the output of the drain electrode of the two and OTA circuit joins.Under normal circumstances, owing to there is no the load saltus step, the some position of the positive-negative input end of OTA circuit is suitable, referring to Fig. 4, I1<I2 is arranged, I3<I4, I2 and I4 are reference current sources, n1 point current potential is high level, and n2 point current potential is low level, so M2p and M2n two driving tubes turn-off.When the load saltus step occurs when, can cause that saltus step occurs V+ (or V-), and then cause I1>I2 (or I3>I4), cause n1 point current potential to reduce (or n2 point potential rise), so that M2p pipe conducting (or the conducting of M2n pipe), the load of the current direction OTA circuit that one tunnel is extra, the Slew Rate of error amplifier so greatly improves.
The error amplifier of the present embodiment as shown in Figure 6 with Slew Rate, do not increase the simulation process of the error amplifier of circuit, curve 1 is input step Waveform Input step waveform, curve 2 is output voltage error amplifier waveforms of the present invention, curve 3 is not to be with Slew Rate to increase the output voltage error amplifier waveform of circuit, clearly can find out: with respect to Slew Rate, not increasing the error amplifier of circuit in prior art, the Slew Rate of the error amplifier in the present embodiment improves greatly.
The error amplifier with Slew Rate increase circuit of the error amplifier of the present embodiment as shown in Figure 7 and prior art is applied to respectively respond fast the simulation result of buck system transient modelling process, in figure, a load saltus step is arranged at the 20us place: the simulation curve of the error amplifier that curve 1 is the present embodiment, curve 2 is simulation curves that prior art band Slew Rate increases the error amplifier of circuit; Clearly, error amplifier of the present invention is compared with the error amplifier with Slew Rate increase circuit of prior art, and the transient process of the quick response buck system of error amplifier of the present invention is shorter.
Claims (2)
1. an error amplifier, comprise that OTA circuit and Slew Rate increase circuit, described Slew Rate increases circuit and comprises current detection circuit and drive circuit, and the load of the input of the input of described current detection circuit and OTA circuit is joined, the input of output and drive circuit joins; Described drive circuit is exported the output of extra current to the OTA circuit, it is characterized in that,
Described current detection circuit comprises the first testing circuit of joining with the load of the positive input terminal of OTA circuit and the second testing circuit joined with the load of the negative input end of OTA circuit;
Described the first testing circuit comprises that metal-oxide-semiconductor M212, the metal-oxide-semiconductor M213 leaked altogether with metal-oxide-semiconductor M212, the metal-oxide-semiconductor M214 be connected with metal-oxide-semiconductor M212 current mirror and grid meet external bias voltage V
bias1metal-oxide-semiconductor M215; Metal-oxide-semiconductor M213 forms current mirror with the positive input terminal load pipe M203 of OTA circuit and is connected, the common drain terminal that the output of the first testing circuit is metal-oxide-semiconductor M212 and metal-oxide-semiconductor M213;
Described the second testing circuit comprises metal-oxide-semiconductor M221, metal-oxide-semiconductor M222, the metal-oxide-semiconductor M223 leaked altogether with metal-oxide-semiconductor M222, the metal-oxide-semiconductor M225 be connected with metal-oxide-semiconductor M223 formation current mirror and the metal-oxide-semiconductor M224 leaked altogether with metal-oxide-semiconductor M225; Described metal-oxide-semiconductor M221 forms current mirror with the negative input end load pipe M209 of OTA circuit and is connected, and the grid of described metal-oxide-semiconductor M224 meets external bias voltage V
bias2; The common drain terminal that the output of the second testing circuit is metal-oxide-semiconductor M222 and metal-oxide-semiconductor M223;
The second driving tube that the first driving tube that described drive circuit comprises the first inverter group be connected with the first testing circuit output, the second inverter group be connected with the second testing circuit output, be connected with the output of the first inverter group is connected with the output with the second inverter group; The output of described the first driving tube and the second driving tube all joins with the output of OTA circuit;
Described the first inverter group and the second inverter group form by the two-stage inverter;
Described the first inverter group comprise metal-oxide-semiconductor M216, metal-oxide-semiconductor M218, with metal-oxide-semiconductor M216 leak altogether common grid metal-oxide-semiconductor M217, leak altogether the metal-oxide-semiconductor M219 of common grid with metal-oxide-semiconductor M218; The common grid end of described metal-oxide-semiconductor M216 and M217 and the common drain terminal of metal-oxide-semiconductor M212 and M213 join, and the common drain terminal of metal-oxide-semiconductor M218 and M219 and the input of the first driving tube join; The common grid end of the common drain terminal of described metal-oxide-semiconductor M216 and M217 and metal-oxide-semiconductor M218 and M219 joins;
Described the second inverter group comprise metal-oxide-semiconductor M226, metal-oxide-semiconductor M228, with metal-oxide-semiconductor M226 leak altogether common grid metal-oxide-semiconductor M227, leak altogether the metal-oxide-semiconductor M229 of common grid with metal-oxide-semiconductor M228; The common grid end of described metal-oxide-semiconductor M226 and metal-oxide-semiconductor M227 and the common drain terminal of metal-oxide-semiconductor M222 and metal-oxide-semiconductor M223 join, and the common drain terminal of metal-oxide-semiconductor M228 and metal-oxide-semiconductor M229 and the input of the second driving tube join; The common grid end of the common drain terminal of described metal-oxide-semiconductor M226 and metal-oxide-semiconductor M227 and metal-oxide-semiconductor M228 and metal-oxide-semiconductor M229 joins.
2. error amplifier according to claim 1, is characterized in that,
Described the first driving tube is PMOS pipe M2p, and described the second driving tube is NMOS pipe M2n; The common drain terminal of the grid of described the first driving tube and metal-oxide-semiconductor M218 and metal-oxide-semiconductor M219 joins; The common drain terminal of the grid of described the second driving tube and metal-oxide-semiconductor M228 and metal-oxide-semiconductor M229 joins; The drain electrode of described the first driving tube and the second driving tube is all joined with the output of OTA circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110427919.5A CN102420575B (en) | 2011-12-19 | 2011-12-19 | Error amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110427919.5A CN102420575B (en) | 2011-12-19 | 2011-12-19 | Error amplifier |
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| CN102420575A CN102420575A (en) | 2012-04-18 |
| CN102420575B true CN102420575B (en) | 2014-01-08 |
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| CN201110427919.5A Expired - Fee Related CN102420575B (en) | 2011-12-19 | 2011-12-19 | Error amplifier |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101359898A (en) * | 2007-07-31 | 2009-02-04 | 展讯通信（上海）有限公司 | Slew rate intensifier for dynamic CMOS operational amplifier |
| US7859317B1 (en) * | 2007-04-17 | 2010-12-28 | Marvell International Ltd. | Low power high slew non-linear amplifier for use in clock generation circuitry for noisy environments |
-
2011
- 2011-12-19 CN CN201110427919.5A patent/CN102420575B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7859317B1 (en) * | 2007-04-17 | 2010-12-28 | Marvell International Ltd. | Low power high slew non-linear amplifier for use in clock generation circuitry for noisy environments |
| CN101359898A (en) * | 2007-07-31 | 2009-02-04 | 展讯通信（上海）有限公司 | Slew rate intensifier for dynamic CMOS operational amplifier |
Non-Patent Citations (4)
| Title |
|---|
| Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators;Hoi Lee等;《IEEE transactions on circuits and systems-II:express briefs》;20050930;第52卷(第9期);第563-567页 * |
| Hoi Lee等.Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators.《IEEE transactions on circuits and systems-II:express briefs》.2005,第52卷(第9期),第563-567页. |
| 张伟娟等.恒跨导高摆率轨对轨运算放大器的设计.《电子测试》.2011,(第11期),第58-61页. |
| 恒跨导高摆率轨对轨运算放大器的设计;张伟娟等;《电子测试》;20111130(第11期);第58-61页 * |
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Granted publication date: 20140108 Termination date: 20181219 |