CN102420118B - Method for forming metal silicide grid electrodes - Google Patents
Method for forming metal silicide grid electrodes Download PDFInfo
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- CN102420118B CN102420118B CN201110360011.7A CN201110360011A CN102420118B CN 102420118 B CN102420118 B CN 102420118B CN 201110360011 A CN201110360011 A CN 201110360011A CN 102420118 B CN102420118 B CN 102420118B
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Abstract
The invention discloses a method for forming metal silicide grid electrodes, which comprises the following steps of: step 1, metal polysilicon grid electrode pattern formation; step 2, primary gride electrode etching of the metal polysilicon grid electrodes; step 3, photoresist removal; step 4, dielectric film deposition; and step 5, secondary grid electrode etching. In the method, the twice grid electrode etching is utilized, metal silicides and buffer layer side walls are exposed after the primary etching, a layer of dielectric film is deposited, and the chemical reaction of metal elements and oxygen elements in the subsequent high-temperature oxidation process is prevented, so the problem of buffer layer projection is solved. In addition, the high-temperature process is not adopted before the primary etching, the corresponding high-temperature process is carried out after the metal silicide patterns are formed, and the problem of etching concave holes caused by silicon clusters can be solved.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing process, relate in particular to a kind of formation method of metal silicide gate.
Background technology
Grid structure with metal silicide is generally used in semiconductor technology.Metal silicide after crystallization has low-resistance characteristic, is used to the grid that reduces resistance and connect different doping types.But metal silicide easily forms the cluster (cluster) of silicon in high-temperature technology in inside, can cause the shrinkage pool defect (pitting) in grid etch.In some device technology, when there is no high-temperature step or gate dielectric film (or being called gate dielectric) thickness between metal silicide deposition and grid etch enough in thick situation, this problem there will not be.But along with device dimensions shrink, the thickness of gate dielectric is more and more thinner, simultaneously in the manufacturing process of some device because a variety of causes must add the technique with high temperature before grid etch, or special process can cause metalloid silicide film to peel off problems such as (peeling) and need to add the existence of some special circumstances such as annealing in process before etching, make shrinkage pool defect become the problem solving of having to.As shown in Figure 1, the grid structure of metal silicide comprises from the bottom to top: on silicon substrate 101, be gate dielectric 102, then be grid polycrystalline silicon 103, the resilient coating of metal silicide and/or (diffusion) barrier layer 104 (nonessential), be metal silicide 105 and top layer deielectric-coating 106 (nonessential) above, top layer deielectric-coating 106 is the photoresist 107 after graphical above.Fig. 1 explanation be in the situation that forming silicon bunch group, can in gate dielectric 102, form shrinkage pool defect 110 with general lithographic method.
In surface channel (surface channel) device, because the doped chemical in polysilicon can be diffused in metal silicide above, so need to increase one deck barrier layer and resilient coating, for example TiN/Ti, in some device technology, often to add the oxide layer that forms one deck tens Izod right sides with the high temperature oxidation process of oxygen on grid polycrystalline silicon sidewall to improve reliability performance, will produce like this resilient coating metal oxidized, volumetric expansion and cause the outstanding defect of resilient coating.Fig. 2 is the schematic diagram after high temperature sidewall oxidation, the resilient coating of metal silicide and/or barrier layer 104 are after high-temperature oxydation, can form outstanding defect 111 at sidewall, cause the wayward and grid of grid curb wall (spacer) critical size and the source electric leakage problem between leaking.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of formation method of metal silicide gate, to solve the technical problem of the outstanding defect of metal silicide etching shrinkage pool defect and metal silicide resilient coating.
For solving the problems of the technologies described above, the invention provides a kind of formation method of metal silicide gate, the method includes the steps of:
Step 1, the formation of metal polysilicon gate figure;
Step 2, the grid etch for the first time of metal polysilicon gate;
Step 3, photoresist is removed;
Step 4, deielectric-coating deposition;
Step 5, for the second time grid etch.
Step 1 is specially: (gate dielectric adopts thermal oxidation method to form on silicon substrate, to form one deck gate dielectric, formation temperature is less than 600 ℃, its thickness is 20-150 dust), (grid polycrystalline silicon adopts CVD (chemical vapour deposition (CVD)) method to form on gate dielectric, to form one deck doping or plain grid polycrystalline silicon, formation temperature is less than 600 ℃, its thickness is 500-1500 dust), (method of metal silicide CVD or PVD (physical vaporous deposition) forms on grid polycrystalline silicon, to form layer of metal silicide, formation temperature is less than 600 ℃, its thickness is 500-1500 dust), then be coated with photoresist and form metal polysilicon gate figure.The temperature of these techniques generally, below 600 degrees Celsius, can not cause silicon in metal silicide, to form cluster.Described gate dielectric is silica, or silicon nitride, or the combination of silica and silicon nitride; Described metal silicide is tungsten silicide WSix, or cobalt silicide CoSix, or titanium silicide TiSix, or molybdenum silicide MoSix, or nickle silicide NiSix.
Preferably, in step 1, after grid polycrystalline silicon forms, metal silicide increases following steps before forming: the resilient coating and/or the barrier layer that on grid polycrystalline silicon, form layer of metal silicide.In some device for the diffusion of impurity in preventing grid polycrystalline silicon, generally also can in the middle of grid polycrystalline silicon and metal silicide, add one deck resilient coating (buffer layer) and/or barrier layer (barrier layer), barrier layer is TiN, WN etc. for example, and resilient coating is Ti such as.The resilient coating of described metal silicide and/or barrier layer adopt physical vaporous deposition to form, and its formation temperature is normal temperature～300 ℃, and wherein the thickness of resilient coating is 0-50 dust, and the thickness on barrier layer is 0-100 dust.
Preferably, in step 1, after metal silicide forms, before coating photoresist, increase following steps: on metal silicide, form one deck top layer deielectric-coating.On metal silicide, also have one deck top layer deielectric-coating (first medium film) at some in the non-volatility memorizer of self-aligned contact hole (SAC) technique, its effect is the stop-layer of SAC etching.Described top layer deielectric-coating is silica, or silicon nitride, or the combination of silica and silicon nitride.Described top layer deielectric-coating using plasma strengthens chemical vapour deposition technique or chemical vapour deposition technique forms, and formation temperature is less than 600 ℃, and its thickness is 500-1500 dust.
In step 1, make to form with photoresist metal polysilicon gate figure, described photoresist is as the etch mask layer of step 2.
In step 2, grid etch stops at gate polysilicon layer for the first time, and more than photoresist opened areas grid polycrystalline silicon, membranous quilt is all removed, and gate polysilicon layer is partly removed, preferably, the grid polycrystalline silicon thickness that part is removed accounts for 10%～80% of whole grid polycrystalline silicon layer thickness.Current etching comprises top layer deielectric-coating (first medium film) etching, metal silicide etching, grid polycrystalline silicon partial etching, if having resilient coating and/or barrier layer also to comprise the etching on this resilient coating and/or barrier layer between polysilicon and metal silicide.The object of etching is to form metal silicide figure before the cluster of silicon forms for the first time, makes the resilient coating sidewall of metal silicide and containing metal element expose simultaneously.
Step 4, deielectric-coating (second medium film) deposition, protects the metal silicide exposing and resilient coating; In step 4, described deielectric-coating is silica or silicon nitride.Described deielectric-coating adopts chemical vapour deposition technique deposition, and described deielectric-coating deposit thickness is at 20 dust～200 dusts.
In step 5, the top layer deielectric-coating (first medium film) on the metal silicide of grid etch use is for the second time as etching hard mask layer; Second medium film on gate lateral wall, the part of grid pole polysilicon of the second medium film of other positions and for the first time etching residue is all removed, and grid etch stops on gate dielectric for the second time, forms final gate patterns.Different with traditional grid structure, there is the protection of one deck second medium film at the sidewall of metal silicide and resilient coating, part of grid pole polysilicon exposes simultaneously.Due in etching through being the cluster that there is no silicon in metal silicide, so avoided the shrinkage pool problem of gate dielectric.Have the protection of deielectric-coating due to metal silicide and resilient coating, in follow-up high temperature oxidation process, resilient coating can be not oxidized and cause volumetric expansion and distinct issues simultaneously.
Compared to the prior art, the present invention has following beneficial effect: the present invention is that the new grid film layer structure preparation that may use in surface channel (surfacechannel) device and non-volatility memorizer (NVM) device provides a kind of attainable its preparation process, has solved shrinkage pool defect and the outstanding defect problem of resilient coating in new film layer structure etching under the prerequisite that guarantees device performance.In order to solve the problem of outstanding defect of grid oxidation film shrinkage pool (pitting) defect of metal silicide gate structure in etching process and metal silicide resilient coating, the present invention proposes a kind of formation method of metal silicide gate, utilize grid etch twice, after etching, exposing metal silicide and resilient coating sidewall for the first time, deposit a layer dielectric, stop the chemical reaction of metallic element and oxygen element in follow-up high temperature oxidation process, thus resolve buffer layer distinct issues.Before etching, avoid high-temperature technology for the first time in addition, carrying out again corresponding high-temperature technology after waiting metal silicide figure to form, can avoid like this etching shrinkage pool problem causing due to the cluster of silicon.
Accompanying drawing explanation
Fig. 1 is the generalized section that adopts the metal silicide gate structure of existing technique formation;
Fig. 2 adopts the metal silicide gate structure of existing technique formation after high temperature oxidation process, to form the generalized section of the outstanding defect of sidewall;
Fig. 3-Fig. 7 is the technological process generalized section of the inventive method; Wherein, Fig. 3 is the generalized section that the inventive method step 1 metal polysilicon gate figure forms; Fig. 4 is the inventive method step 2 generalized section after grid etch for the first time; Fig. 5 is the generalized section after the inventive method step 3 grid etch removal for the first time photoresist; Fig. 6 is the post-depositional generalized section of the inventive method step 4 deielectric-coating; Fig. 7 is the inventive method step 5 generalized section after grid etch for the second time;
Fig. 8 is after technique of the present invention completes, the generalized section of the metal silicide gate of formation after high-temperature oxydation.
In figure, description of reference numerals is as follows:
The 101st, silicon substrate, the 102nd, gate dielectric, the 103rd, grid polycrystalline silicon, the 104th, the resilient coating of metal silicide and/or barrier layer, the 105th, metal silicide, the 106th, top layer deielectric-coating (first medium film), the 107th, photoresist, the 108th, deielectric-coating (second medium film), the 109th, oxide-film, the 110th, shrinkage pool defect, the 111st, outstanding defect.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further detailed explanation.
Embodiment 1
If Fig. 3 is to as shown in Fig. 7, the processing step of the formation method of a kind of metal silicide gate of the present invention comprises as follows:
1. as shown in Figure 3, use the gate dielectric 102 of thermal oxidation method growth a layer thickness 20-150 dust (in the present embodiment, this thickness is the 32 Izod right sides) on silicon substrate 101, formation temperature is less than 600 ℃; On gate dielectric 102, be doping or the plain grid polycrystalline silicon 103 of 500-1500 dust (in the present embodiment, this thickness is the 800 Izod right sides) by CVD (chemical vapour deposition (CVD)) method deposition a layer thickness, polysilicon deposition temperature is less than 600 ℃ (the present embodiment is selected 550 ℃ of left and right); On grid polycrystalline silicon 103, deposit resilient coating and/or barrier layer 104 (the present embodiment adopts Ti resilient coating and TiN barrier layer) of layer of metal silicide by the method for PVD (physical vapour deposition (PVD)), the thickness of Ti resilient coating is on the 20 Izod right sides, the thickness on TiN barrier layer is on the 50 Izod right sides, and its formation temperature is normal temperature～300 ℃; The method that uses CVD or PVD deposits layer of metal silicide 105 on the resilient coating of metal silicide and/or barrier layer 104, thickness is 500-1500 dust (in the present embodiment, this thickness is on the 700 Izod right sides), here the technological temperature of CVD and PVD all can not exceed 600 ℃, can avoid like this silicon to form cluster in metal silicide 105; It on metal silicide 105, is the top layer deielectric-coating 106 (the present embodiment adopts SiN hard mask layer) of 500-1500 dust (in the present embodiment, this thickness is the 1500 Izod right sides) by PECVD (plasma enhanced chemical vapor deposition method) or CVD process deposits a layer thickness, the depositing temperature of top layer deielectric-coating 106 generally need to be less than 600 ℃, prevents the formation of cluster.On top layer deielectric-coating 106, be coated with photoresist 107 and form gate patterns.
2. as shown in Figure 4, carry out first step etching, if litho pattern comprises anti-reflecting layer, should comprise etching anti-reflecting layer, etching top layer deielectric-coating 106 and etching metal silicide 105, three steps such as the resilient coating of metal silicide and/or barrier layer 104, the etching condition of three steps can be different, etching condition is selected corresponding membranous etching gas, require to adjust according to pattern, in the region of opening pattern, the resilient coating of metal silicide and/or barrier layer 104, metal silicide 105, top layer deielectric-coating 106 is all removed, grid polycrystalline silicon 103 is partly removed, the grid polycrystalline silicon thickness that part is removed accounts for 10%～80% of whole grid polycrystalline silicon layer thickness, grid polycrystalline silicon 103 is advisable to remove the 500 Izod right sides in the present embodiment.
3. as shown in Figure 5, with the conventional ashing method in this area and wet etching removal photoresist 107, now top layer deielectric-coating 106, metal silicide 105, the sidewall on the resilient coating of metal silicide and/or barrier layer 104 exposes completely, and grid polycrystalline silicon 103 sidewall sections expose.
4. as shown in Figure 6, adopting process deposits a layer thickness of CVD is the deielectric-coating 108 (the present embodiment employing silicon nitride layer) of 20 dust～200 dusts (in the present embodiment, this thickness is the 100 Izod right sides), and depositing temperature does not limit.Because the existence of Step Coverage effect, the thickness of the deielectric-coating 108 on sidewall is less than 100 dusts, the thickness sum of both sides side wall medium film 108 adds that the width of etching figure is exactly the critical size of final grid for the first time, so the thickness of deielectric-coating 108 is determined by two factors: 1. enough stop follow-up high temperature oxidation process oxygen element and be diffused in metal silicide resilient coating; 2. can control the critical size of grid.
5. as shown in Figure 7, use the top layer deielectric-coating 106 conducts hard mask layer of etching for the second time, grid structure is carried out to etching for the second time.Deielectric-coating 108 on gate lateral wall, the part of grid pole polysilicon 103 of the deielectric-coating 108 of other positions and for the first time etching residue is all removed, and etching stopping, on gate dielectric 102, at this moment forms final grid structure.
6. Fig. 8 is after using technique of the present invention, schematic diagram after high-temperature oxydation, high-temperature oxydation condition is 970 ℃, logical O2, quick high-temp annealing 20s, at this moment form the oxide-film 109 on the 40 Izod right sides with the sidewall of lower area in etching interface for the first time, do not have shrinkage pool defect and resilient coating to give prominence to defect simultaneously.
Claims (14)
1. a formation method for metal silicide gate, is characterized in that, the method includes the steps of:
Step 1, the formation of metal polysilicon gate figure, be specially: on silicon substrate, form one deck gate dielectric, on gate dielectric, form one deck grid polycrystalline silicon, on grid polycrystalline silicon, form resilient coating and/or the barrier layer of layer of metal silicide, on resilient coating and/or barrier layer, form layer of metal silicide, be then coated with photoresist and form metal polysilicon gate figure; The resilient coating of described metal silicide and/or barrier layer adopt physical vaporous deposition to form, and its formation temperature is normal temperature～300 ℃, and wherein the thickness of resilient coating is 0-50 dust, and the thickness on barrier layer is 0-100 dust;
Step 2, the grid etch for the first time of metal polysilicon gate; Grid etch stops at gate polysilicon layer for the first time, and more than photoresist opened areas grid polycrystalline silicon, membranous quilt is all removed, and gate polysilicon layer is partly removed;
Step 3, photoresist is removed;
Step 4, deielectric-coating deposition, described deielectric-coating adopts chemical vapour deposition technique deposition, and described deielectric-coating deposit thickness is at 20 dust～200 dusts;
Step 5, for the second time grid etch;
Step 6 forms oxide-film in etching interface for the first time with the sidewall of lower area after high-temperature oxydation, does not have shrinkage pool defect and resilient coating to give prominence to defect.
2. the method for claim 1, is characterized in that, described gate dielectric adopts thermal oxidation method to form, and formation temperature is less than 600 ℃, and its thickness is 20-150 dust; Described grid polycrystalline silicon adopts chemical vapour deposition technique to form, and formation temperature is less than 600 ℃, and its thickness is 500-1500 dust; Described metal silicide adopts chemical vapour deposition technique or physical vaporous deposition to form, and formation temperature is less than 600 ℃, and its thickness is 500-1500 dust.
3. the method for claim 1, is characterized in that, in step 1, after metal silicide forms, increases following steps: on metal silicide, form one deck top layer deielectric-coating before coating photoresist.
4. method as claimed in claim 3, is characterized in that, in step 1, described top layer deielectric-coating using plasma strengthens chemical vapour deposition technique or chemical vapour deposition technique forms, and formation temperature is less than 600 ℃, and its thickness is 500-1500 dust.
5. the method for claim 1, is characterized in that, in step 1, described gate dielectric is silica, or silicon nitride, or the combination of silica and silicon nitride.
6. method as claimed in claim 3, is characterized in that, in step 1, described top layer deielectric-coating is silica, or silicon nitride, or the combination of silica and silicon nitride.
7. method as claimed in claim 4, is characterized in that, in step 1, described top layer deielectric-coating is silica, or silicon nitride, or the combination of silica and silicon nitride.
8. the method for claim 1, is characterized in that, in step 1, described metal silicide is tungsten silicide WSix, or cobalt silicide CoSix, or titanium silicide TiSix, or molybdenum silicide MoSix, or nickle silicide NiSix.
9. the method for claim 1, is characterized in that, in step 1, described resilient coating is Ti, and described barrier layer is TiN or WN.
10. the method for claim 1, is characterized in that, in step 1, makes to form with photoresist metal polysilicon gate figure, and described photoresist is as the etch mask layer of step 2.
11. the method for claim 1, is characterized in that, in step 2, described gate polysilicon layer is partly removed, and the grid polycrystalline silicon thickness that part is removed accounts for 10%～80% of whole grid polycrystalline silicon layer thickness.
12. the method for claim 1, is characterized in that, in step 4, described deielectric-coating is silica or silicon nitride.
13. methods as claimed in claim 3, is characterized in that, in step 5, the top layer deielectric-coating on the metal silicide of grid etch use is for the second time as etching hard mask layer.
14. methods as described in claim 1 or 13, is characterized in that, in step 5, grid etch stops on gate dielectric for the second time.
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| CN201110360011.7A CN102420118B (en) | 2011-11-14 | 2011-11-14 | Method for forming metal silicide grid electrodes |
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| CN201110360011.7A CN102420118B (en) | 2011-11-14 | 2011-11-14 | Method for forming metal silicide grid electrodes |
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| CN102420118B true CN102420118B (en) | 2014-07-09 |
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| CN115995486A (en) * | 2021-10-15 | 2023-04-21 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933741A (en) * | 1997-08-18 | 1999-08-03 | Vanguard International Semiconductor Corporation | Method of making titanium silicide source/drains and tungsten silicide gate electrodes for field effect transistors |
| US6492250B1 (en) * | 2000-08-15 | 2002-12-10 | United Microelectronics Corp. | Polycide gate structure and method of manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100695896B1 (en) * | 2006-02-22 | 2007-03-19 | 삼성전자주식회사 | Method of forming semiconductor device having metal gate electrode and the device so formed |
| US20050156208A1 (en) * | 2003-09-30 | 2005-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device having multiple silicide types and a method for its fabrication |
| DE102008035809B3 (en) * | 2008-07-31 | 2010-03-25 | Advanced Micro Devices, Inc., Sunnyvale | A technique for reducing the silicide inequalities in polysilicon gate electrodes through an intervening diffusion blocking layer |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5933741A (en) * | 1997-08-18 | 1999-08-03 | Vanguard International Semiconductor Corporation | Method of making titanium silicide source/drains and tungsten silicide gate electrodes for field effect transistors |
| US6492250B1 (en) * | 2000-08-15 | 2002-12-10 | United Microelectronics Corp. | Polycide gate structure and method of manufacture |
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