CN102419337A - Qualitative analysis method of LDD structure of MOSFET device - Google Patents
Qualitative analysis method of LDD structure of MOSFET device Download PDFInfo
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- CN102419337A CN102419337A CN2011102335966A CN201110233596A CN102419337A CN 102419337 A CN102419337 A CN 102419337A CN 2011102335966 A CN2011102335966 A CN 2011102335966A CN 201110233596 A CN201110233596 A CN 201110233596A CN 102419337 A CN102419337 A CN 102419337A
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Abstract
The invention provides a qualitative analysis method of an LDD structure of an MOSFET (Metal-Oxide-Semiconductor Field-Effect transistor) device. The method comprises the following steps of: A. preparing a dyeing liquor of a source electrode, a drain electrode and an LDD structure according to a volume ratio of HF to HNO3 to acetate acid gracial equal to 1:2:10; B. immersing an MOSFET device to be measured into the dyeing liquor for 5 sec; C. carrying out cross section observation by a field emission scan electron microscope on doped structure zones of the source electrode, the drain electrode and the LDD structure of the MOSFET device, taking photographs of the scanning by the scan electron microscope and measuring junction depths of correlative doped structures; D. carrying out a qualitative determination on whether the LDD structure is employed. Usage of the dyeing liquor formula in the invention enables simple, rapid and economic junction depth confirmation of doped structures of the source electrode, the drain electrode and the LDD structure of a same kind of MOSFET device and rapid qualitative determination on whether the LDD structure is employed in the MOSFET device.
Description
Technical field
The present invention relates to a kind of method for qualitative analysis of MOSFET device LDD structure.
Background technology
Metal-oxide layer-semiconductor-field-effect transistor; (Metal-Oxide-Semiconductor Field-Effect transistor MOSFET) is a kind of field-effect transistor (field-effect transistor) that can be widely used in mimic channel and digital circuit.MOSFET is different according to the polarity of its " passage ", can be divided into the MOSFET of N type and P type, is called NMOSFET and PMOSFET usually again, and other are called for short and also comprise NMOS FET, PMOS FET, nMOSFET, pMOSFET etc.
Recent decades in past, the size of MOSFET constantly diminishes.In the early stage IC MOSFET processing procedure, passage length is about several microns grade, but to the IC processing procedure of today, and this parameter has been dwindled tens times even above 100 times.The volume production of 90nm product, 65nm product, 45nm product has proved absolutely the speed of MOSFET device size micro.The micro of device size has no doubt increased integrated level; Reduced cost; But also brought negative effect-short-channel effect (short-channel effects) on the other hand: after promptly channel length is reduced to a certain degree; The depletion region of source electrode, drain electrode shared proportion in whole raceway groove increases, and the silicon face below the grid forms the required quantity of electric charge of inversion layer and reduces, thereby threshold voltage reduces.The interior depletion region of substrate increases threshold voltage along the electric charge of channel width side direction dwell portion simultaneously.When channel width was reduced to the same magnitude of depletion width, the threshold voltage increase became very significantly.The short channel device threshold voltage is very responsive to the variation of channel length.
For reducing the influence of this secondary physical influence, realize short channel device, on device architecture, improve.Manage to reduce raceway groove electric field, especially drain terminal electric field on the one hand; To eliminate the interaction between the PN junction, between the device on the other hand.Lightly doped drain MOS structure (LDD) has therefore appearred.
Lightly doped drain (Lightly Doped Drain; LDD) structure; Be that MOSFET is in order to weaken the drain region electric field, to improve a kind of structure that a series of short-channel effects such as thermoelectron degradation effect are taked, shown in accompanying drawing 1; Wherein substrate is a P type substrate 1, and lightly doped drain is a n-lightly doped drain 2.Be near draining, a low-doped drain region to be set in the raceway groove, let this low-doped drain region also bear part voltage, this structure can prevent the thermoelectron degradation effect.In fact, present this structure has become the basic structure of forming MOSFET in the circuit on a large scale.
We know and adopt different doping processs, through diffusion, P-type semiconductor and N-type semiconductor are produced on same block semiconductor (normally silicon or the germanium) substrate, just form the space charge region at their interface and claim PN junction.Because doping type and doping content there are differences, the transition interface of an impurity concentration of PN junction existence, promptly we " knot " said (Junction), and its degree of depth we be referred to as " junction depth " (Junction Depth).If we want whether adopted the LDD structure to carry out qualitative analysis to the MOSFET device in technological process, will obtain LDD " junction depth " information by certain technological means.Therefore how whether to have adopted the LDD structure to carry out qualitative analysis, become this technical field problem demanding prompt solution the MOSFET device.
Summary of the invention
For solving the problem that how whether has adopted the LDD structure to carry out qualitative analysis to the MOSFET device, the present invention provides following technical scheme:
A kind of method for qualitative analysis of MOSFET device LDD structure may further comprise the steps:
A, HF: HNO by volume
3: the isostructural dyeing liquor preparation of source electrode, drain electrode, the LDD that glacial acetic acid=1: 2: 10 ratio is carried out the MOSFET device;
B, MOSFET device to be measured is soaked in the dyeing liquor takes out after 5 seconds;
C, use field emission scanning electron microscope to carry out the doped structure districts such as source electrode, drain electrode, LDD of cross-section MOSFET device, take the photo of scanning electron microscope scanning, and measure the junction depth of relevant doped structure;
D, do the qualitative judgement whether this MOSFET device to be measured has adopted the LDD structure.
As a kind of preferred version of the present invention, the HF concentration in the said steps A is 49%, HNO
3Concentration is 97%.
As another kind of preferred version of the present invention, the MOSFET device to be measured among the said step B is the sample of good sample of microsection or manual sliver.
The present invention has following advantage: through the PN junction prescription of its dyeing liquor of this kind to doped structure districts such as the source electrode of MOSFET device, drain electrode, LDD; Carrying out later on the doped structure junction depths such as source electrode, drain electrode, LDD of this MOSFET device of the same race again confirms; Only needing to use the best empirical value that draws to obtain gets final product; Not only fast but also economical, the junction depth of all doped structures can obtain in a pictures, can make the qualitative judgement of whether the MOSFET device having been adopted the LDD structure fast.
Description of drawings
Fig. 1 MOSFET device lightly-doped drain zone structure;
MOSFET device lightly-doped drain zone structure figure after the dyeing that Fig. 2 scanning electron microscope is taken.
Label is among the figure:
1-P type substrate 2-n-lightly doped drain
Embodiment
Do to set forth in detail in the face of this process implementing example down, thereby protection scope of the present invention is made more explicit defining so that advantage of the present invention and characteristic can be easier to it will be appreciated by those skilled in the art that.
Shown in MOSFET device lightly-doped drain zone structure figure after the dyeing that accompanying drawing 2 scanning electron microscope are taken, be the picture that obtains through the inventive method, the sample that uses in the present embodiment is the good sample of microsection.A kind of method for qualitative analysis of MOSFET device LDD structure, its concrete operations step is following:
A, HF: HNO by volume
3: the isostructural dyeing liquor preparation of source electrode, drain electrode, the LDD that glacial acetic acid=1: 2: 10 ratio is carried out the MOSFET device, wherein the concentration of HF is 49%, HNO
3Concentration be 97%;
B, MOSFET device to be measured is soaked in the dyeing liquor takes out after 5 seconds;
C, use field emission scanning electron microscope to carry out the doped structure districts such as source electrode, drain electrode, LDD of cross-section MOSFET device, take the photo of scanning electron microscope scanning, and measure the junction depth of relevant doped structure;
D, do the qualitative judgement whether this MOSFET device to be measured has adopted the LDD structure, can confirm that according to the photo that obtains present embodiment sample device has adopted the LDD structure.
The above; Be merely one of embodiment of the present invention; But protection scope of the present invention is not limited thereto; Any those of ordinary skill in the art are in the technical scope that the present invention disclosed, and variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain that claims were limited.
Claims (3)
1. the method for qualitative analysis of a MOSFET device LDD structure, it is characterized in that: this method may further comprise the steps:
A, HF: HNO by volume
3: the isostructural dyeing liquor preparation of source electrode, drain electrode, the LDD that glacial acetic acid=1: 2: 10 ratio is carried out the MOSFET device;
B, MOSFET device to be measured is soaked in the dyeing liquor takes out after 5 seconds;
C, use field emission scanning electron microscope to carry out the doped structure districts such as source electrode, drain electrode, LDD of cross-section MOSFET device, take the photo of scanning electron microscope scanning, and measure the junction depth of relevant doped structure;
D, do the qualitative judgement whether this MOSFET device to be measured has adopted the LDD structure.
2. the method for qualitative analysis of a kind of MOSFET device LDD structure according to claim 1 is characterized in that: the HF concentration in the said steps A is 49%, HNO
3Concentration is 97%.
3. the method for qualitative analysis of a kind of MOSFET device LDD structure according to claim 1 is characterized in that: the MOSFET device to be measured among the said step B is the sample of good sample of microsection or manual sliver.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011102335966A CN102419337A (en) | 2011-08-16 | 2011-08-16 | Qualitative analysis method of LDD structure of MOSFET device |
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| CN2011102335966A CN102419337A (en) | 2011-08-16 | 2011-08-16 | Qualitative analysis method of LDD structure of MOSFET device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103926266A (en) * | 2014-04-21 | 2014-07-16 | 武汉新芯集成电路制造有限公司 | Failure analysis method of semiconductor structure |
| CN105304516A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | PN junction dyeing method |
-
2011
- 2011-08-16 CN CN2011102335966A patent/CN102419337A/en active Pending
Non-Patent Citations (3)
| Title |
|---|
| 《SPIE》 19950915 Toshihiro Sugii et al. 15 ps Cryogenic Operation of O.19-mum-LG n+ - p+ Double-Gate SOI CMOS 第2636卷, * |
| ROCK_CHEN ET AL.: "JUNCTION LEAKAGE INDUCED BY SILICON DISLOCATION IN A 0.13MICRON LOGIC PROCESS", 《RELIABILITY PHYSICS SYMPOSIUM,2005.PROCEEDINGS. 43RD ANNUAL. 2005 IEEE INTERNATIONAL》 * |
| TOSHIHIRO SUGII ET AL.: "15 ps Cryogenic Operation of O.19-μm-LG n+ - p+ Double-Gate SOI CMOS", 《SPIE》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103926266A (en) * | 2014-04-21 | 2014-07-16 | 武汉新芯集成电路制造有限公司 | Failure analysis method of semiconductor structure |
| CN103926266B (en) * | 2014-04-21 | 2016-07-06 | 武汉新芯集成电路制造有限公司 | A kind of failure analysis method of semiconductor structure |
| CN105304516A (en) * | 2015-09-22 | 2016-02-03 | 上海华虹宏力半导体制造有限公司 | PN junction dyeing method |
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Application publication date: 20120418 |