CN102412228A - Coaxial through-silicon-via interconnection structure and manufacturing method thereof - Google Patents
Coaxial through-silicon-via interconnection structure and manufacturing method thereof Download PDFInfo
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- CN102412228A CN102412228A CN2011103365352A CN201110336535A CN102412228A CN 102412228 A CN102412228 A CN 102412228A CN 2011103365352 A CN2011103365352 A CN 2011103365352A CN 201110336535 A CN201110336535 A CN 201110336535A CN 102412228 A CN102412228 A CN 102412228A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 122
- 239000010703 silicon Substances 0.000 claims abstract description 122
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 120
- 239000000463 material Substances 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 17
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- 239000010937 tungsten Substances 0.000 claims description 15
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 11
- 239000000956 alloy Substances 0.000 claims description 11
- 238000013459 approach Methods 0.000 claims description 11
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- 229910017052 cobalt Inorganic materials 0.000 claims description 8
- 239000010941 cobalt Substances 0.000 claims description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 229910052742 iron Inorganic materials 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910019001 CoSi Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 6
- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 claims description 6
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 239000011135 tin Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 239000011701 zinc Substances 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000010276 construction Methods 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 230000003313 weakening effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000008030 elimination Effects 0.000 description 3
- 238000003379 elimination reaction Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920006242 ethylene acrylic acid copolymer Polymers 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229920002480 polybenzimidazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052702 rhenium Inorganic materials 0.000 description 2
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- GUVLYNGULCJVDO-UHFFFAOYSA-N EPTC Chemical compound CCCN(CCC)C(=O)SCC GUVLYNGULCJVDO-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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Abstract
The invention relates to the technical field of microelectronic packaging, in particular to a coaxial through silicon via interconnection structure. The interconnect structure, comprising: a silicon substrate; a through silicon via penetrating through the silicon substrate; the heavily doped layer is positioned on the side wall of the through silicon via; an outer conductive connection member surrounded by the heavily doped layer; at least one insulating layer surrounded by the outer conductive connecting member; at least one inner conductive connecting member surrounded by an insulating layer and forming a coaxial structure with the outer conductive connecting member. The invention also provides a manufacturing method of the coaxial through silicon via interconnection structure. The invention can be used for enhancing the robustness of the through silicon via, isolating noise, eliminating crosstalk, shielding EMI, reducing transmission loss, weakening the parasitic effect of the through silicon via and improving high-frequency performance; meanwhile, the characteristics of the insulating layer can be conveniently measured, and the characteristics of the insulating layer can be obtained only by measuring the insulating characteristics between the outer conductive connecting member and the inner conductive connecting member without additionally manufacturing a measuring structure.
Description
Technical field
The present invention relates to the microelectronic packaging technology field, be specifically related to a kind of coaxial interconnecting silicon through holes structure and manufacturing approach thereof.
Background technology
Along with people's is to the requirement of electronic product to the development of miniaturization, high-performance, direction such as multi-functional; The researcher makes great efforts to seek and does electronic system more little; Performance is more and more stronger, and function is done many more more, has produced many new technologies, new material and new design thus; Wherein (System-in-Package, SiP) technology is exactly these technological typical case representatives for three-dimensional packaging technology and system in package.
Three-dimensional packaging technology is meant under the prerequisite that does not change package body sizes, in same packaging body, stacks the encapsulation technology of two above chips in vertical direction.And whole or most electric functions of a system or subsystem are configured in the packaging body, just realized system in package.The interconnecting silicon through holes technology realizes one of key technology of three-dimension packaging and system in package just.The interconnecting silicon through holes structure is a perpendicular interconnection, can pile up chip in vertical direction so on the one hand, realizes that three-dimensional is integrated, and on the other hand, perpendicular interconnection has shortened the length of interconnection line greatly, and the electric property of integrated system will be greatly improved.In addition, along with the chip pin number further increases and further the dwindling of pin pitch, receive the restriction of organic substrate process, the miniaturization of conventional substrate lines has improved cost of manufacture greatly, and is difficult to satisfy the requirement of using.The keyset technology of applying silicon through-hole interconnection then is a kind of effective solution of these problems of reply.Because use semi-conductive manufacturing process, the keyset of applying silicon through-hole interconnection can obtain very highdensity wiring and very little pitch.And the thermal coefficient of expansion and the chip of silicon keyset are close, can reduce the mismatch of thermal coefficient of expansion like this, thereby avoid a lot of problems, have greatly improved the hot Mechanical Reliability of packaging body.
But along with the electronic system frequency is increasingly high, the silicon via densities is increasing, and integrated chip and components and parts get more and more in the system in package, and it is an important factor must considering that the electromagnetic interference (EMI) problem becomes in the electronic system design.Electromagnetic interference also is called as radio frequency interference (RFI), is to cause by having the electromagnetic radiation that the electronic circuit that changes the signal of telecommunication and element send.Electromagnetic interference can influence even destroy the operate as normal of electronic system.There are three kinds of main modes to be used for improving at present or elimination EMI.First kind of technology is with senser and electromagnetic radiation source physical isolation.Second kind of technology is to use bypass or decoupling capacitor and filter with the interference signal ground connection of not wanting.The third technology is to use Faraday cage (Faraday cage) or intercepts the element that shell shields senser or produces EMI.In numerous technology, adopt the co-axial interconnect structure, can effectively realize the effect of EMI shielded.
Use existing technology, can form the interconnecting silicon through holes coaxial configuration, but all existing various problems aspect process complexity, cost and the electrical property.For example; " Fabrication and characterization of robust through-silicon vias for silicon-carrier applications " is said for the paper that IBM delivers at IBM J. RES. & DEV. VOL. 52 NO. 6; Can form an outer shroud is that DOPOS doped polycrystalline silicon and inner core are the coaxial interconnecting silicon through holes structure of copper; But the etching of outer shroud and inner core will be carried out with filling step by step, has so then increased process complexity and cost expenditure.CEA-LETI is at Electronics Packaging Technology Conference; 2009. EPTC ' 09. 11th; 2009; Pp. the paper " Mid-process through silicon vias technology using tungsten metallization:Process optimazation and electrical results " delivered of 772-777. is said, can form the silicon through hole that the tungsten of many annulars are filled, but because its interconnection all is a loop configuration; The resistance of interconnection receives the thickness limits of tungsten layer and resistance is bigger, and conductivity is not good.
In addition, because silicon substrate is a semiconductor but not insulator also exists ghost effect between interconnecting silicon through holes and the silicon substrate, the electric property of system is affected.
Summary of the invention
The object of the present invention is to provide a kind of coaxial interconnecting silicon through holes structure, effectively EMI shielded reduces loss, slackens the ghost effect of silicon through hole, strengthens the robustness of silicon through hole.
Another object of the present invention is to provide a kind of manufacturing approach of coaxial interconnecting silicon through holes structure.
In order to achieve the above object, the technical scheme of the present invention's employing is:
A kind of coaxial interconnecting silicon through holes structure comprises:
Silicon chip;
The silicon through hole runs through said silicon chip;
Heavily doped layer is positioned at the sidewall of said silicon through hole;
Outer conduction connecting elements is centered on by said heavily doped layer;
At least one layer insulating is centered on by said outer conduction connecting elements;
At least conduction connecting elements in one deck is centered on by said insulating barrier, forms coaxial configuration with said outer conduction connecting elements.
In the such scheme, said silicon through hole is straight hole or bellmouth.
In the such scheme, said heavily doped layer is positioned at the surface of silicon chip, and said outer conduction connecting elements is positioned on the said heavily doped layer on said silicon chip surface.
In the such scheme, said interior conduction connecting elements is solid construction or loop configuration.
In the such scheme, said insulating barrier and said interior conduction connecting elements repeat to be arranged alternately, and form many annular coaxials structure.
In the such scheme, said silicon chip is p type silicon or n type silicon.
In the such scheme, the doped chemical of said heavily doped layer is III A family or V A family element, and doping type is identical with the silicon chip type or opposite.
In the such scheme, the concentration of the doped chemical of said heavily doped layer is greater than 10
12Atom/cm
3
In the such scheme, said outer conduction connecting elements comprises one deck contact material at least.
In the such scheme, said contact material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi
2), platinum silicide (PtSi), cobalt silicide (CoSi
2) and tungsten silicide (WSi
2) in one or more.
In the such scheme, said contact material and said heavily doped layer form ohmic contact.
In the such scheme, said outer conduction connecting elements comprises layer of conductive material at least.
In the such scheme, said electric conducting material is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, the polysilicon; Said electric conducting material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi
2), platinum silicide (PtSi), cobalt silicide (CoSi
2) and tungsten silicide (WSi
2) in one or more.
In the such scheme, said insulating barrier comprises one deck insulating material at least.
In the such scheme, said insulating material is glass, silica (SiO
2), silicon nitride (Si
3N
4), silicon oxynitride (SiON), tantalum oxide (Ta
2O
5), aluminium oxide (Al
2O
3), in the polymer one or more.
In the such scheme, said in the material of conduction connecting elements be in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, polysilicon, CNT, the conducting resinl one or more.
A kind of manufacturing approach of coaxial interconnecting silicon through holes structure comprises the steps:
On silicon chip, form the silicon through hole;
On the sidewall of said silicon through hole, form heavily doped layer;
Conduction connecting elements outside said heavily doped layer surface forms;
Conduction connecting elements surface forms insulating barrier outside said;
Conduction connecting elements in said surface of insulating layer forms.
In the such scheme, on silicon chip, after the formation silicon through hole, form heavily doped layer on the upper and lower surface of said silicon chip said.
In the such scheme, the formation of said heavily doped layer is injected through ion or the method for diffusing, doping realizes that the concentration of doping is greater than 10
12Atom/cm
3
In the such scheme, said outer conduction coupling member comprises one deck contact material at least, through the annealed alloy processing, forms ohmic contact with heavily doped layer after said contact material forms, and annealing temperature is at 300 ℃-500 ℃.
Compare with the prior art scheme, the beneficial effect that the technical scheme that the present invention adopts produces is following:
Coaxial interconnecting silicon through holes structure of the present invention can be used for strengthening the robustness of silicon through hole, can noise isolation, and elimination is crosstalked, and EMI shielded reduces loss, slackens the ghost effect of silicon through hole, can improve high frequency performance; Be convenient to measure the insulating barrier characteristic simultaneously, do not need extra manufacturing measurement structure, the insulation characterisitic that only needs to measure between outer conduction connecting elements and the interior conduction connecting elements can obtain the insulating barrier characteristic.
Description of drawings
The sketch map of the coaxial interconnecting silicon through holes structure that Fig. 1 provides for the embodiment of the invention;
The sketch map of the coaxial interconnecting silicon through holes structure that Fig. 2 provides for another embodiment of the present invention;
The sketch map of the coaxial interconnecting silicon through holes structure that Fig. 3 provides for another embodiment of the present invention;
The sketch map of the coaxial interconnecting silicon through holes structure that Fig. 4 provides for another embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment technical scheme of the present invention is described in detail.
Embodiment 1:
Coaxial interconnecting silicon through holes structure as shown in Figure 1, that present embodiment provides comprises silicon chip 101, silicon through hole, heavily doped layer 103, conducts electricity connecting elements 104, insulating barrier 105 and interior conduction connecting elements 106 outward.Wherein silicon chip is a p type silicon, and the silicon through hole is a straight hole, through-silicon substrate 101.Heavily doped layer 103 is positioned at the sidewall silicon of silicon through hole, and doped chemical is III A family or V A family element, and doping type is a p type impurity, boron ion for example, and doping content is 10
19Atom/cm
3, doping depth is 1 micron.Outer conduction connecting elements 104 comprises one deck contact material at least, is centered on by heavily doped layer 103, and contact material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi
2), platinum silicide (PtSi), cobalt silicide (CoSi
2) and tungsten silicide (WSi
2) in one or more, thickness is 0.5 micron-5 microns, contact material is in heavily doped layer 103 and outer conduction connecting elements 104 interfaces formation ohmic contact.Insulating barrier 105, the connecting elements 104 that conducted electricity outward centers on, and it forms material and comprises glass, silica (SiO
2), silicon nitride (Si
3N
4), silicon oxynitride (SiON), tantalum oxide (Ta
2O
5), aluminium oxide (Al
2O
3), in the polymer one or more, polymer can be polyimides (PI), benzocyclobutene (BCB), polyethylene, polybenzimidazoles (PBO) or ethylene acrylic acid co polymer (EAA), thickness is 1 micron-200 microns.Interior conduction connecting elements 106 is solid filling; Being insulated layer 105 centers on; With outer conduction connecting elements 104 insulation, its formation material is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy (alloy element comprises silver, gold, nickel, iron, cobalt, manganese, rhenium), polysilicon, CNT or the conducting resinl.
In the present embodiment, silicon chip 101 can also be a n type silicon, and the doping type of heavily doped layer 103 can be identical with the silicon chip type or opposite.
In the present embodiment; Outer conduction connecting elements 104 also comprises layer of conductive material at least, and electric conducting material is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy (alloy element comprises silver, gold, nickel, iron, cobalt, manganese, rhenium), the polysilicon; Said electric conducting material also can be identical with contact material, is aluminium (Al), aluminium-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten (W), molybdenum silicide (MoSi
2), platinum silicide (PtSi), cobalt silicide (CoSi
2) and tungsten silicide (WSi
2) in one or more.
In the present embodiment, insulating barrier 105 can repeat to be arranged alternately with interior conduction connecting elements 106, forms the annular coaxial structure.
Present embodiment also provides a kind of manufacturing approach of coaxial interconnecting silicon through holes structure, comprises the steps:
(1) on silicon chip 101, adopt the method for etching or laser drilling to form the silicon through hole;
(2) on the sidewall of silicon through hole, form heavily doped layer, doping method is that diffusing, doping or ion inject;
(3) conduction connecting elements outside the method through evaporation, sputter, plating, chemical plating, chemical vapour deposition (CVD) or physical vapour deposition (PVD) forms on the heavily doped layer surface; Under 300 ℃-500 ℃, carry out the annealed alloy processing then, in heavily doped layer 103 and outer conduction connecting elements 104 interfaces formation ohmic contact;
(4) conduct electricity connecting elements 104 surfaces outside through sputter, evaporation or chemical gaseous phase depositing process and form layer of conductive material at least, contact with insulating barrier 105;
(5) the method fill insulant through spin coating in the silicon through hole;
(6) method through laser drilling forms insulating barrier 105 in the silicon through hole of fill insulant;
(7) conduction connecting elements 106 in the method that said surface of insulating layer is filled through plating, chemical plating, chemical vapour deposition (CVD), physical vapour deposition (PVD), backflow or motlten metal forms.
Embodiment 2:
As shown in Figure 2, in the coaxial interconnecting silicon through holes structure that present embodiment provides, interior conduction connecting elements 106 is that annular is filled, and is insulated layer 105 and centers on, and other architectural features are said identical with embodiment 1 shown in Figure 1 with manufacturing approach.
Embodiment 3:
As shown in Figure 3, in the coaxial interconnecting silicon through holes structure that present embodiment provides, the silicon through hole is a bellmouth, and other architectural features are identical with embodiment 1 shown in Figure 1 with manufacturing approach.
Embodiment 4:
As shown in Figure 4, in the coaxial interconnecting silicon through holes structure that present embodiment provides, heavily doped layer may extend to the upper and lower surface of silicon chip with outer conduction connecting elements.Method and the method among the embodiment 1 of making this structure are basic identical, just when forming heavily doped layer with outer conduction connecting elements, not only in the silicon through hole, the upper and lower surface of silicon chip also form heavily doped layer with outside conduct electricity connecting elements.
Coaxial interconnecting silicon through holes structure of the present invention can be used for strengthening the robustness of silicon through hole, can noise isolation, and elimination is crosstalked, and EMI shielded slackens the ghost effect of silicon through hole, reduces loss, can improve high frequency performance; Be convenient to measure the insulating barrier characteristic simultaneously, do not need extra manufacturing measurement structure, the insulation characterisitic that only needs to measure between outer conduction connecting elements and the interior conduction connecting elements can obtain the insulating barrier characteristic.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (20)
1. a coaxial interconnecting silicon through holes structure is characterized in that, comprising:
Silicon chip;
The silicon through hole runs through said silicon chip;
Heavily doped layer is positioned at the sidewall of said silicon through hole;
Outer conduction connecting elements is centered on by said heavily doped layer;
At least one layer insulating is centered on by said outer conduction connecting elements;
At least conduction connecting elements in one deck is centered on by said insulating barrier, forms coaxial configuration with said outer conduction connecting elements.
2. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said silicon through hole is straight hole or bellmouth.
3. coaxial interconnecting silicon through holes structure as claimed in claim 1, it is characterized in that: said heavily doped layer is positioned at the surface of silicon chip, and said outer conduction connecting elements is positioned on the said heavily doped layer on said silicon chip surface.
4. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the conduction connecting elements is solid construction or loop configuration in said.
5. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said insulating barrier and said interior conduction connecting elements repeat to be arranged alternately, and form many annular coaxials structure.
6. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said silicon chip is p type silicon or n type silicon.
7. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the doped chemical of said heavily doped layer is III A family or V A family element, and doping type is identical with the silicon chip type or opposite.
8. coaxial interconnecting silicon through holes structure as claimed in claim 7, it is characterized in that: the concentration of the doped chemical of said heavily doped layer is greater than 10
12Atom/cm
3
9. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said outer conduction connecting elements comprises one deck contact material at least.
10. coaxial interconnecting silicon through holes structure as claimed in claim 9 is characterized in that: said contact material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi
2), platinum silicide (PtSi), cobalt silicide (CoSi
2) and tungsten silicide (WSi
2) in one or more.
11. coaxial interconnecting silicon through holes structure as claimed in claim 9 is characterized in that: said contact material and said heavily doped layer form ohmic contact.
12. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said outer conduction connecting elements comprises layer of conductive material at least.
13. coaxial interconnecting silicon through holes structure as claimed in claim 12 is characterized in that: said electric conducting material is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, the polysilicon; Said electric conducting material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi
2), titanium nitride (TiN), tungsten (W), molybdenum silicide (MoSi
2), platinum silicide (PtSi), cobalt silicide (CoSi
2) and tungsten silicide (WSi
2) in one or more.
14. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said insulating barrier comprises one deck insulating material at least.
15. coaxial interconnecting silicon through holes structure as claimed in claim 14 is characterized in that: said insulating material is glass, silica (SiO
2), silicon nitride (Si
3N
4), silicon oxynitride (SiON), tantalum oxide (Ta
2O
5), aluminium oxide (Al
2O
3), in the polymer one or more.
16. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the material of conduction connecting elements is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, polysilicon, CNT, the conducting resinl in said.
17. the manufacturing approach of a coaxial interconnecting silicon through holes structure is characterized in that, comprises the steps:
On silicon chip, form the silicon through hole;
On the sidewall of said silicon through hole, form heavily doped layer;
Conduction connecting elements outside said heavily doped layer surface forms;
Conduction connecting elements surface forms insulating barrier outside said;
Conduction connecting elements in said surface of insulating layer forms.
18. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17 is characterized in that, on silicon chip, after the formation silicon through hole, forms heavily doped layer on the upper and lower surface of said silicon chip said.
19. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17 is characterized in that: the formation of said heavily doped layer is injected through ion or the method for diffusing, doping realizes that the concentration of doping is greater than 10
12Atom/cm
3
20. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17; It is characterized in that: said outer conduction coupling member comprises one deck contact material at least; After said contact material forms through the annealed alloy processing; Form ohmic contact with heavily doped layer, annealing temperature is at 300 ℃-500 ℃.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103545296A (en) * | 2012-07-12 | 2014-01-29 | 全视科技有限公司 | Integrated circuit stack with integrated electromagnetic interference shielding |
| CN103787264A (en) * | 2014-01-21 | 2014-05-14 | 华进半导体封装先导技术研发中心有限公司 | Manufacturing method applied to high-speed broadband optical interconnection TSV device and device thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110073858A1 (en) * | 2009-09-25 | 2011-03-31 | International Business Machines Corporation | Test Structure for Determination of TSV Depth |
| CN102103979A (en) * | 2009-12-16 | 2011-06-22 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional silicon-based passive circuit formed by silicon through holes |
| US20110171827A1 (en) * | 2010-01-14 | 2011-07-14 | International Business Machines Corporation | Three Dimensional Integration and Methods of Through Silicon Via Creation |
| CN102214723A (en) * | 2011-06-01 | 2011-10-12 | 北京大学 | Semiconductor radiation sensing device and manufacturing method thereof |
-
2011
- 2011-10-31 CN CN201110336535.2A patent/CN102412228B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110073858A1 (en) * | 2009-09-25 | 2011-03-31 | International Business Machines Corporation | Test Structure for Determination of TSV Depth |
| CN102103979A (en) * | 2009-12-16 | 2011-06-22 | 中国科学院微电子研究所 | Method for manufacturing three-dimensional silicon-based passive circuit formed by silicon through holes |
| US20110171827A1 (en) * | 2010-01-14 | 2011-07-14 | International Business Machines Corporation | Three Dimensional Integration and Methods of Through Silicon Via Creation |
| CN102214723A (en) * | 2011-06-01 | 2011-10-12 | 北京大学 | Semiconductor radiation sensing device and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| IBM: "Fabrication and characterization of robust through-silicon vias for silicon-carrier applications", 《IBM J. RES. & DEV.》, vol. 52, no. 6, 30 November 2008 (2008-11-30) * |
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