CN102412228A - Coaxial through-silicon via interconnection structure and manufacturing method thereof - Google Patents

Abstract

The present invention relates to the field of microelectronic packaging technology, and in particular to a coaxial through silicon via interconnection structure. The interconnection structure comprises: a silicon substrate; a through silicon via, which penetrates the silicon substrate; a heavily doped layer, which is located on the side wall of the through silicon via; an external conductive connection member, which is surrounded by the heavily doped layer; at least one insulating layer, which is surrounded by the external conductive connection member; at least one inner conductive connection member, which is surrounded by the insulating layer and forms a coaxial structure with the external conductive connection member. The present invention also provides a method for manufacturing a coaxial through silicon via interconnection structure. The present invention can be used to enhance the robustness of through silicon vias, isolate noise, eliminate crosstalk, shield EMI, reduce transmission loss, weaken the parasitic effect of through silicon vias, and improve high-frequency performance; at the same time, it is easy to measure the characteristics of the insulating layer, and there is no need to manufacture an additional measurement structure. The characteristics of the insulating layer can be obtained by measuring the insulation characteristics between the external conductive connection member and the inner conductive connection member.

Description

Coaxial through-silicon via interconnection structure and manufacturing method thereof

technical field

The present invention relates to the technical field of microelectronic packaging, in particular to a coaxial through-silicon via interconnection structure and a manufacturing method thereof.

Background technique

With people's requirements for the development of electronic products in the direction of miniaturization, high performance, and multi-function, researchers strive to make electronic systems smaller and smaller, with stronger performance and more functions. Many new technologies, new materials and new designs, among which three-dimensional packaging technology and system-in-package (System-in-Package, SiP) technology are typical representatives of these technologies.

Three-dimensional packaging technology refers to the packaging technology that stacks two or more chips in the same package in the vertical direction without changing the size of the package. System-in-package is realized by disposing all or most of the electronic functions of a system or subsystem in one package. Through-silicon via interconnect technology is one of the key technologies to realize three-dimensional packaging and system-in-package. The through-silicon via interconnection structure is a vertical interconnection, so that on the one hand, chips can be stacked in the vertical direction to achieve three-dimensional integration. On the other hand, the vertical interconnection greatly shortens the length of the interconnection line, and the electrical performance of the integrated system will be improved. Great improvement. In addition, with the further increase in the number of chip pins and the further shrinking of the pin pitch, limited by the organic substrate process, the miniaturization of the traditional substrate lines greatly increases the production cost, and it is difficult to meet the application requirements. The interposer technology using TSV interconnection is an effective solution to these problems. Due to the use of semiconductor process technology, the interposer board using through-silicon via interconnection can obtain very high-density wiring and small pitch. Moreover, the thermal expansion coefficient of the silicon interposer is similar to that of the chip, which can reduce the mismatch of thermal expansion coefficients, thereby avoiding many problems and greatly improving the thermomechanical reliability of the package.

However, as the frequency of electronic systems increases, the density of through-silicon vias increases, and more and more chips and components are integrated in system-in-packages, the problem of electromagnetic interference (EMI) has become a must in the design of electronic systems. An important factor to consider. Electromagnetic interference, also known as radio frequency interference (RFI), is caused by electromagnetic radiation emitted by electronic circuits and components with varying electrical signals. Electromagnetic interference can affect or even destroy the normal operation of electronic systems. There are currently three main approaches used to improve or eliminate EMI. The first technique is to physically isolate sensitive components from the source of electromagnetic radiation. The second technique is to use bypass or decoupling capacitors and filters to ground unwanted interfering signals. A third technique is to use a Faraday cage or barrier enclosure to shield sensitive or EMI-generating components. Among many technologies, the use of coaxial interconnection structures can effectively achieve the effect of shielding EMI.

Applying the existing technology, it is possible to form a TSV interconnection coaxial structure, but there are various problems in terms of process complexity, cost and electrical performance. For example, as described in the paper "Fabrication and characterization of robust through-silicon vias for silicon-carrier applications" published by IBM in IBM J. RES. & DEV. VOL. 52 NO. 6, an outer ring can be formed for doping polysilicon and Coaxial TSV interconnection structure with copper inner core, but the etching and filling of the outer ring and the inner core have to be carried out step by step, which increases the process complexity and cost expenditure. As stated in the paper "Mid-process through silicon vias technology using tungsten metallization: Process optimization and electrical results" published by CEA-LETI at Electronics Packaging Technology Conference, 2009. EPTC'09. 11th, 2009, pp. 772-777. Multiple ring-shaped tungsten-filled TSVs are formed, but because the interconnection is in a ring structure, the resistance of the interconnection is limited by the thickness of the tungsten layer, and the resistance value is relatively large, and the conductivity is not good.

In addition, since the silicon substrate is a semiconductor rather than an insulator, there are parasitic effects between the TSV interconnection and the silicon substrate, which will also greatly affect the electrical performance of the system.

Contents of the invention

The purpose of the present invention is to provide a coaxial TSV interconnection structure, which can effectively shield EMI, reduce transmission loss, weaken the parasitic effect of TSV, and enhance the robustness of TSV.

Another object of the present invention is to provide a method for manufacturing a coaxial TSV interconnection structure.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A coaxial through-silicon via interconnection structure, comprising:

Silicon substrate;

through-silicon vias, penetrating through the silicon substrate;

a heavily doped layer located on the sidewall of the TSV;

an outer conductive connection member surrounded by the heavily doped layer;

at least one insulating layer surrounded by said outer conductive connection member;

At least one layer of inner conductive connection members, surrounded by the insulating layer, forms a coaxial structure with the outer conductive connection members.

In the above solution, the TSVs are straight holes or tapered holes.

In the above solution, the heavily doped layer is located on the surface of the silicon substrate, and the external conductive connection member is located on the heavily doped layer on the surface of the silicon substrate.

In the above solution, the inner conductive connecting member is a solid structure or a ring structure.

In the above solution, the insulating layer and the inner conductive connecting member are repeatedly and alternately arranged to form a multi-ring coaxial structure.

In the above solution, the silicon substrate is p-type silicon or n-type silicon.

In the above scheme, the doping elements of the heavily doped layer are Group III A or Group VA elements, and the doping type is the same as or opposite to that of the silicon substrate.

In the above solution, the doping element concentration of the heavily doped layer is greater than 10 ¹² atoms/cm ³ .

In the above solution, the outer conductive connection member includes at least one layer of contact material.

In the above scheme, the contact material is aluminum (Al), aluminum-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi ₂ ), platinum silicide (PtSi), cobalt silicide (CoSi ₂ ) and one or more of tungsten silicide (WSi ₂ ).

In the above solution, the contact material forms an ohmic contact with the heavily doped layer.

In the above solution, the outer conductive connection member includes at least one layer of conductive material.

In the above scheme, the conductive material is one or more of nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and their single or binary alloys, polysilicon ; The conductive material is aluminum (Al), aluminum-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi ₂ ), platinum silicide (PtSi), cobalt silicide (CoSi ₂ ) and One or several kinds of tungsten silicide (WSi ₂ ).

In the solution above, the insulating layer includes at least one layer of insulating material.

In the above solution, the insulating material is glass, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), one or more of polymers.

In the above scheme, the material of the internal conductive connecting member is nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and their single or binary alloys, polysilicon, carbon nano One or more of tubes and conductive adhesives.

A method for manufacturing a coaxial through-silicon via interconnection structure, comprising the steps of:

Forming through-silicon vias on silicon substrates;

forming a heavily doped layer on the sidewall of the TSV;

forming an external conductive connection member on the surface of the heavily doped layer;

forming an insulating layer on the surface of the outer conductive connection member;

An inner conductive connection member is formed on the surface of the insulating layer.

In the above solution, after the through-silicon vias are formed on the silicon substrate, heavily doped layers are formed on the upper and lower surfaces of the silicon substrate.

In the above solution, the formation of the heavily doped layer is realized by ion implantation or diffusion doping, and the doping concentration is greater than 10 ¹² atoms/cm ³ .

In the above scheme, the external conductive connecting structure includes at least one layer of contact material, and the contact material is annealed and alloyed after formation to form an ohmic contact with the heavily doped layer, and the annealing temperature is 300°C-500°C.

Compared with prior art solutions, the beneficial effects produced by the technical solutions adopted in the present invention are as follows:

The coaxial TSV interconnection structure of the present invention can be used to enhance the robustness of TSVs, can isolate noise, eliminate crosstalk, shield EMI, reduce transmission loss, weaken parasitic effects of TSVs, and improve high-frequency performance ; At the same time, it is convenient to measure the properties of the insulating layer, without additionally manufacturing a measurement structure, and the properties of the insulating layer can be obtained only by measuring the insulating properties between the outer conductive connecting member and the inner conductive connecting member.

Description of drawings

FIG. 1 is a schematic diagram of a coaxial TSV interconnection structure provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a coaxial TSV interconnection structure provided by another embodiment of the present invention;

3 is a schematic diagram of a coaxial TSV interconnection structure provided by another embodiment of the present invention;

FIG. 4 is a schematic diagram of a coaxial TSV interconnection structure provided by another embodiment of the present invention.

Detailed ways

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

Example 1:

As shown in FIG. 1, the coaxial TSV interconnection structure provided by this embodiment includes a silicon substrate 101, a TSV, a heavily doped layer 103, an outer conductive connection member 104, an insulating layer 105 and an inner conductive connection member. 106. The silicon substrate is p-type silicon, and the through-silicon vias are straight holes, penetrating through the silicon substrate 101 . The heavily doped layer 103 is located on the silicon sidewall of the TSV, and the doping element is group III A or group VA element, and the doping type is p-type impurity, such as boron ion, and the doping concentration is 10 ¹⁹ atoms/cm ³ , The doping depth is 1 micron. The outer conductive connection member 104 includes at least one layer of contact material, surrounded by the heavily doped layer 103, and the contact material is aluminum (Al), aluminum-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide ( One or more of MoSi ₂ ), platinum silicide (PtSi), cobalt silicide (CoSi ₂ ) and tungsten silicide (WSi ₂ ), with a thickness of 0.5 microns to 5 microns, and the contact material is between the heavily doped layer 103 and the outer conductive The connection member 104 interface forms an ohmic contact. The insulating layer 105 is surrounded by the outer conductive connection member 104, and its forming material includes glass, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), one or more of polymers, polymers can be polyimide (PI), benzocyclobutene (BCB), polyethylene, polybenzimidazole ( PBO) or ethylene acrylic acid copolymer (EAA), with a thickness of 1 micron to 200 microns. The inner conductive connection member 106 is solid filled, surrounded by the insulating layer 105, and insulated from the outer conductive connection member 104, and its forming material is nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tungsten, zinc, silver, tin One or more of its one or two element alloys (alloying elements include silver, gold, nickel, iron, cobalt, manganese, rhenium), polysilicon, carbon nanotubes or conductive glue.

In this embodiment, the silicon substrate 101 may also be n-type silicon, and the doping type of the heavily doped layer 103 may be the same as or opposite to that of the silicon substrate.

In this embodiment, the outer conductive connecting member 104 also includes at least one layer of conductive material, the conductive material is nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and their unary or One or more of binary alloys (alloying elements include silver, gold, nickel, iron, cobalt, manganese, rhenium), polysilicon; the conductive material can also be the same as the contact material, aluminum (Al), aluminum - One of silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten (W), molybdenum silicide (MoSi ₂ ), platinum silicide (PtSi), cobalt silicide (CoSi ₂ ) and tungsten silicide (WSi ₂ ) species or several.

In this embodiment, the insulating layer 105 and the inner conductive connecting member 106 may be repeatedly and alternately arranged to form a ring-shaped coaxial structure.

This embodiment also provides a method for manufacturing a coaxial TSV interconnection structure, including the following steps:

(1) Forming TSVs on the silicon substrate 101 by means of etching or laser drilling;

(2) A heavily doped layer is formed on the sidewall of the TSV, and the doping method is diffusion doping or ion implantation;

(3) Form an external conductive connection member on the surface of the heavily doped layer by evaporation, sputtering, electroplating, chemical plating, chemical vapor deposition or physical vapor deposition, and then perform annealing and alloying treatment at 300°C-500°C. The interface between the heavily doped layer 103 and the external conductive connection member 104 forms an ohmic contact;

(4) Forming at least one layer of conductive material on the surface of the outer conductive connection member 104 by sputtering, evaporation or chemical vapor deposition, which is in contact with the insulating layer 105;

(5) Fill the insulating material in the TSV by spin coating;

(6) Forming the insulating layer 105 by laser drilling in the TSV filled with insulating material;

(7) Forming the inner conductive connection member 106 on the surface of the insulating layer by means of electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, reflow or molten metal filling.

Example 2:

As shown in FIG. 2, in the coaxial TSV interconnection structure provided by this embodiment, the inner conductive connection member 106 is filled in a ring and surrounded by an insulating layer 105. Other structural features and manufacturing methods are the same as those of the embodiment shown in FIG. 1 1 same as described.

Example 3:

As shown in FIG. 3 , in the coaxial TSV interconnection structure provided in this embodiment, the TSVs are tapered holes, and other structural features and manufacturing methods are the same as those in Embodiment 1 shown in FIG. 1 .

Example 4:

As shown in FIG. 4 , in the coaxial TSV interconnection structure provided in this embodiment, the heavily doped layer and the external conductive connecting member can extend to the upper and lower surfaces of the silicon substrate. The method of manufacturing this structure is basically the same as the method in Example 1, except that when forming the heavily doped layer and the external conductive connection member, the heavily doped layer is not only formed in the through-silicon hole, but also on the upper and lower surfaces of the silicon substrate. and external conductive connection members.

The coaxial TSV interconnection structure of the present invention can be used to enhance the robustness of TSVs, can isolate noise, eliminate crosstalk, shield EMI, weaken the parasitic effects of TSVs, reduce transmission loss, and improve high-frequency performance ; At the same time, it is convenient to measure the properties of the insulating layer, without additionally manufacturing a measurement structure, and the properties of the insulating layer can be obtained only by measuring the insulating properties between the outer conductive connecting member and the inner conductive connecting member.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (20)

1. a coaxial interconnecting silicon through holes structure is characterized in that, comprising:

Silicon chip;

The silicon through hole runs through said silicon chip;

Heavily doped layer is positioned at the sidewall of said silicon through hole;

Outer conduction connecting elements is centered on by said heavily doped layer;

At least one layer insulating is centered on by said outer conduction connecting elements;

At least conduction connecting elements in one deck is centered on by said insulating barrier, forms coaxial configuration with said outer conduction connecting elements.

2. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said silicon through hole is straight hole or bellmouth.

3. coaxial interconnecting silicon through holes structure as claimed in claim 1, it is characterized in that: said heavily doped layer is positioned at the surface of silicon chip, and said outer conduction connecting elements is positioned on the said heavily doped layer on said silicon chip surface.

4. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the conduction connecting elements is solid construction or loop configuration in said.

5. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said insulating barrier and said interior conduction connecting elements repeat to be arranged alternately, and form many annular coaxials structure.

6. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said silicon chip is p type silicon or n type silicon.

7. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the doped chemical of said heavily doped layer is III A family or V A family element, and doping type is identical with the silicon chip type or opposite.

8. coaxial interconnecting silicon through holes structure as claimed in claim 7, it is characterized in that: the concentration of the doped chemical of said heavily doped layer is greater than 10 ¹²Atom/cm ³

9. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said outer conduction connecting elements comprises one deck contact material at least.

10. coaxial interconnecting silicon through holes structure as claimed in claim 9 is characterized in that: said contact material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi ₂), platinum silicide (PtSi), cobalt silicide (CoSi ₂) and tungsten silicide (WSi ₂) in one or more.

11. coaxial interconnecting silicon through holes structure as claimed in claim 9 is characterized in that: said contact material and said heavily doped layer form ohmic contact.

12. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said outer conduction connecting elements comprises layer of conductive material at least.

13. coaxial interconnecting silicon through holes structure as claimed in claim 12 is characterized in that: said electric conducting material is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, the polysilicon; Said electric conducting material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi ₂), titanium nitride (TiN), tungsten (W), molybdenum silicide (MoSi ₂), platinum silicide (PtSi), cobalt silicide (CoSi ₂) and tungsten silicide (WSi ₂) in one or more.

14. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said insulating barrier comprises one deck insulating material at least.

15. coaxial interconnecting silicon through holes structure as claimed in claim 14 is characterized in that: said insulating material is glass, silica (SiO ₂), silicon nitride (Si ₃N ₄), silicon oxynitride (SiON), tantalum oxide (Ta ₂O ₅), aluminium oxide (Al ₂O ₃), in the polymer one or more.

16. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the material of conduction connecting elements is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, polysilicon, CNT, the conducting resinl in said.

17. the manufacturing approach of a coaxial interconnecting silicon through holes structure is characterized in that, comprises the steps:

On silicon chip, form the silicon through hole;

On the sidewall of said silicon through hole, form heavily doped layer;

Conduction connecting elements outside said heavily doped layer surface forms;

Conduction connecting elements surface forms insulating barrier outside said;

Conduction connecting elements in said surface of insulating layer forms.

18. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17 is characterized in that, on silicon chip, after the formation silicon through hole, forms heavily doped layer on the upper and lower surface of said silicon chip said.

19. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17 is characterized in that: the formation of said heavily doped layer is injected through ion or the method for diffusing, doping realizes that the concentration of doping is greater than 10 ¹²Atom/cm ³

20. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17; It is characterized in that: said outer conduction coupling member comprises one deck contact material at least; After said contact material forms through the annealed alloy processing; Form ohmic contact with heavily doped layer, annealing temperature is at 300 ℃-500 ℃.

Images