CN102412228A - Coaxial through-silicon via interconnection structure and manufacturing method thereof - Google Patents

Coaxial through-silicon via interconnection structure and manufacturing method thereof Download PDF

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CN102412228A
CN102412228A CN2011103365352A CN201110336535A CN102412228A CN 102412228 A CN102412228 A CN 102412228A CN 2011103365352 A CN2011103365352 A CN 2011103365352A CN 201110336535 A CN201110336535 A CN 201110336535A CN 102412228 A CN102412228 A CN 102412228A
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silicon
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CN102412228B (en
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赫然
王惠娟
于大全
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明涉及微电子封装技术领域,具体涉及一种同轴硅通孔互连结构。所述互连结构,包括:硅基片;硅通孔,贯穿硅基片;重掺杂层,位于硅通孔的侧壁;外导电连接构件,被重掺杂层围绕;至少一层绝缘层,被外导电连接构件围绕;至少一层内导电连接构件,被绝缘层围绕,与外导电连接构件形成同轴结构。本发明还提供一种同轴硅通孔互连结构的制造方法。本发明可用于增强硅通孔的鲁棒性,可以隔离噪声,消除串扰,屏蔽EMI,减小传输损耗,消弱硅通孔寄生效应,可改善高频性能;同时便于测量绝缘层特性,不需额外制造测量结构,只需测量外导电连接构件和内导电连接构件之间的绝缘特性即可得到绝缘层特性。

The present invention relates to the field of microelectronic packaging technology, and in particular to a coaxial through silicon via interconnection structure. The interconnection structure comprises: a silicon substrate; a through silicon via, which penetrates the silicon substrate; a heavily doped layer, which is located on the side wall of the through silicon via; an external conductive connection member, which is surrounded by the heavily doped layer; at least one insulating layer, which is surrounded by the external conductive connection member; at least one inner conductive connection member, which is surrounded by the insulating layer and forms a coaxial structure with the external conductive connection member. The present invention also provides a method for manufacturing a coaxial through silicon via interconnection structure. The present invention can be used to enhance the robustness of through silicon vias, isolate noise, eliminate crosstalk, shield EMI, reduce transmission loss, weaken the parasitic effect of through silicon vias, and improve high-frequency performance; at the same time, it is easy to measure the characteristics of the insulating layer, and there is no need to manufacture an additional measurement structure. The characteristics of the insulating layer can be obtained by measuring the insulation characteristics between the external conductive connection member and the inner conductive connection member.

Description

同轴硅通孔互连结构及其制造方法Coaxial through-silicon via interconnection structure and manufacturing method thereof

技术领域 technical field

 本发明涉及微电子封装技术领域,具体涉及一种同轴硅通孔互连结构及其制造方法。 The present invention relates to the technical field of microelectronic packaging, in particular to a coaxial through-silicon via interconnection structure and a manufacturing method thereof.

背景技术 Background technique

随着人们对电子产品向小型化、高性能、多功能等方向的发展的要求,研究人员努力探求将电子系统越做越小,性能越来越强,功能越做越多,由此产生了许多新技术、新材料和新设计,其中三维封装技术以及系统级封装(System-in-Package,SiP)技术就是这些技术的典型代表。 With people's requirements for the development of electronic products in the direction of miniaturization, high performance, and multi-function, researchers strive to make electronic systems smaller and smaller, with stronger performance and more functions. Many new technologies, new materials and new designs, among which three-dimensional packaging technology and system-in-package (System-in-Package, SiP) technology are typical representatives of these technologies.

三维封装技术,是指在不改变封装体尺寸的前提下,在同一个封装体内于垂直方向叠放两个以上芯片的封装技术。而将一个系统或子系统的全部或大部份电子功能配置在一个封装体中,就实现了系统级封装。硅通孔互连技术正是实现三维封装和系统级封装的关键技术之一。硅通孔互连结构是垂直互连,这样一方面可以在垂直方向对芯片进行堆叠,实现三维集成,另一方面,垂直互连大大缩短了互连线的长度,集成系统的电气性能将得到很大的提升。另外,随着芯片管脚数进一步增多和管脚节距的进一步缩小,受有机基板工艺的限制,传统基板线条微细化大大提高了制作成本,并难以满足应用的要求。应用硅通孔互连的转接板技术则是应对这些问题的一种有效解决方案。由于使用半导体的工艺制程,应用硅通孔互连的转接板可以得到很高密度的布线和很小的节距。而且,硅转接板的热膨胀系数与芯片相近,这样可以减小热膨胀系数的失配,从而避免很多问题,极大地提高了封装体的热机械可靠性。 Three-dimensional packaging technology refers to the packaging technology that stacks two or more chips in the same package in the vertical direction without changing the size of the package. System-in-package is realized by disposing all or most of the electronic functions of a system or subsystem in one package. Through-silicon via interconnect technology is one of the key technologies to realize three-dimensional packaging and system-in-package. The through-silicon via interconnection structure is a vertical interconnection, so that on the one hand, chips can be stacked in the vertical direction to achieve three-dimensional integration. On the other hand, the vertical interconnection greatly shortens the length of the interconnection line, and the electrical performance of the integrated system will be improved. Great improvement. In addition, with the further increase in the number of chip pins and the further shrinking of the pin pitch, limited by the organic substrate process, the miniaturization of the traditional substrate lines greatly increases the production cost, and it is difficult to meet the application requirements. The interposer technology using TSV interconnection is an effective solution to these problems. Due to the use of semiconductor process technology, the interposer board using through-silicon via interconnection can obtain very high-density wiring and small pitch. Moreover, the thermal expansion coefficient of the silicon interposer is similar to that of the chip, which can reduce the mismatch of thermal expansion coefficients, thereby avoiding many problems and greatly improving the thermomechanical reliability of the package.

但是,随着电子系统频率越来越高,硅通孔密度越来越大,以及系统级封装中集成的芯片和元器件越来越多,电磁干扰(EMI)问题成为电子系统设计中是必须要考虑的一个重要的因素。电磁干扰也被称为射频干扰(RFI),是由带有变化电信号的电子电路和元件发出的电磁辐射引起的。电磁干扰会影响甚至破坏电子系统的正常工作。目前有三种主要方式用来改善或消除EMI。第一种技术是将敏感元件与电磁辐射源物理隔离。第二种技术是使用旁路或去耦电容和过滤器将不要的干扰信号接地。第三种技术是使用法拉第笼(Faraday cage)或阻隔外壳来屏蔽敏感元件或产生EMI的元件。在众多技术中,采用同轴互连结构,可以有效实现屏蔽EMI的效果。 However, as the frequency of electronic systems increases, the density of through-silicon vias increases, and more and more chips and components are integrated in system-in-packages, the problem of electromagnetic interference (EMI) has become a must in the design of electronic systems. An important factor to consider. Electromagnetic interference, also known as radio frequency interference (RFI), is caused by electromagnetic radiation emitted by electronic circuits and components with varying electrical signals. Electromagnetic interference can affect or even destroy the normal operation of electronic systems. There are currently three main approaches used to improve or eliminate EMI. The first technique is to physically isolate sensitive components from the source of electromagnetic radiation. The second technique is to use bypass or decoupling capacitors and filters to ground unwanted interfering signals. A third technique is to use a Faraday cage or barrier enclosure to shield sensitive or EMI-generating components. Among many technologies, the use of coaxial interconnection structures can effectively achieve the effect of shielding EMI.

应用已有的技术,可以形成硅通孔互连同轴结构,但是在工艺复杂性、成本和电性能方面都存在着各种的问题。例如,IBM在IBM J. RES. & DEV. VOL. 52 NO. 6发表的论文“Fabrication and characterization of robust through-silicon vias for silicon-carrier applications”所述,可以形成一个外环为掺杂多晶硅和内芯为铜的同轴硅通孔互连结构,但是外环和内芯的刻蚀与填充要分步进行,如此则增加了工艺复杂性和成本支出。CEA-LETI在Electronics Packaging Technology Conference, 2009. EPTC’09. 11th, 2009, pp. 772-777.发表的论文“Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results”所述,可以形成多环形的钨填充的硅通孔,但是由于其互连都是环形结构,互连的电阻受钨层的厚度限制而阻值较大,导电性不佳。 Applying the existing technology, it is possible to form a TSV interconnection coaxial structure, but there are various problems in terms of process complexity, cost and electrical performance. For example, as described in the paper "Fabrication and characterization of robust through-silicon vias for silicon-carrier applications" published by IBM in IBM J. RES. & DEV. VOL. 52 NO. 6, an outer ring can be formed for doping polysilicon and Coaxial TSV interconnection structure with copper inner core, but the etching and filling of the outer ring and the inner core have to be carried out step by step, which increases the process complexity and cost expenditure. As stated in the paper "Mid-process through silicon vias technology using tungsten metallization: Process optimization and electrical results" published by CEA-LETI at Electronics Packaging Technology Conference, 2009. EPTC'09. 11th, 2009, pp. 772-777. Multiple ring-shaped tungsten-filled TSVs are formed, but because the interconnection is in a ring structure, the resistance of the interconnection is limited by the thickness of the tungsten layer, and the resistance value is relatively large, and the conductivity is not good.

另外,由于硅衬底是半导体而非绝缘体,硅通孔互连与硅衬底之间还存在着寄生效应,这样也会在很大程度上使系统的电学性能受到影响。 In addition, since the silicon substrate is a semiconductor rather than an insulator, there are parasitic effects between the TSV interconnection and the silicon substrate, which will also greatly affect the electrical performance of the system.

发明内容 Contents of the invention

本发明的目的在于提供一种同轴硅通孔互连结构,有效屏蔽EMI,减小传输损耗,消弱硅通孔寄生效应,增强硅通孔的鲁棒性。 The purpose of the present invention is to provide a coaxial TSV interconnection structure, which can effectively shield EMI, reduce transmission loss, weaken the parasitic effect of TSV, and enhance the robustness of TSV.

本发明的另一目的在于提供一种同轴硅通孔互连结构的制造方法。 Another object of the present invention is to provide a method for manufacturing a coaxial TSV interconnection structure.

为了达到上述目的,本发明采用的技术方案为: In order to achieve the above object, the technical scheme adopted in the present invention is:

一种同轴硅通孔互连结构,包括: A coaxial through-silicon via interconnection structure, comprising:

硅基片; Silicon substrate;

硅通孔,贯穿所述硅基片; through-silicon vias, penetrating through the silicon substrate;

重掺杂层,位于所述硅通孔的侧壁; a heavily doped layer located on the sidewall of the TSV;

外导电连接构件,被所述重掺杂层围绕; an outer conductive connection member surrounded by the heavily doped layer;

至少一层绝缘层,被所述外导电连接构件围绕; at least one insulating layer surrounded by said outer conductive connection member;

至少一层内导电连接构件,被所述绝缘层围绕,与所述外导电连接构件形成同轴结构。 At least one layer of inner conductive connection members, surrounded by the insulating layer, forms a coaxial structure with the outer conductive connection members.

上述方案中,所述硅通孔为直孔或锥形孔。 In the above solution, the TSVs are straight holes or tapered holes.

上述方案中,所述重掺杂层位于硅基片的表面,所述外导电连接构件位于所述硅基片表面的所述重掺杂层之上。 In the above solution, the heavily doped layer is located on the surface of the silicon substrate, and the external conductive connection member is located on the heavily doped layer on the surface of the silicon substrate.

上述方案中,所述内导电连接构件为实心结构或环形结构。 In the above solution, the inner conductive connecting member is a solid structure or a ring structure.

上述方案中,所述绝缘层和所述内导电连接构件重复交替设置,形成多环形同轴结构。 In the above solution, the insulating layer and the inner conductive connecting member are repeatedly and alternately arranged to form a multi-ring coaxial structure.

上述方案中,所述硅基片为p型硅或者n型硅。 In the above solution, the silicon substrate is p-type silicon or n-type silicon.

上述方案中,所述重掺杂层的掺杂元素为III A族或者V A族元素,掺杂类型与硅基片类型相同或相反。 In the above scheme, the doping elements of the heavily doped layer are Group III A or Group VA elements, and the doping type is the same as or opposite to that of the silicon substrate.

上述方案中,所述重掺杂层的掺杂元素的浓度大于1012原子/cm3In the above solution, the doping element concentration of the heavily doped layer is greater than 10 12 atoms/cm 3 .

上述方案中,所述外导电连接构件包括至少一层接触材料。 In the above solution, the outer conductive connection member includes at least one layer of contact material.

上述方案中,所述接触材料为铝(Al)、铝-硅、硅化钛(TiSi2)、氮化钛(TiN)、钨、硅化钼(MoSi2)、硅化铂(PtSi)、硅化钴(CoSi2)和硅化钨(WSi2)中的一种或几种。 In the above scheme, the contact material is aluminum (Al), aluminum-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi 2 ), platinum silicide (PtSi), cobalt silicide (CoSi 2 ) and one or more of tungsten silicide (WSi 2 ).

上述方案中,所述接触材料与所述重掺杂层形成欧姆接触。 In the above solution, the contact material forms an ohmic contact with the heavily doped layer.

上述方案中,所述外导电连接构件包括至少一层导电材料。 In the above solution, the outer conductive connection member includes at least one layer of conductive material.

上述方案中,所述导电材料为镍、铁、铜、铝、铂、金、钯、钛、钽、钨、锌、银、锡及其一元或二元合金、多晶硅中的一种或几种;所述导电材料为铝(Al)、铝-硅、硅化钛(TiSi2)、氮化钛(TiN)、钨、硅化钼(MoSi2)、硅化铂(PtSi)、硅化钴(CoSi2)和硅化钨(WSi2)中的一种或几种。 In the above scheme, the conductive material is one or more of nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and their single or binary alloys, polysilicon ; The conductive material is aluminum (Al), aluminum-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi 2 ), platinum silicide (PtSi), cobalt silicide (CoSi 2 ) and One or several kinds of tungsten silicide (WSi 2 ).

上述方案中,所述绝缘层包括至少一层绝缘材料。 In the solution above, the insulating layer includes at least one layer of insulating material.

上述方案中,所述绝缘材料为玻璃、氧化硅(SiO2)、氮化硅(Si3N4)、氧氮化硅(SiON)、氧化钽(Ta2O5)、氧化铝(Al2O3)、聚合物中的一种或几种。 In the above solution, the insulating material is glass, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), one or more of polymers.

上述方案中,所述内导电连接构件的材料为镍、铁、铜、铝、铂、金、鈀、钛、钽、钨、锌、银、锡及其一元或二元合金、多晶硅、碳纳米管、导电胶中的一种或几种。 In the above scheme, the material of the internal conductive connecting member is nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and their single or binary alloys, polysilicon, carbon nano One or more of tubes and conductive adhesives.

一种同轴硅通孔互连结构的制造方法,包括如下步骤: A method for manufacturing a coaxial through-silicon via interconnection structure, comprising the steps of:

在硅基片上形成硅通孔; Forming through-silicon vias on silicon substrates;

在所述硅通孔的侧壁上形成重掺杂层; forming a heavily doped layer on the sidewall of the TSV;

在所述重掺杂层表面形成外导电连接构件; forming an external conductive connection member on the surface of the heavily doped layer;

在所述外导电连接构件表面形成绝缘层; forming an insulating layer on the surface of the outer conductive connection member;

在所述绝缘层表面形成内导电连接构件。 An inner conductive connection member is formed on the surface of the insulating layer.

上述方案中,在所述在硅基片上形成硅通孔之后,在所述硅基片上、下表面形成重掺杂层。 In the above solution, after the through-silicon vias are formed on the silicon substrate, heavily doped layers are formed on the upper and lower surfaces of the silicon substrate.

上述方案中,所述重掺杂层的形成通过离子注入或者扩散掺杂的方法实现,掺杂的浓度大于1012原子/cm3In the above solution, the formation of the heavily doped layer is realized by ion implantation or diffusion doping, and the doping concentration is greater than 10 12 atoms/cm 3 .

上述方案中,所述外导电连结构件包括至少一层接触材料,所述接触材料形成后经过退火合金化处理,与重掺杂层形成欧姆接触,退火温度在300℃-500℃。 In the above scheme, the external conductive connecting structure includes at least one layer of contact material, and the contact material is annealed and alloyed after formation to form an ohmic contact with the heavily doped layer, and the annealing temperature is 300°C-500°C.

与现有技术方案相比,本发明采用的技术方案产生的有益效果如下: Compared with prior art solutions, the beneficial effects produced by the technical solutions adopted in the present invention are as follows:

本发明的同轴硅通孔互连结构可用于增强硅通孔的鲁棒性,可以隔离噪声,消除串扰,屏蔽EMI,减小传输损耗,消弱硅通孔寄生效应,可改善高频性能;同时便于测量绝缘层特性,不需额外制造测量结构,只需测量外导电连接构件和内导电连接构件之间的绝缘特性即可得到绝缘层特性。 The coaxial TSV interconnection structure of the present invention can be used to enhance the robustness of TSVs, can isolate noise, eliminate crosstalk, shield EMI, reduce transmission loss, weaken parasitic effects of TSVs, and improve high-frequency performance ; At the same time, it is convenient to measure the properties of the insulating layer, without additionally manufacturing a measurement structure, and the properties of the insulating layer can be obtained only by measuring the insulating properties between the outer conductive connecting member and the inner conductive connecting member.

附图说明 Description of drawings

图1为本发明实施例提供的同轴硅通孔互连结构的示意图; FIG. 1 is a schematic diagram of a coaxial TSV interconnection structure provided by an embodiment of the present invention;

图2为本发明另一实施例提供的同轴硅通孔互连结构的示意图; FIG. 2 is a schematic diagram of a coaxial TSV interconnection structure provided by another embodiment of the present invention;

图3为本发明另一实施例提供的同轴硅通孔互连结构的示意图; 3 is a schematic diagram of a coaxial TSV interconnection structure provided by another embodiment of the present invention;

图4为本发明另一实施例提供的同轴硅通孔互连结构的示意图。 FIG. 4 is a schematic diagram of a coaxial TSV interconnection structure provided by another embodiment of the present invention.

具体实施方式 Detailed ways

下面结合附图和实施例对本发明技术方案进行详细描述。 The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

实施例1: Example 1:

如图1所示,本实施例提供的同轴硅通孔互连结构,包括硅基片101、硅通孔、重掺杂层103、外导电连接构件104、绝缘层105和内导电连接构件106。其中硅基片为p型硅,硅通孔为直孔,贯穿硅基片101。重掺杂层103,位于硅通孔的硅侧壁,掺杂元素为III A族或者V A族元素,掺杂类型为p型杂质,例如硼离子,掺杂浓度为1019原子/cm3,掺杂深度为1微米。外导电连接构件104至少包括一层接触材料,被重掺杂层103围绕,接触材料为铝(Al)、铝-硅、硅化钛(TiSi2)、氮化钛(TiN)、钨、硅化钼(MoSi2)、硅化铂(PtSi)、硅化钴(CoSi2)和硅化钨(WSi2)中的一种或几种,厚度为0.5微米-5微米,接触材料在重掺杂层103与外导电连接构件104界面形成欧姆接触。绝缘层105,被外导电连接构件104围绕,其形成材料包括玻璃、氧化硅(SiO2)、氮化硅(Si3N4)、氧氮化硅(SiON)、氧化钽(Ta2O5)、氧化铝(Al2O3)、聚合物中的一种或几种,聚合物可以为聚酰亚胺(PI)、苯并环丁烯(BCB)、聚乙烯、聚苯并咪唑(PBO)或者乙烯丙烯酸共聚物(EAA),厚度为1微米-200微米。内导电连接构件106为实心填充,被绝缘层105围绕,与外导电连接构件104绝缘,其形成材料为镍、铁、铜、铝、铂、金、鈀、钛、钨、锌、银、锡及其一元或二元合金(合金化元素包括银、金、镍、铁、钴、锰、铼)、多晶硅、碳纳米管或者导电胶中的一种或几种。 As shown in FIG. 1, the coaxial TSV interconnection structure provided by this embodiment includes a silicon substrate 101, a TSV, a heavily doped layer 103, an outer conductive connection member 104, an insulating layer 105 and an inner conductive connection member. 106. The silicon substrate is p-type silicon, and the through-silicon vias are straight holes, penetrating through the silicon substrate 101 . The heavily doped layer 103 is located on the silicon sidewall of the TSV, and the doping element is group III A or group VA element, and the doping type is p-type impurity, such as boron ion, and the doping concentration is 10 19 atoms/cm 3 , The doping depth is 1 micron. The outer conductive connection member 104 includes at least one layer of contact material, surrounded by the heavily doped layer 103, and the contact material is aluminum (Al), aluminum-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide ( One or more of MoSi 2 ), platinum silicide (PtSi), cobalt silicide (CoSi 2 ) and tungsten silicide (WSi 2 ), with a thickness of 0.5 microns to 5 microns, and the contact material is between the heavily doped layer 103 and the outer conductive The connection member 104 interface forms an ohmic contact. The insulating layer 105 is surrounded by the outer conductive connection member 104, and its forming material includes glass, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), one or more of polymers, polymers can be polyimide (PI), benzocyclobutene (BCB), polyethylene, polybenzimidazole ( PBO) or ethylene acrylic acid copolymer (EAA), with a thickness of 1 micron to 200 microns. The inner conductive connection member 106 is solid filled, surrounded by the insulating layer 105, and insulated from the outer conductive connection member 104, and its forming material is nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tungsten, zinc, silver, tin One or more of its one or two element alloys (alloying elements include silver, gold, nickel, iron, cobalt, manganese, rhenium), polysilicon, carbon nanotubes or conductive glue.

本实施例中,硅基片101还可以是n型硅,重掺杂层103的掺杂类型可以与硅基片类型相同或相反。 In this embodiment, the silicon substrate 101 may also be n-type silicon, and the doping type of the heavily doped layer 103 may be the same as or opposite to that of the silicon substrate.

本实施例中,外导电连接构件104还包括至少一层导电材料,导电材料为镍、铁、铜、铝、铂、金、钯、钛、钽、钨、锌、银、锡及其一元或二元合金(合金化元素包括银、金、镍、铁、钴、锰、铼)、多晶硅中的一种或几种;所述导电材料也可以与接触材料相同,为铝(Al)、铝-硅、硅化钛(TiSi2)、氮化钛(TiN)、钨(W)、硅化钼(MoSi2)、硅化铂(PtSi)、硅化钴(CoSi2)和硅化钨(WSi2)中的一种或几种。 In this embodiment, the outer conductive connecting member 104 also includes at least one layer of conductive material, the conductive material is nickel, iron, copper, aluminum, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and their unary or One or more of binary alloys (alloying elements include silver, gold, nickel, iron, cobalt, manganese, rhenium), polysilicon; the conductive material can also be the same as the contact material, aluminum (Al), aluminum - One of silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten (W), molybdenum silicide (MoSi 2 ), platinum silicide (PtSi), cobalt silicide (CoSi 2 ) and tungsten silicide (WSi 2 ) species or several.

本实施例中,绝缘层105和内导电连接构件106可以重复交替设置,形成环形同轴结构。 In this embodiment, the insulating layer 105 and the inner conductive connecting member 106 may be repeatedly and alternately arranged to form a ring-shaped coaxial structure.

本实施例还提供一种同轴硅通孔互连结构的制造方法,包括如下步骤: This embodiment also provides a method for manufacturing a coaxial TSV interconnection structure, including the following steps:

(1)在硅基片101上采用刻蚀或者激光打孔的方法形成硅通孔; (1) Forming TSVs on the silicon substrate 101 by means of etching or laser drilling;

(2)在硅通孔的侧壁上形成重掺杂层,掺杂方法为扩散掺杂或者离子注入; (2) A heavily doped layer is formed on the sidewall of the TSV, and the doping method is diffusion doping or ion implantation;

(3)在重掺杂层表面通过蒸发、溅射、电镀、化学镀、化学气相沉积或者物理气相沉积的方法形成外导电连接构件,然后在300℃-500℃下进行退火合金化处理,在重掺杂层103与外导电连接构件104界面形成欧姆接触; (3) Form an external conductive connection member on the surface of the heavily doped layer by evaporation, sputtering, electroplating, chemical plating, chemical vapor deposition or physical vapor deposition, and then perform annealing and alloying treatment at 300°C-500°C. The interface between the heavily doped layer 103 and the external conductive connection member 104 forms an ohmic contact;

(4)通过溅射、蒸发或化学气相沉积方法在外导电连接构件104表面形成至少一层导电材料,与绝缘层105接触; (4) Forming at least one layer of conductive material on the surface of the outer conductive connection member 104 by sputtering, evaporation or chemical vapor deposition, which is in contact with the insulating layer 105;

(5)在硅通孔内通过旋涂的方法填充绝缘材料; (5) Fill the insulating material in the TSV by spin coating;

(6)在填充绝缘材料的硅通孔内通过激光打孔的方法形成绝缘层105; (6) Forming the insulating layer 105 by laser drilling in the TSV filled with insulating material;

(7)在所述绝缘层表面通过电镀、化学镀、化学气相沉积、物理气相沉积、回流或者熔融金属填充的方法形成内导电连接构件106。 (7) Forming the inner conductive connection member 106 on the surface of the insulating layer by means of electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, reflow or molten metal filling.

实施例2: Example 2:

如图2所示,本实施例提供的同轴硅通孔互连结构中,内导电连接构件106为环形填充,被绝缘层105围绕,其他结构特征和制造方法与图1所示的实施例1所述相同。 As shown in FIG. 2, in the coaxial TSV interconnection structure provided by this embodiment, the inner conductive connection member 106 is filled in a ring and surrounded by an insulating layer 105. Other structural features and manufacturing methods are the same as those of the embodiment shown in FIG. 1 1 same as described.

实施例3: Example 3:

如图3所示,本实施例提供的同轴硅通孔互连结构中,硅通孔为锥形孔,其他结构特征和制造方法与图1所示的实施例1相同。 As shown in FIG. 3 , in the coaxial TSV interconnection structure provided in this embodiment, the TSVs are tapered holes, and other structural features and manufacturing methods are the same as those in Embodiment 1 shown in FIG. 1 .

实施例4: Example 4:

如图4所示,本实施例提供的同轴硅通孔互连结构中,重掺杂层和外导电连接构件可延伸至硅基片上、下表面。制造此结构的方法与实施例1中的方法基本相同,只是在形成重掺杂层和外导电连接构件时,不仅仅在硅通孔内,在硅基片上、下表面也形成重掺杂层和外导电连接构件。 As shown in FIG. 4 , in the coaxial TSV interconnection structure provided in this embodiment, the heavily doped layer and the external conductive connecting member can extend to the upper and lower surfaces of the silicon substrate. The method of manufacturing this structure is basically the same as the method in Example 1, except that when forming the heavily doped layer and the external conductive connection member, the heavily doped layer is not only formed in the through-silicon hole, but also on the upper and lower surfaces of the silicon substrate. and external conductive connection members.

本发明的同轴硅通孔互连结构可用于增强硅通孔的鲁棒性,可以隔离噪声,消除串扰,屏蔽EMI,消弱硅通孔寄生效应,减小传输损耗,可改善高频性能;同时便于测量绝缘层特性,不需额外制造测量结构,只需测量外导电连接构件和内导电连接构件之间的绝缘特性即可得到绝缘层特性。 The coaxial TSV interconnection structure of the present invention can be used to enhance the robustness of TSVs, can isolate noise, eliminate crosstalk, shield EMI, weaken the parasitic effects of TSVs, reduce transmission loss, and improve high-frequency performance ; At the same time, it is convenient to measure the properties of the insulating layer, without additionally manufacturing a measurement structure, and the properties of the insulating layer can be obtained only by measuring the insulating properties between the outer conductive connecting member and the inner conductive connecting member.

以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。 The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (20)

1. a coaxial interconnecting silicon through holes structure is characterized in that, comprising:
Silicon chip;
The silicon through hole runs through said silicon chip;
Heavily doped layer is positioned at the sidewall of said silicon through hole;
Outer conduction connecting elements is centered on by said heavily doped layer;
At least one layer insulating is centered on by said outer conduction connecting elements;
At least conduction connecting elements in one deck is centered on by said insulating barrier, forms coaxial configuration with said outer conduction connecting elements.
2. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said silicon through hole is straight hole or bellmouth.
3. coaxial interconnecting silicon through holes structure as claimed in claim 1, it is characterized in that: said heavily doped layer is positioned at the surface of silicon chip, and said outer conduction connecting elements is positioned on the said heavily doped layer on said silicon chip surface.
4. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the conduction connecting elements is solid construction or loop configuration in said.
5. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said insulating barrier and said interior conduction connecting elements repeat to be arranged alternately, and form many annular coaxials structure.
6. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said silicon chip is p type silicon or n type silicon.
7. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the doped chemical of said heavily doped layer is III A family or V A family element, and doping type is identical with the silicon chip type or opposite.
8. coaxial interconnecting silicon through holes structure as claimed in claim 7, it is characterized in that: the concentration of the doped chemical of said heavily doped layer is greater than 10 12Atom/cm 3
9. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said outer conduction connecting elements comprises one deck contact material at least.
10. coaxial interconnecting silicon through holes structure as claimed in claim 9 is characterized in that: said contact material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi2), titanium nitride (TiN), tungsten, molybdenum silicide (MoSi 2), platinum silicide (PtSi), cobalt silicide (CoSi 2) and tungsten silicide (WSi 2) in one or more.
11. coaxial interconnecting silicon through holes structure as claimed in claim 9 is characterized in that: said contact material and said heavily doped layer form ohmic contact.
12. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said outer conduction connecting elements comprises layer of conductive material at least.
13. coaxial interconnecting silicon through holes structure as claimed in claim 12 is characterized in that: said electric conducting material is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, the polysilicon; Said electric conducting material is aluminium (Al), aluminium-silicon, titanium silicide (TiSi 2), titanium nitride (TiN), tungsten (W), molybdenum silicide (MoSi 2), platinum silicide (PtSi), cobalt silicide (CoSi 2) and tungsten silicide (WSi 2) in one or more.
14. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: said insulating barrier comprises one deck insulating material at least.
15. coaxial interconnecting silicon through holes structure as claimed in claim 14 is characterized in that: said insulating material is glass, silica (SiO 2), silicon nitride (Si 3N 4), silicon oxynitride (SiON), tantalum oxide (Ta 2O 5), aluminium oxide (Al 2O 3), in the polymer one or more.
16. coaxial interconnecting silicon through holes structure as claimed in claim 1 is characterized in that: the material of conduction connecting elements is one or more in nickel, iron, copper, aluminium, platinum, gold, palladium, titanium, tantalum, tungsten, zinc, silver, tin and monobasic thereof or bianry alloy, polysilicon, CNT, the conducting resinl in said.
17. the manufacturing approach of a coaxial interconnecting silicon through holes structure is characterized in that, comprises the steps:
On silicon chip, form the silicon through hole;
On the sidewall of said silicon through hole, form heavily doped layer;
Conduction connecting elements outside said heavily doped layer surface forms;
Conduction connecting elements surface forms insulating barrier outside said;
Conduction connecting elements in said surface of insulating layer forms.
18. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17 is characterized in that, on silicon chip, after the formation silicon through hole, forms heavily doped layer on the upper and lower surface of said silicon chip said.
19. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17 is characterized in that: the formation of said heavily doped layer is injected through ion or the method for diffusing, doping realizes that the concentration of doping is greater than 10 12Atom/cm 3
20. the manufacturing approach of coaxial interconnecting silicon through holes structure as claimed in claim 17; It is characterized in that: said outer conduction coupling member comprises one deck contact material at least; After said contact material forms through the annealed alloy processing; Form ohmic contact with heavily doped layer, annealing temperature is at 300 ℃-500 ℃.
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