CN102411983B

CN102411983B - Random access memory powered according to data dynamics

Info

Publication number: CN102411983B
Application number: CN2010102959005A
Authority: CN
Inventors: 庄景德; 杨皓义; 林宜纬; 黄威; 石维强; 陈家政
Original assignee: Faraday Technology Corp
Current assignee: Faraday Technology Corp
Priority date: 2010-09-21
Filing date: 2010-09-21
Publication date: 2013-12-04
Anticipated expiration: 2030-09-21
Also published as: CN102411983A

Abstract

The invention provides a random access memory powered according to data dynamics. The random access memory has a plurality of memory cells. In one embodiment, memory cells arranged at a same column are coupled with a same contraposition line and correspond to a same power supply circuit. Each memory cell is provided with two inverters, and a power supply circuit is provided with two power switches. To all the memory cells at a same column, two power switches can carry out independent power supply control for two inverters in each memory cell respectively according to the voltage of a bit line, i.e., desired write data of the bit line during write operation. The invention enables both read and write-in of the random access memory to be attended.

Description

Random access memory according to the Data Dynamic power supply

Technical field

The present invention relates to a kind of random access memory, and be particularly related to and a kind ofly to classify basis as, two phase inverters in same row static storage cell carried out respectively to independently-powered control to take into account the random access memory of readwrite performance.

Background technology

Random access memory, be for example static RAM, is one of most important construction assembly of contemporary electronic systems.The layout area of reduction random access memory, reduction random access memory operating voltage are to improve the development trend that the merit dissipative structure is modern random access memory.

Random access memory is provided with and a plurality ofly follows row (column), row (row) is arranged as the storage unit of matrix, and each storage unit stores a data for access.For instance, in six basic transistor (6transistors, 6T) static storage cells, two phase inverters and two gateway transistors are arranged, each phase inverter is formed by a pair of complementary transistor respectively.Wherein, the output terminal of a phase inverter couples the input end of another phase inverter, forms the breech lock framework of latch data; And the output terminal of two phase inverters can be considered a pair of back end, anti-phase with it with the data of one of differential form record respectively.In each storage unit of same row, a pair of back end of each storage unit couples one of them in same pair of bit lines separately via a gateway transistor respectively.In the storage unit of same a line, the gateway transistor of each storage unit couples same character line in grid, makes each gateway transistor according to the conducting between the Control of Voltage corresponding data node of character line and corresponding bit line.In addition, the storage unit of five transistors (5transistors, 5T) and the storage unit of eight transistors (8transistors, 8T) are also arranged.A gateway transistor only is set in five transistor cells, and each storage unit of same row is only via the single bit line access.Eight transistorized storage unit are in order to realize even port (dual-port) or dual-port (two-port) random access memory, and each storage unit can be carried out access by two pairs of bit line.Be provided with two pairs of gateway transistors in eight transistor cells, every a pair of gateway transistor according to the voltage of a pair of character line, control respectively two back end whether conducting to the bit line of a pair of correspondence.

Random access memory can be described below the access running of storage unit.In the time will reading the data of a certain storage unit, corresponding bit line can first be precharged to the high voltage of logical one.Read Qi Shishi, a data node of storage unit can be by corresponding gateway transistor turns to this bit line; If what this back end stored is the logical zero of low-voltage, the phase inverter that the voltage of this bit line will be stored in unit drags down, with the data content of reflection logical zero.When reading while not yet starting, the not conducting of gateway transistor, this back end be n channel metal oxide semiconductor transistor conducting in phase inverter to low-voltage with stored logic 0.But, when reading Qi Shihou, due to this back end can be separately by the gateway transistor turns to high-tension bit line, therefore the voltage of this back end can raise.Say equivalently, when reading while starting to carry out, the n channel metal oxide semiconductor transistor in gateway transistor AND gate phase inverter can be usingd this back end and be carried out dividing potential drop as dividing point between logical one high voltage and logical zero low-voltage.If it is too high that the voltage of this back end is drawn high, will surpass the escape voltage (trip voltage) of storage unit breech lock framework and be stored unit and think logical one by mistake, and be logical one by the data of this back end by the logical zero upset mistakenly via the feedback mechanism of latch circuit.In order to prevent causing wrong Data flipping when the reading out data, when realizing storage unit, usually can adopt one weak (raceway groove is long or narrow, the conducting degree is poor, source electrode and drain between conducting resistance larger) the gateway transistor; Thus, when reading while carrying out, n channel metal oxide semiconductor transistor in phase inverter has lower resistance relatively, can make the voltage ratio of this back end approach the low-voltage of logical zero, and keeps larger noise immunity (margin) with escape voltage.

Gateway transistor is conducive to data and reads, but data are write and can cause negative impact.For example, in the time low logic voltage 0 will being write to a back end of a certain storage unit via a bit line, this back end can be by the gateway transistor turns to this bit line, makes the voltage of this back end can reach the low-voltage of logical zero.Suppose the p channel metal oxide semiconductor transistor conducting in phase inverter originally of this back end to high voltage and stored logic 1, in the time logical zero will being write to this back end, the p channel metal oxide semiconductor transistor in the gateway transistor AND gate phase inverter of conducting is in this back end dividing potential drop.If the gateway transistor a little less than, the voltage of this back end will comparatively approach the high voltage of logical one, is difficult for being pulled low to the low-voltage of logical zero.Say equivalently, when logical zero is write to the back end of logical one, gateway transistor tendency is pulled low to low-voltage by back end, and the p channel metal oxide semiconductor transistor in phase inverter is inclined to back end is maintained to high voltage, and both can vie each other.If the data consideration of reading and adopt weak gateway transistor, the gateway transistor will weaken writing fashionable competitive power, is unfavorable for that data write.On the other hand, in the time high voltage logic 1 will being write to a back end of a certain storage unit via a bit line, this back end can be by the gateway transistor turns to this bit line, makes the voltage of this back end can reach the high voltage of logical one.Suppose the n channel metal oxide semiconductor transistor conducting in phase inverter originally of this back end to low-voltage and stored logic 0, in the time logical one will being write to this back end, the n channel metal oxide semiconductor transistor in the gateway transistor AND gate phase inverter of conducting is in this back end dividing potential drop.If the gateway transistor a little less than, the voltage of this back end will comparatively approach the low-voltage of logical zero, difficult quilt is drawn high the high voltage to logical one.Say equivalently, when logical one is write to the back end of logical zero, gateway transistor tendency draws high back end to high voltage, and the n channel metal oxide semiconductor transistor in phase inverter is inclined to back end is maintained to low-voltage, and both can vie each other.If the data consideration of reading and adopt weak gateway transistor, the gateway transistor will weaken writing fashionable competitive power, is unfavorable for that data write.

In other words, to read the demand write with data be conflicting to data; For the advanced technologies random access memory/storage unit of small size, low-work voltage, above-mentioned contradiction is more obvious.

Summary of the invention

For the problems referred to above, read and write in order to take into account data, the present invention propose a kind of take classify basis, the independently-powered random access memory of two phase inverters according to bit line data (voltage) in each storage unit of same row as.

The purpose of this invention is to provide a kind of random access memory, it includes a plurality of power circuits that are arranged as storage unit and a correspondence of row (column).Each storage unit is provided with one first power end, one second power end and an end, and the position end of a plurality of storage unit all is coupled to same bit line.Be provided with one first phase inverter, one second phase inverter and a gateway transistor in each storage unit.The first phase inverter has a power end, an input end and an output terminal, couples respectively the first power end, one second back end and one first back end.The second phase inverter also has a power end, an input end and an output terminal, couples respectively the second power end, the first back end and the second back end.Gateway transistor one end couples the position end, and the other end couples one of them of the second back end and the first back end.Power circuit is provided with one first feeder ear and one second feeder ear, couples respectively the first power end and second power end of a plurality of storage unit of same row; Power circuit includes a power switch, couple bit line and feeder ear, and receive a write control signal, writing the fashionable decision of the voltage according to bit line whether will be by this first feeder ear conducting to an operating voltage according to this, and when reading, making this first feeder ear and this second feeder ear all be maintained at this operating voltage wherein, this operating voltage is the nominal supply voltages of this random access memory.

In one embodiment of the invention, aforesaid power circuit separately includes an electric power maintainer, couples the first feeder ear; When power switch, not by the feeder ear conducting during to operating voltage, the electric power maintainer provides an electric current in feeder ear.

In one embodiment of the invention, aforesaid power switch includes a power transistor, has a grid and two links, couples respectively bit line, operating voltage and the first feeder ear.

In one embodiment of the invention, aforesaid power switch separately includes a logical circuit, is coupled between grid and bit line; Logical circuit carries out logical operation by the voltage of bit line and a write control signal, and whether power transistor is to determine the first feeder ear conducting to operating voltage according to the operation result of logical circuit.

In one embodiment of the invention, gateway transistor in aforesaid each storage unit is coupled between the first back end and position end, and each storage unit separately is provided with a second end, and separately include one second gateway transistor, be coupled between the second back end and second end; The second end of a plurality of storage unit all is coupled to one second bit line; Whether, and power circuit separately includes one second power switch, the second power switch couples the second bit line and the second feeder ear, to write the fashionable decision of the voltage according to the second bit line will be by the second feeder ear conducting to operating voltage.

In one embodiment of the invention, each storage unit in aforesaid a plurality of storage unit separately is provided with one the 3rd power end and one the 4th power end; The first phase inverter in each storage unit separately is provided with a second source end, couples the 3rd power end; The second phase inverter in each storage unit separately is provided with a second source end, couples the 4th power end; And random access memory separately includes a second source circuit, the second source circuit is provided with one the 3rd feeder ear, couples the 4th power end of a plurality of storage unit; And the second source circuit includes one second power switch, the second power switch couples the 3rd feeder ear of bit line and second source circuit, and whether with the voltage according to bit line, determine will be by the 3rd feeder ear conducting to the second operating voltage of second source circuit; Wherein the second operating voltage and operating voltage are different.

In one embodiment of the invention, aforesaid second source circuit separately includes one second electric power maintainer, and the second electric power maintainer is coupled to the 3rd feeder ear of second source circuit; When the second power switch, during not by feeder ear conducting to the second operating voltage of second source circuit, the second electric power maintainer provides an electric current in the 3rd feeder ear of second source circuit.

In one embodiment of the invention, gateway transistor in aforesaid each storage unit is coupled between the first back end and position end, and each storage unit separately is provided with a second end, one the 3rd power end and one the 4th power end, and separately include one second gateway transistor, be coupled between the second back end and second end; And the first phase inverter in each storage unit separately is provided with a second source end, couple the 3rd power end; The second phase inverter in each storage unit separately is provided with a second source end, couples the 4th power end; The second end of a plurality of storage unit all is coupled to one second bit line, and random access memory separately includes a second source circuit, is provided with one the 3rd feeder ear, couples the 4th power end of a plurality of storage unit; And the second source circuit includes one second power switch, couple the feeder ear of the second bit line and second source circuit, whether with the voltage according to the second bit line, determine will be by the 3rd feeder ear conducting to the second operating voltage of second source circuit; Wherein the second operating voltage and operating voltage are different.

In one embodiment of the invention, gateway transistor in aforesaid each storage unit is coupled between the first back end and position end, and each storage unit separately is provided with a second end and one second gateway transistor, the second gateway transistor is coupled between the first back end and second end; The second end of a plurality of storage unit all is coupled to one second bit line, and the power switch in power circuit according to the voltage of the voltage of bit line and the second bit line whether determine write fashionable by operating voltage conducting to the first feeder ear.

In one embodiment of the invention, include a power transistor in aforesaid power switch, have a grid and two links, two links couple respectively operating voltage and the first feeder ear; One logical circuit, be coupled between grid, bit line and second bit line of power transistor; Logical circuit carries out logical operation by the voltage of the voltage of bit line and the second bit line, and whether power transistor is to determine the first feeder ear conducting to operating voltage according to the operation result of logical circuit.

In the present invention, can first according to data, read demand and adopt weak gateway transistor.For writing demand, in the time logical zero will being write to the back end of a script stored logic 1 via a bit line, the p channel metal oxide semiconductor transistor conducting in one first phase inverter originally of tentation data node is to high voltage, write fashionable, the present invention can reduce via the power supply control to phase inverter the source electrode supply voltage (making its source electrode suspension joint) of its p channel metal oxide semiconductor transistor in the first phase inverter, but maintains the source electrode supply voltage of its p channel metal oxide semiconductor transistor in the second phase inverter.The source electrode supply voltage that reduces the p channel metal oxide semiconductor transistor in the first phase inverter can reduce its source voltage and conducting degree, makes the gateway transistor more easily the back end of script stored logic 1 is pulled low to the low-voltage of logical zero.Simultaneously, concerning the p channel metal oxide semiconductor transistor of the second phase inverter, because its source electrode supply voltage remains unchanged, its conducting degree is unaffected, can be by the voltage fast lifting of corresponding data node the high voltage to logical one.When realizing, the present invention can reduce the source electrode supply voltage according to the p channel metal oxide semiconductor transistor in that phase inverter of voltage (also wanting data writing) judgement reply of bit line.

Symmetrically, the discussion of continuity the preceding paragraph, the present invention also can increase to the n channel metal oxide semiconductor transistor in the first phase inverter its source electrode supply voltage (making its source electrode suspension joint), can reduce equally its grid and voltage between source electrodes poor, reduce its conducting degree, so that logical one is write to a back end of stored logic 0 originally via a bit line; Simultaneously, to the n channel metal oxide semiconductor transistor in the second phase inverter, its source electrode supply voltage remains unchanged, and its conducting degree is unaffected, can rapidly the voltage of its corresponding data node be pulled low to the low-voltage of logical zero.

Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of instructions, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by embodiment, and the cooperation accompanying drawing, be described in detail as follows.

The accompanying drawing explanation

Fig. 1 illustrates the random access memory of one embodiment of the invention.

Fig. 2 illustrates the operation situation of random access memory shown in Fig. 1.

Fig. 3 illustrates the random access memory of another embodiment of the present invention.

Fig. 4 illustrates the operation situation of random access memory shown in Fig. 3.

Fig. 5 illustrates the random access memory of further embodiment of this invention.

Fig. 6 illustrates the operation situation of random access memory shown in Fig. 5.

Fig. 7 illustrates the random access memory of yet another embodiment of the invention.

Fig. 8 illustrates the operation situation of random access memory shown in Fig. 7.

Fig. 9 illustrates the random access memory of another embodiment of the present invention.

Figure 10 illustrates the operation situation of random access memory shown in Fig. 9.

Figure 11 illustrates the random access memory of further embodiment of this invention.

Figure 12 illustrates the operation situation of random access memory shown in Figure 11.

Figure 13 illustrates the random access memory of yet another embodiment of the invention.

Figure 14 illustrates the operation situation of random access memory shown in Figure 13.

Figure 15 illustrates the random access memory of another embodiment of the present invention.

Figure 16 illustrates the operation situation of random access memory shown in Figure 15.

Description of reference numerals in above-mentioned accompanying drawing is as follows:

The 101-108 random access memory

U (m, n)-U (m ', n '), Uf (m, n)-Uf (m ', n), Ue (m, n)-Ue (m ', n) storage unit

21a-25a, 21b-25b, 25c-25d, 26,26c, 27a-27c, 28a-28b power switch

31a-35a, 31b-35b, 35c-35d, 36,36c, 37a-37c, 38a-38b electric power retainer

PC1 (n)-PC8 (n), PC1 (n '), PC5N (n)-PC7N (n) power circuit

BL (n), BLB (n), BL (n '), BLB (n '), BL1 (n)-BL2 (n), BLB1 (n)-BLB2 (n) bit line

WL (m), WL (m '), WL1 (m)-WL2 (m), WL1 (m ')-WL2 (m ') character line

WEB, WE write control signal

VDD, VSS operating voltage

VVDD1, VVDD2, VVSS1, VVSS2 voltage

M1-M8, N1-N2, P1-P2, T1-T4, NM1-NM4 transistor

The NR1-NR2 rejection gate

The ND1-ND2 Sheffer stroke gate

Iv1-iv2, IVa-IVd phase inverter

I3-I4, I7-I8 electric current

Nb1-nb4, ns1-ns4, np1-np2, Q, QB, nn1-nn2 node

Embodiment

Please refer to Fig. 1, that it is illustrated is an embodiment of random access memory of the present invention.In the present embodiment, random access memory 101 can be a static RAM, has a plurality of storage unit, in Fig. 1 with storage unit U (m, n), U (m, n '), U (m ', n) with U (m ', n ') as representative; Each storage unit can be six transistorized static storage cells.These memory cell arrangements are array, and for instance, storage unit U (m, n) and U (m, n ') are arranged in same a line, corresponding to same character line W (m); Storage unit U (m ', n) with U (m ', n '), be arranged in another row, corresponding to character line W (m ').Moreover, storage unit U (m, n) and U (m ', n) be arranged in same row, corresponding to pair of bit lines BL (n) and BLB (n); Storage unit U (m, n ') and U (m ', n ') belong to same row, corresponding another pairs of bit line BL (n ') and BLB (n ').

In random access memory 101, each storage unit U (m, n) is identical to the framework of U (m ', n '); With storage unit U (m, n) be example, it has two, and mutually transistor N1 and N2(of coupling can be the n channel metal oxide semiconductor transistor), two transistor P1 and the P2(of coupling can be the p channel metal oxide semiconductor transistor mutually) can be the n channel metal oxide semiconductor transistor with two transistor Ts that mutually mate 1 and T2().Transistor P1 and N1 form a phase inverter iv1, and input end couples the source electrode that node QB, output terminal couple node Q, transistor P1 and couples node ns1, and the source electrode of transistor N1 couples operating voltage VSS(as a ground terminal voltage).Symmetrically, transistor P2 and N2 form a phase inverter iv2, and input end couples the source electrode that node Q, output terminal couple node QB, transistor P2 and couples node ns2, and the source electrode of transistor N2 couples operating voltage VSS.Transistor T 1 is with T2 as the gateway transistor, and both grids are controlled by character line WL (m); Transistor T 1 is coupled between node nb1 and Q, and 2 of transistor Ts are coupled between node nb2 and QB.Node ns1 and ns2 can be considered two power ends of storage unit U (m, n), and node Q and QB are two back end, and node nb1 and nb2 can be considered two ends.

In order to realize technology of the present invention, also be provided with a plurality of power circuits in random access memory 101, each power circuit is corresponding to the storage unit of row; In Fig. 1, power circuit PC1 (n) corresponding to storage unit U (m, n) and U (m ', the row under n), power circuit PC1 (n ') is another row under corresponding stored unit U (m, n ') and U (m ', n ').The identical and coupling of the circuit framework of each power circuit PC1 (n) and PC1 (n '), below take power circuit PC1 (n) and illustrate as example.

In the embodiment in figure 1, be provided with two

power switch

21a and 21b in power circuit PC1 of the present invention (n), and two electric power maintainer 31a and 31b.Wherein, node np1 and np2 can be considered the feeder ear of power circuit PC1 (n), node np1 be coupled to each storage unit U (m, n) and U (m ', node ns1 n), be the supply of the phase inverter iv1 in storage unit voltage VVDD1.Symmetrically, node np2 be coupled to each storage unit U (m, n) and U (m ', node ns2 n), be the supply of the phase inverter iv2 in storage unit voltage VVDD2.The transistor M1 and the M2(that are respectively equipped with mutual coupling in

power switch

21a and 21b can be the p channel metal oxide semiconductor transistor) and two rejection gate NR1 and the NR2 that mutually mate.The source electrode of transistor M1 couples operating voltage VDD, and drain electrode couples node np1, and rejection gate NR1 is coupled between bit line BL (n) and transistor M1; Rejection gate NR1 does anti-or logical operation for voltage and the write control signal WEB of bit line BL (n), its output terminal couples the grid of transistor M1, and it can be the voltage higher than operating voltage VSS to operating voltage VDD(to make transistor M1 be able to determine whether to put the np1 conducting according to anti-or logic operation result).Symmetrically, rejection gate NR2 does anti-or logical operation for voltage and the write control signal WEB of bit line BLB (n), makes transistor M2 determine whether will put the np2 conducting to operating voltage VDD according to anti-or logic operation result.

Electric power maintainer

31a and 31b are provided with two, and transistor M3 and the M4(of coupling can be the p-type metal oxide semiconductor transistors mutually), its grid couples operating voltage VSS, and source electrode couples operating voltage VDD, and drain electrode couples respectively node np1 and np2.In preferred embodiment of the present invention, it is stronger than transistor M3 and M4 that transistor M1 and M2 can design; In other words, with transistor M1(M2) compare transistor M3(M4) raceway groove long or narrower, driving force is poor, source electrode is larger with the conducting resistance between draining.

The embodiment of continuity Fig. 1, please refer to Fig. 2, and it is to take the coherent signal of power circuit PC1 (n) and state to illustrate the operation situation of random access memory 101 of the present invention as example.Random access memory 101 can alternately operate on read mode (being denoted as " read " in Fig. 2), standby mode (" standby ") and write mode (" write ").When random access memory 101 operates on standby mode, character line WL (m) (with WL (m ')) is logical zero, any storage unit of not access; Bit line BL (n) and BLB (n) can be maintained at the high voltage (being for example operating voltage VDD) of logical one, and write control signal WEB is controlled as logical one.Via the logical operation of rejection gate NR1 and NR2, transistor M1 and M2 are switched on (being denoted as " on " in Fig. 2), and node np1 and np2 are distinguished to conducting to operating voltage VDD, make voltage VVDD1 and VVDD2 all equal operating voltage VDD.In this case, each storage unit U (m, n) and U (m ', the phase inverter iv1 in n) and iv2 all normal operation with latch data.

Random access memory 101 can operate on read mode with the data reading by storage unit U (m, n).Under this pattern, write control signal WEB still equals operating voltage VDD for logical one makes voltage VVDD1 and VVDD2, bit line BL (n) and BLB (n) can first be precharged to the high voltage of logical one, then character line WL (m) can carry out conducting storage unit U (m with logical one, n) transistor T 1 and T2 in, the voltage that makes bit line BL (n) and the voltage of BLB (n) can follow node Q and QB, so represent random (don't care) in logic with mark " x " in Fig. 2.For instance, suppose node Q and QB difference stored logic 1 and the logical zero of storage unit U (m, n); When reading, open while at first making transistor T 2 start conducting, the transistor N2 tendency of conducting is maintained at operating voltage VSS by node QB, and 2 tendencies of transistor T are pulled up to the voltage of node QB the logical one high voltage of node nb2; Between the source drain of transistor T 2 between the source drain of conducting resistance and transistor N2 conducting resistance can take node QB as the dividing point dividing potential drop.When circuit design, for the voltage that prevents node QB is drawn high mistakenly by transistor T 2, transistor T 2(and T1) can be designed to weak transistor.

Random access memory 101 also can operate on write mode and the data of are write to storage unit U (m, n).Take and write logical one and illustrate as example (being denoted as " write " 1 " " in Fig. 2); Will in storage unit U (m, n), write logical one, will make exactly the high voltage that node Q is logical one, and to make anti-phase node QB be the logical zero low-voltage.Therefore writing Qi Shishi, bit line BL (n) is logical one, and bit line BLB (n) is logical zero, character line WL (m) be logical one with turn-on transistor T1 and T2, write control signal WEB is logical zero.What suppose that node Q stores originally is the logical zero of low-voltage, and node QB can store anti-phase logical one.When writing Qi Shishi, the transistor P2 of conducting can be inclined to node QB is maintained to logical one, the transistor N1 of conducting can be inclined to node Q is maintained to logical zero, and these two transistor N1 and P2 can strengthen the tendency that it maintains voltage mutually via the breech lock framework: when transistor P2 is maintained at high voltage by node OB, also guarantee the conducting of transistor N1; Symmetrically, when transistor N1 is maintained at low-voltage by node Q, also guarantee the conducting of transistor P2.For realizing that the purpose write makes the voltage upset of node Q and QB, transistor T 1 should be drawn high the voltage of node Q, 2 voltages that should drag down node QB of transistor T.But, with transistor N1, with N2, compare, due to transistor T 1 and T2 a little less than, more difficult node Q and the QB change voltage of effectively ordering about.

But, under the running of power circuit PC1 of the present invention (n), when writing Qi Shishi, the logical zero of bit line BLB (n) and the logical zero of write control signal WEB can the transistor M2 in power switch 21b be closed via rejection gate NR2 (in Fig. 2 with " off " representative), only with transistor M4 regulation and control, maintain the voltage VVDD2 of node np2.With respect to transistor M2, because transistor M4 is designed to weak transistor, therefore even transistor M4 conducting, the voltage VVDD2 of node np2 also no longer is maintained at operating voltage VDD and can reduces.Thus, transistor P2 also diminishes at the source voltage of node ns2, and the conducting degree of transistor P2 is died down, thereby makes transistor T 2 easily node QB is pulled low to the low-voltage of logical zero.Moreover, due to the lower voltage of node QB, the transistor N1 also more difficult voltage by node Q is maintained at low-voltage, bit line BL (n) can be promoted the voltage of node Q more quickly.

On the other hand, when writing Qi Shishi, the logical one of bit line BL (n) and the logical zero of write control signal WEB can make the transistor M1 in power switch 21a maintain conducting via rejection gate NR1, therefore voltage VVDD1 maintains operating voltage VDD normal power supply to the transistor P1 in phase inverter iv1.That is to say, when the voltage of node QB starts to descend, transistor P1 can normally start conducting, with the voltage by node Q, draws high to operating voltage VDD; Via the breech lock framework, the voltage that accelerates node Q rises and also can make transistor N2 conducting quickly, further helps the voltage of node QB is pulled low to operating voltage VSS.

In other words, under the running of power circuit PC1 of the present invention (n), if will write logical zero at node QB, the corresponding power switch 21b of transistor P2 can close not conducting, make node np2 be similar to suspension joint, reduce the source electrode supply voltage (namely voltage VVDD2) of transistor P2; At anti-phase node Q, (voltage VVDD1) is unaffected for the source electrode supply voltage of transistor P1, still is equivalent to operating voltage VDD.More than can effectively accelerate speed and the efficiency that data write, and improve static noise nargin (Static Noise Margin).Symmetrically, when will be at storage unit U (m, n) write logical zero in, namely to write logical one and when node Q writes logical zero at node QB, the corresponding power switch 21a of transistor P1 can close, and node np1 can be similar to suspension joint and make the source electrode supply voltage VVDD1 of transistor P1 be less than operating voltage VDD; The source electrode supply voltage VVDD2 of transistor P2 is unaffected.That is to say, power switch 21a of the present invention and 21b are that both independently operate, and control respectively the source electrode supply voltage of phase inverter iv1 and phase inverter iv2 in each storage unit of same row; According to the data writing (being respectively logical zero/logical one or logical one/logical zero) on bit line BL (n)/BLB (n), two phase inverter iv1 and iv2 only have the source electrode supply voltage of one of them to reduce, another source electrode supply voltage remains unchanged, with the ability that retains its driving voltage and the feedback mechanism of latch circuit.

In a kind of prior art, when carrying out data, write fashionablely, can unify two phase inverters in storage unit are reduced to supply voltage in the lump.For example, when will, when node QB writes logical zero, making in the lump the source electrode supply voltage of transistor P1 and P2 reduce.Although this conducting degree that can reduce transistor P2 maintains the ability of voltage to reduce transistor P2 at node QB, but also can injure the ducting capacity of transistor P1, make transistor P1 can not be normally with the lower voltage of node OB, increase the conducting degree, affecting transistor P1 draws high, the demand that meeting of the present invention writes according to data is dynamically adjusted, only in two phase inverters, reduce the power supply of one of them, effectively to promote the write performance of random access memory of the present invention.In addition, because the supply voltage that changes a phase inverter is only switched in the present invention, therefore the present invention also can be lower in the power consumption of switching supply voltage, the speed that completes switching also can be than comparatively fast.

In random access memory 101 of the present invention, as power switch 21a(21b) while closing, node np1(np2) voltage VVDD1(VVDD2) can be relevant with the leakage current of same each storage unit of row.For example, when will when the node QB of storage unit U (m, n) writes logical zero, the transistor M2 in power switch 21b closes not conducting via bit line BLB (n), make node np2 present the state of approximate suspension joint.Due to node np2 can with an electric power coiling be coupled to same row each storage unit U (m, n) and even U (m ', n), the equivalent capacity of this electric power coiling can maintain with electric charge the voltage of node np2; Each storage unit U (m, n) and even U (m ', each transistor P2 in n) thus the electric power coiling draw leakage current (no matter the transistor P2 in each storage unit whether conducting), the voltage VVDD2 of node np2 is reduced because of electric discharge.Properly design the parameter of transistor M4, suitable electric current I 4 compensates the leakage current of same each storage unit of row can to make transistor M4 conducting one, the voltage VVDD2 of node np2 can stably be maintained at lower than operating voltage VDD but degree that can be not too low, to safeguard stored data in each storage unit of same row.Symmetrically, when the transistor M1 in power switch 21a stops conducting, transistor M3 also can provide electric current I 3 to compensate the leakage current of same each storage unit of row.

Please refer to Fig. 3 and Fig. 4; Fig. 3 signal be another embodiment of random access memory of the present invention, Fig. 4 signal be the situation that the random access memory of the present embodiment operates on various patterns.Be similar to random access memory 101(Fig. 1), the random access memory 102 of the present embodiment is also that each storage unit of n row (arranges the power circuit PC2 (n) of a correspondence with U (m, n) and U (m ', n) representative).Two feeder ears that node np1 and np2 are power circuit PC2 (n), be coupled to node ns1 and the ns2 in each storage unit of same row with electric power coiling respectively, usings voltage VVDD1 and the VVDD2 source electrode supply voltage as transistor P1 and P2 is provided.Also be provided with two power switch 22a and 22b in power circuit PC2 (n), and two electric power maintainer 32a and 32b.Electric power maintainer 32a and 32b can be respectively the p channel metal oxide semiconductor transistor of two couplings with transistor M3 and M4() to realize, the grid of transistor M3 and source electrode couple respectively operating voltage VSS and VDD, and drain electrode couples node np1; Symmetrically, the drain electrode of transistor M4 couples node np2.Power switch 32a is provided with a transistor M1 and a phase inverter Iva; Phase inverter IVa is anti-phase to control the grid of transistor M1 by the data of bit line BL (n) (voltage).Transistor M1 is as a power transistor (being for example a p channel metal oxide semiconductor transistor), and its source electrode couples respectively operating voltage VDD and node np1 with drain electrode.Symmetrically, power switch 32b is provided with the transistor that a transistor M2(can be one and transistor M1 coupling) with a phase inverter IVb, whether transistor M2 can be determined according to the reverse voltage of bit line BLB (n) between its source drain operating voltage VDD conducting to node np2.

The principle of work of power circuit PC2 (n) is similar to the power circuit PC1 (n) in Fig. 1, can be that the phase inverter iv1 of same array storage unit and iv2 supply respectively two independently voltage VVDD1 and VVDD2 mutually according to the data voltage of bit line BL (n) and BLB (n), the source electrode supply voltage of usining as transistor P1 and P2.But, random access memory 102 has been cancelled the write control signal WEB in Fig. 1, therefore the on-off circuit 22a of power circuit PC2 (n) can only regulate and control voltage VVDD1 according to bit line BL (n), on-off circuit 22b can only regulate and control voltage VVDD2 according to bit line BLB (n).As shown in Figure 4, when writing fashionablely carrying out data, the operation situation of power circuit PC2 (n) can be analogized by the operation situation of power circuit PC1 (n), therefore power circuit PC2 (n) also follows the advantage of power circuit PC1 (n).For example, in the time will in data cell U (m, n), writing the position of logical one, bit line BLB (n) can be pulled low to the low-voltage of logical zero, via the running of phase inverter IVb, and even the conducting degree of transistor M2 reduces closes fully, makes node np2 be similar to suspension joint; Same array storage unit U (m, n) and even other storage unit U be not accessed (m ', n) can draw leakage current and voltage VVDD2 is dragged down via the electric power coiling of node np2, electric power maintainer M4 provides electric current I 4 suitably to compensate the leakage current of same array storage unit, and voltage VVDD2 is maintained to an appropriate voltage lower than operating voltage VDD.This voltage VVDD2 can reduce the conducting degree of transistor N1 and P2 in storage unit U (m, n), and the data of improving storage unit U (m, n) write, but can not affect other storage unit U (m ', the data in n).The transistor M1 of conducting in power switch 22a is maintained at operating voltage VDD by voltage VVDD1, assists transistor P1 and N2 in storage unit U (m, n) inerrably to complete and write fast.

On the other hand, when random access memory 102 will be in storage unit U (m, n) during reading out data, if storage unit U is (m, n) position stored in be logical one (in Fig. 4, be denoted as " read " 1 " "), node Q and QB can distinguish stored logic 1 and logical zero; Reading while carrying out, the voltage of bit line BLB (n) can be dragged down, and the transistor M2 in power switch 22b can reduce the conducting degree accordingly, loosens the control to voltage VVDD2; Now, and same array storage unit U (m, n) and even the storage unit U that is not accessed (m ', n) all can draw leakage current by the electric power coiling of node np2, voltage VVDD2 is reduced.But, with the running that writes logical one, compare, when reading logical one, the degree that the voltage of bit line BLB (n) is dragged down is less, and speed is slower, therefore on the less that affects of the storage unit of same row.In other words, via suitable circuit design, as long as the transistor M4 of electric power maintainer 32b can maintain suitable voltage VVDD2 when writing logical one, the running that just can guarantee to read logical one is errorless, can not affect the data that store in each storage unit of same row.Symmetrically, if transistor M3 can maintain suitable voltage VVDD1 when writing logical zero, the running of reading logical zero also can be correct.In addition, via suitable circuit design, if the sensing amplifier used while reading (not icon) detects the standard of logical zero, higher than phase inverter IVa and IVb, changed its output the standard of logical one into by logical zero, also can guarantee to read the correctness of running.For example, when reading logical one, when the voltage drop of bit line BLB (n) during to (VDD-dV), wherein dV is difference voltage, now sensing amplifier can be logical zero by the data identification on bit line BLB (n), but phase inverter IVb will bit line BLB (n) regards as logical one and, still to transistor M2 output logic 0, transistor M2 just can not reduce the conducting degree.

Please refer to Fig. 5 and Fig. 6; That Fig. 5 illustrates is another embodiment of random access memory of the present invention, the operation situation of the random access memory shown in Fig. 5 under various patterns of Fig. 6 signal.In the present embodiment, be provided with each storage unit that power circuit PC3 (n) thinks n row in random access memory 103 (as storage unit U (m, n) and U (m ', n)) provide respectively voltage VVDD1 and VVDD2.Be similar to power switch 21a and the 21b of Fig. 1 power circuit PC1 (n), in power circuit PC3 (n), also be provided with power switch 23a and 23b, but omitted the electric power maintainer.Under the control of write control signal WEB, power switch 23a and 23b can supply two independent voltage VVDD1 and VVDD2 being write phase inverter iv1 and the iv2 that the fashionable voltage according to bit line BL (n) and BLB (n) is respectively same each storage unit of row.For example, when will be at data cell U (m, n) data writing 1, because write control signal WEB and bit line BLB (n) are logical zero, the not conducting of transistor M2 in power switch 23b, make node np2 be similar to suspension joint, voltage VVDD2 also will reduce, and with improvement, writes running.Under suitable circuit design, as long as node np2 can be when not conducting of transistor M2 with the electric charge of the equivalent capacity/stray capacitance leakage current of same each storage unit of row that suitably contends with, just can guarantee to write the normally errorless of running, also can not affect the storage unit be not accessed in same row.

Please refer to Fig. 7 and Fig. 8; That Fig. 7 illustrates is the another embodiment of random access memory of the present invention, and what Fig. 8 illustrated is the situation that in Fig. 7, random access memory operates on various patterns.In the present embodiment, random access memory 104 is also the power circuit PC4 (n) that n the storage unit be listed as arranges a correspondence.Be provided with power switch 24a, 24b and

electric power maintainer

34a and 34b in power circuit PC4 (n).Power switch 24a and 24b realize with transistor NM1 and NM2 respectively; Transistor NM1 and NM2 can be two n channel metal oxide semiconductor transistors of coupling mutually.The drain electrode of transistor NM1, grid and source electrode couple respectively operating voltage VDD, bit line BL (n) and node np1; Symmetrically, the drain electrode of transistor NM2, grid and source electrode couple respectively operating voltage VDD, bit line BLB (n) and node np2.

Electric power maintainer

34a and 34b are realized by transistor NM3 and NM4 respectively; These two transistors can be the n channel metal oxide semiconductor transistors mutually mated, and two transistor is separately diode and connects, and drain electrode is coupled to operating voltage VDD jointly with grid, and source electrode couples respectively node np1 and np2.

According to the data voltage of bit line BL (n), whether power switch 24a can determine operating voltage VDD conducting to node np1; For example, as shown in Figure 8, when random access memory 104 will be at storage unit U (m, n) write logical zero in and make bit line BL (n) when the logical zero, not conducting of transistor NM1 in power switch 24a, make node np1 be similar to suspension joint, and node np1 will reduce for the source electrode supply voltage VVDD1 that each storage unit provides, the usefulness write to promote data.No matter read or write, transistor NM3 in electric power maintainer 34a can afford redress electric current I 3 suitably to maintain voltage VVDD1 when transistor not conducting of NM1 or conducting degree are low, make voltage VVDD1 lower than operating voltage VDD, but be unlikely to too low, to guarantee in same row, in each storage unit except the storage unit that to be ready being written into data, stored data can be not influenced.Symmetrically, power switch 24b and electric power maintainer 34b can regulate and control according to the data of bit line BLB (n) the voltage VVDD2 of node np2.

Please refer to Fig. 9 and Figure 10; That Fig. 9 illustrates is the another embodiment of random access memory of the present invention, and what Figure 10 illustrated is the situation that the random access memory shown in Fig. 9 operates on various patterns.In aforementioned each embodiment, the power circuit of random access memory 101 to 104 of the present invention is to provide source electrode supply voltage VVDD1 and VVDD2 for the transistor P1 in each storage unit of same row and P2, and dynamically adjusts respectively voltage VVDD1 and VVDD2 according to the data voltage of character line.In the embodiment shown in Fig. 9 and Figure 10, random access memory 105 not only be take power circuit PC5 (n) and is that each storage unit of n row is (as storage unit U (m, n) with U (m ', n)) provide voltage VVDD1 and VVDD2, transistor N1 and the N2 of the power circuit PC5N (n) set up in each storage unit of same row of also separately take provides respectively voltage VVSS1 and VVSS2.

In random access memory 105, the circuit framework of power circuit PC5 (n) and the power circuit PC1 (n) that configures similar Fig. 1.At storage unit U (m, n) (with U (m ', n)) in, the transistor P1 of phase inverter iv1 and iv2 and P2 are coupled respectively node np1 and the np2 of power circuit PC5 (n) by node ns1 and ns2, and the source electrode supply voltage that the voltage VVDD1 that power circuit PC5 (n) provides at node np1 and np2 and VVDD2 just become transistor P1 and P2.Power circuit PC5 (n) is provided with power switch 25a, 25b and electric power maintainer 35a, 35b.Whether power switch 25a determines node np1 conducting to operating voltage VDD according to the voltage of write control signal WEB and bit line BL (n); Symmetrically, whether power switch 25b determines node np2 conducting to operating voltage VDD according to the voltage of write control signal WEB and bit line BLB (n).When power switch 25a makes the approximate suspension joint of node np1, electric power maintainer 25a can assist to make voltage VVDD1 lower than voltage VDD but be unlikely to too low; In like manner, electric power maintainer 25b can assist to maintain suitable voltage VVDD2 when the approximate suspension joint of node np2.

On the other hand, two node nn1 and the nn2 of power circuit PC5N (n) can be considered two feeder ears, supply respectively voltage VVSS1 and VVSS2; At storage unit U (m, n) (and even U (m ', n)) in two phase inverter iv1 and iv2, the source electrode of transistor N1 and N2 couples node nn1 and nn2 by node ns3 and ns4 respectively, usings voltage VVSS1 and the VVSS2 source electrode supply voltage as transistor N1 and N2.Be provided with power switch 25c, 25d and electric power maintainer 35c, 35d in power circuit PC5N (n).Be provided with transistor M5 and a Sheffer stroke gate ND1 in power switch 25c; Symmetrically, transistor M6 and Sheffer stroke gate ND2 are set in power switch 25d.Transistor M5 and M6 can be the n channel metal oxide semiconductor transistors of two couplings, and source electrode is coupled to operating voltage VSS.Sheffer stroke gate ND1 does anti-and logical operation by the data voltage of bit line BL (n) and another write control signal WE, and controls accordingly the grid of transistor M5.According to the output of Sheffer stroke gate ND1, whether transistor M5 can determine between its drain electrode and source electrode node nn1 conducting to operating voltage VSS.Symmetrically, Sheffer stroke gate ND2 does anti-and computing for bit line BLB (n) and write control signal WE, makes transistor M6 can control according to this conducting between node nn2 and operating voltage VSS.Electric power maintainer 35c and 35d realize with transistor M7 and M8 respectively, these two transistors can be the n channel metal oxide semiconductor transistors mutually mated, grid and source electrode couple respectively operating voltage VDD and VSS, and drain electrode couples respectively node nn1 and nn2.When transistor M5 closes not conducting, node nn1 is similar to suspension joint, and the leakage current that each storage unit of same row is injected node nn1 can make voltage VVSS1 higher than operating voltage VSS, and transistor M7 can draw suitable electric current I 7, so that voltage VVSS1 is higher than operating voltage VSS, but can be not too high.Symmetrically, during not conducting of transistor M6 in power switch 25d, the transistor M8 in electric power maintainer 35d can On current I8 to assist maintain suitable voltage VVSS2.

Power circuit PC5 (n) can be described as follows with the situation of PC5N (n) Collaboration.Write control signal WEB and WE be inversion signal each other, when random access memory 105 operates on, reads or during standby mode, write control signal WE can anergy be logical zero, and write control signal WEB is logical one.In power circuit PC5 (n), the write control signal WEB of logical one can make transistor M1 and M2 conducting, makes voltage VVDD1 and VVDD2 all be maintained at operating voltage VDD, and normal power supply is given transistor P1 and the P2 in each storage unit of same row.In like manner, logical zero write control signal WE can make transistor M5 and the M6 conducting in power circuit PC5N (n), make voltage VVSS1 and VVSS2 all be maintained at operating voltage VSS, normally for the transistor N1 in each storage unit of same row and N2, provide the source electrode supply voltage.

When random access memory 105 will be write fashionable, write control signal WE activation is logical one, write control signal WEB is anti-phase logical zero, impels power circuit PC5 (n) and PC5N (n) to regulate and control respectively voltage VVDD1, VVDD2, VVSS1 and VVSS2 according to bit line BL (n) and BLB (n).For example, when will be at storage unit U (m, while n), writing logical one, bit line BLB (n) is logical zero, transistor M2 in power circuit PC5 (n) stops conducting, makes node np2 be similar to suspension joint, reduces voltage VVDD2, the logical one of bit line BL (n) makes transistor M1 maintain conducting, and voltage VVDD1 is maintained to normal operating voltage VDD.On the other hand, the bit line BL (n) of logical one and logical one write control signal WE close the transistor M5 in power switch 25c via Sheffer stroke gate ND1, and node nn1 is similar to suspension joint, voltage VVSS1 is upwards drifted about and surpass operating voltage VSS; Transistor M7 makes voltage VVSS1 be unlikely to too high, allows in same row other storage unit of not being accessed (as storage unit U (m ', n)) correct storage data still.Logical zero bit line BLB (n) makes the transistor M6 normally in power switch 25d, and voltage VVSS2 is maintained to normal operating voltage VSS.

Suppose storage unit U (m, n) stored logic 0(node Q is logical zero originally, node QB is logical one), when random access memory 105 will write logical one in storage unit U (m, n), just as leading portion described, voltage VVDD2 can reduce, and reduces the conducting degree of transistor P2 in storage unit U (m, n), also make the voltage of node QB reduce via 2 electric discharges of gateway transistor T, it be logical zero that node QB can by logical one, be overturn quickly.In addition, voltage VVSS1 raises, and reduces the conducting degree of transistor N1, also makes the voltage of node Q raise, and it be logical one that node Q can more promptly via transistor P1 charging, by logical zero, be overturn.At the same time, voltage VVDD1 can normally be maintained at operating voltage VDD, assist transistor P1 normally and node Q is increased to the high voltage of logical one, in like manner, voltage VVSS2 can normally be maintained at operating voltage VSS, makes the transistor N1 can normally and node QB is pulled low to the low-voltage of logical zero.That is to say, via power circuit PC5 of the present invention (n) and the respectively regulation and control of PC5N (n) to voltage VVDD1, VVDD2, VVSS1 and VVSS2, random access memory 105 of the present invention can effectively promote the usefulness that data write.

In random access memory 105, power circuit PC5 (n) and PC5N (n) can be considered as respectively head (header) power circuit and pin (footer) power circuit.Power circuit PC5N (n) in Fig. 9 is only a kind of embodiment of the present invention; The embodiment of other kind can be analogized with PC4 (n) by power circuit PC2 (n), the PC3 (n) of Fig. 3, Fig. 5 and Fig. 7.In addition, random access memory in Fig. 3, Fig. 5 and Fig. 7 also can be according to the framework of random access memory 105, and transistor N1 and the N2 of circuit in each storage unit of same row that is similar to power circuit PC5N (n) of take regulates and controls respectively the source electrode supply voltage.

Please refer to Figure 11 and Figure 12; That Figure 11 illustrates is a kind of embodiment that random access memory of the present invention is applied to five transistor static storage cells, and what Figure 12 illustrated is the situation of the random access memory running shown in Figure 11.In the present embodiment, random access memory 106 can have a plurality of storage unit that are respectively in a plurality of row, and the storage unit Uf (m, n) in being listed as with n in Figure 11 and Uf (m ', n) as representative.Be similar to aforesaid six transistor static storage cell U (m, n), in storage unit Uf (m, n), with transistor P1 and N1, transistor P2 and N2, form respectively two phase inverter iv1 and iv2, and using node Q and QB as back end.But, in random access memory 106, same row each storage unit Uf (m, n) and Uf (m ', n) only via single bit lines BL (n) access data; Therefore storage unit Uf (m, n) (with Uf (m ', n)) also only has a gateway transistor T 1, its grid couples character line WL (m), whether source drain is coupled between node nb1 and Q, with the voltage according to character line WL (m), determine node Q conducting to bit line BL (n).

Concerning five transistorized storage unit, owing to not having anti-phase bit line that Control of Voltage is provided on node QB, therefore, in writing running, need write logical one (making node Q is logical one, and node QB is logical zero) via bit line BL (n), be comparatively difficult.In order to assist writing of logical one, random access memory 106 of the present invention can arrange for each storage unit of n row power circuit PC6 (n) and PC6N (n).Be provided with a power switch 26 and an electric power maintainer 36 in power circuit PC6 (n), so that a voltage VVDD2 to be provided at node np2; Node np2 can be coupled to each storage unit Uf (m, n) and Uf (m ', node ns2 n), the transistor P2 that voltage VVDD2 be can be in each storage unit of same row provides the source electrode supply voltage.In power switch 26, transistor M2(is for example a p channel metal oxide semiconductor transistor) as a power transistor, source electrode couples respectively operating voltage VDD and node np2 with drain electrode.Whether phase inverter IVc ANDORNOTgate NR2 forms a logical circuit, make transistor M2 be able to determine node np2 conducting to operating voltage VDD according to the data voltage of write control signal WEB and bit line BL (n).Electric power maintainer 36 can be with a transistor M4(as a p channel metal oxide semiconductor transistor) realize, its source electrode, grid and drain electrode couple respectively operating voltage VDD, operating voltage VSS and node np2.Compared to transistor M2, transistor M4 can be weak transistor; When not conducting of transistor M2, node np2 can be similar to suspension joint makes voltage VVDD2 depart from operating voltage VDD, and transistor M4 will provide the electric current I 4 compensation leakage current that same array storage unit is drawn by node np2, make voltage VVDD2 lower than operating voltage VDD, but can be not too low, to safeguard the data in each storage unit of same row.

Based on similar technical spirit, be provided with power switch 26c and electric power maintainer 36c in power circuit PC6N (n), with the voltage VVSS1 of regulation and control node nn1.Node nn1 can be coupled to the node ns3 in each storage unit of same row, and the transistor N1 that makes voltage VVSS1 can be same each storage unit of row provides the source electrode supply voltage.Be provided with a transistor M5(in power switch 26c as a n channel metal oxide semiconductor transistor), and form a logical circuit with Sheffer stroke gate ND1 and phase inverter IVd.The drain electrode of transistor M5 and source electrode couple respectively node nn1 and operating voltage VSS, Sheffer stroke gate ND1 does anti-and logical operation by the data voltage of the inversion signal of write control signal WEB and bit line BL (n), and transistor M5 is according to the output control node nn1 of anti-and logical operation and the conducting between operating voltage VSS.Electric power maintainer 36c can be by a transistor M7(as a n channel metal oxide semiconductor transistor) to realize, its drain electrode, grid and source electrode couple respectively node nn1, operating voltage VDD and VSS.Compared to transistor M5, transistor M7 can be weak transistor.When transistor, M5 stops conducting, node nn1 can be similar to suspension joint, make voltage VVSS1 depart from operating voltage VSS, but transistor M7 On current I7 is charged to the leakage current of node nn1 to draw each storage unit of same row, make voltage VVSS1 higher than operating voltage VSS, but can be not too high, do not affect the data in same array storage unit.

But the running brief introduction of random access memory 106 of the present invention is as follows.When reading or during standby mode, write control signal WEB is that logical one is not write with representative.Logical one write control signal WEB can make transistor M2 and M5 conducting, no matter bit line BL (n) is logical zero or 1.Therefore, power circuit PC6 (n) and PC6N (n) are maintained at respectively operating voltage VDD and VSS by voltage VVDD2 and VVSS1, make each storage unit of same row can obtain normal power supply.

Fashionable when being write, write control signal WEB can change into logical zero, and power circuit PC6 (n) will regulate and control respectively voltage VVDD2 and VVSS1 according to the voltage of bit line BL (n) with PC6N (n).When bit line BL (n) will write logical zero for logical zero in storage unit Uf (m, n), transistor M2 and M5 still can normallies, and voltage VVDD2 and VVSS1 can normally be maintained at operating voltage VDD and VSS.Relatively, when bit line BL (n) is logical one when in storage unit Uf (m, n), writing logical one, transistor M2 and M5 can stop conducting; Therefore, node np2 and nn1 are similar to suspension joint, and voltage VVDD2 reduction, voltage VVSS1 are raise.In storage unit Uf (m, n), the voltage VVDD2 of reduction can weaken the conducting degree of transistor P2, and reduces the voltage of node QB, makes node QB more easily via transistor N2 electric discharge, transfer logical zero to; The voltage VVSS1 raise weakens the conducting degree of transistor N1, and improves the voltage of node Q, makes node Q more easily via transistor P1 charging, transfer logical one writing with completion logic 1 to.

The embodiment of continuity Figure 11, please refer to Figure 13 and Figure 14.That Figure 13 illustrates is the another embodiment of random access memory of the present invention, and Figure 14 illustrates the operation situation of the random access memory in Figure 13.Be similar to the random access memory 106 in Figure 11, in the present embodiment, random access memory 107 also adopts five transistorized static storage cells, and is power circuit PC7 (n) and PC7N (n) that the n row arrange a correspondence.But, the power circuit PC6 (n) of random access memory 106 is main in order to improve writing of logical one, therefore one group of power switch and electric power maintainer only are set in power circuit PC6 (n) with PC6N (n).For intactly making writing all of logical zero and logical one be improved, the power circuit PC7 (n) of random access memory 107 is provided with two groups of power switches and electric power maintainer.As shown in figure 13, be provided with power switch 27a, 27b and electric power maintainer 37a, 37b in power circuit PC7 (n).The basic framework of power switch 27b and electric power maintainer 37b is identical with power switch 26, the electric power maintainer 36 of function and Figure 11.Power switch 27a, electric power maintainer 37a are at node np1 regulation and control voltage VVDD1; This voltage VVDD1 can provide the source electrode supply voltage for transistor P1 at the node ns1 of same array storage unit.

Be provided with a transistor M1 and a rejection gate NR1 in power switch 27a, transistor M1 and transistor M2 coupling; Rejection gate NR1 does anti-or logical operation to the data on write control signal WEB and bit line BL (n), and whether transistor M1 can be determined according to the result of anti-or logical operation node np1 conducting to operating voltage VDD.The transistor M4 of transistor M3 in electric power maintainer 37a and electric power maintainer 37b mates mutually; When not conducting of transistor M1, transistor M3 provides electric current I 3 to maintain suitable voltage VVDD1.

The situation that random access memory 107 is write running can be described below.In the time will in storage unit Uf (m, n), writing logical one, logical zero write control signal WEB and logical one bit line BL (n) make transistor M1 conducting, transistor M2 and not conducting of M5.Therefore, voltage VVDD2 reduces, voltage VVSS1 raises, and voltage VVDD1 normally is maintained operating voltage VDD.Therefore, in storage unit Uf (m, n), the conducting degree of transistor P2, N1 weakens, and the ducting capacity of transistor P1 is unaffected, can be normally by node Q conducting to logical one.

Relatively, when at storage unit Uf (m, while n), writing logical zero, the logical zero of bit line BL (n) makes transistor M2 and M5 conducting, and transistor M1 closes and makes node np1 be similar to suspension joint, and voltage VVDD1 descends, with at storage unit Uf (m, n) weaken the conducting degree of transistor P1 in, accelerate to reduce via 1 electric discharge of gateway transistor T the voltage of node Q, make writing of logical zero can carry out ground more smooth.So, random access memory 107 just can be improved writing of logical one and writing of logical zero comparatively all sidedly.

Please refer to Figure 15 and Figure 16; Figure 15 is a kind of embodiment that random access memory of the present invention is applied to dual-port eight transistor static storage cells, and Figure 16 illustrates the operation situation of the random access memory in Figure 15.In the present embodiment, be provided with a plurality of storage unit that are arranged in a plurality of row in random access memory 108, in Figure 15 with storage unit Ue (m, n) and the Ue of n row (m ', n) as representative.Take storage unit Ue (m, n) as example, and it is to be the dual-port static storage unit, wherein, transistor P1 and N1 form phase inverter iv1, transistor P2 and N2 forms another phase inverter iv2, and this two phase inverters iv1 and iv2 form the breech lock framework, at node Q and QB, to store the data of.The node nb1 of storage unit Ue (m, n) and nb2 can be considered two differential position ends of same port, couple respectively bit line BL1 (n) and anti-phase bit line BLB1 (n); Transistor T 1 and T2 this to the gateway transistor according to the voltage of character line WL1 (m) control respectively node Q and QB whether can conducting to bit line BL1 (n) and BLB1 (n).In like manner, the two differential position ends that node nb3 and nb4 are another port, couple respectively bit line BL2 (n) and BLB2 (n), gateway transistor T 3 is controlled respectively bit line BL2 (n) and the access of BLB2 (n) to node Q and QB with T4 according to another character line WL2 (m).Utilize eight transistorized storage unit, random access memory 108 can realize out the static RAM of an even port (dual port).

For promoting writing usefulness, improving the characteristic write running of eight transistor static storage cells, can corresponding power circuit be set for each array storage unit in random access memory 108, power circuit PC8 (n) in Figure 15 is corresponding to n each storage unit Ue (m be listed as, n) with Ue (m ', n).Be provided with power switch 28a, 28b and electric power maintainer 38a, 38b in power circuit PC8 (n), with voltage VVDD1 and the VVDD2 of regulation and control node np1 and np2.Node np1 and np2 are coupled to respectively node ns1 and the ns2 in each storage unit of same row, make voltage VVDD1 and VVDD2 can be respectively as the source electrode supply voltage of transistor P1 and P2.Be provided with transistor M1 and Sheffer stroke gate ND1 in power switch 28a; Transistor M1(is as a p channel metal oxide semiconductor transistor) source electrode couple respectively operating voltage VDD and node np1 with drain electrode, Sheffer stroke gate ND1 does anti-and logical operation by bit line BL1 (n) with the data voltage of BL2 (n), and transistor M1 controls the conducting between node np1 and operating voltage VDD according to anti-and logic operation result.Electric power maintainer 38a can be by transistor M3(as a p channel metal oxide semiconductor transistor) realize; Compared to transistor M1, transistor M3 is the weak transistor of a ducting capacity.When transistor, M1 stops conducting, and node np1 is similar to suspension joint and makes voltage VVDD1 decline depart from operating voltage VDD; 3 of the electric current I of transistor M3 conducting can be assisted the voltage VVDD1 that remains suitable.Symmetrically, being provided with transistor M2(in power switch 28b can mate with transistor M1) and Sheffer stroke gate ND2, the conducting between node np2 and operating voltage VDD controlled with the anti-and logic operation result according to bit line BLB1 (n) and BLB2 (n).Transistor M4 in electric power maintainer 38b can mate with transistor M3; When transistor M2 closes and while making the approximate suspension joint of node np2, the electric current I 4 of transistor M4 conducting can be assisted the voltage VVDD2 that remains suitable.

The operation situation of random access memory 108 can be summarized as follows.When random access memory 108 operates on standby mode, each bit line BL1 (n), BL2 (n), BLB1 (n) are logical one with BLB2 (n), transistor M1 and M2 conducting, make voltage VVDD1 and VVDD2 normal dimensions be held in operating voltage VDD.In any pair of bit lines BL1 (n)/BLB1 (n) or BL2 (n)/BLB2 (n), write fashionablely, the operation situation of power circuit PC8 (n) is similar to the power circuit PC2 (n) in Fig. 3.

Write fashionable, suppose that random access memory 108 will write to storage unit Ue (m by logical one via bit line BL1 (n)/this port of BLB1 (n), n), therefore character line WL1 (m) meeting turn-on transistor T1 and T2, bit line BL1 (n) is logical one, and bit line BLB1 (n) is logical zero.The bit line BLB1 (n) of logical zero can close transistor M2, makes the approximate suspension joint of node np2 and reduces voltage VVDD2; In storage unit Ue (m, n), therefore the conducting degree of transistor P2 can reduce, and the voltage of node QB also can descend, and more easily via 2 electric discharges of gateway transistor T, upset is logical zero to make node QB.In addition, logical one bit line BL1 (n) makes transistor M1 conducting, and voltage VVDD normal dimensions is held in to operating voltage VDD, makes the successfully high voltage to logical one by node Q conducting of transistor P1 in storage unit Ue (m, n).

Random access memory 108 can operate on read mode with the data reading by storage unit Ue (m, n).Under this pattern, bit line BL1 (n), BLB1 (n), BL2 (n) and BLB2 (n) can first be precharged to the high voltage of logical one, then character line WL1 (m) can carry out conducting storage unit Ue (m with logical one with WL2 (m), n) transistor T 1, T2, T3 and T2 in, the voltage that makes bit line BL1 (n) and the voltage of BL2 (n) can follow node Q, and the voltage that the voltage of bit line BL1B (n) and BL2B (n) can be followed node QB.Therefore in Figure 16 with mark " x " representative arbitrarily (don ' t care) in logic.

Random access memory 108 only is applied to a kind of embodiment of dual-port (multiport) storage unit for the present invention; Other kind embodiment of power circuit PC8 (n) can be analogized and be obtained by Fig. 1, Fig. 5 and Fig. 7.In addition, the principle that random access memory 108 also can disclose according to Fig. 9 arranges another pin power circuit, thinks that transistor N1 and the N2 in each storage unit provides voltage VVSS1 and VVSS2.

In summary, as discussed earlier, modern random access memory faces the demand contradictory between reading and writing.If be optimized (similarly being to adopt weak gateway transistor in storage unit) for the demand of reading, the usefulness that writes running will be relative deteriorated with characteristic.Write running for taking into account, random access memory of the present invention is respectively to classify basis as, the regulation and control of two phase inverters that form the breech lock framework in each storage unit of same row being powered respectively according to the data of bit line, can weaken the resistance memory cell data and write the tendency of (Data flipping), and maintain/strengthen the tendency that storage unit acceptance/driving data writes (Data flipping), the usefulness write to promote data, improve the characteristic (similarly being signal noise nargin) that writes running, also make random access memory of the present invention take into account and read and the speed write, usefulness and characteristic.

In some technology, can be when writing a certain storage unit for corresponding word line acts provides extra high voltage (higher than the voltage of logical one) to increase the transistorized conducting degree of gateway, but this can cause comparatively serious half to select to disturb (half-select disturb) problem and degree of stability (stability) doubt; That is to say, concerning same a line, couple other storage unit of same character line, the transistorized conducting degree of its gateway also can increase, and easily makes its stored data be overturn mistakenly.In comparison, the present invention does not need additionally to improve word line voltages when the storage unit of access a line, can not cause half selection interference problem.In other prior art, can be at the supply voltage of being write a little less than two phase inverters of fashionable unification to each storage unit provide; Though this kind of prior art can weaken the tendency that the resistance memory cell data write, the feedback mechanism of latch circuit is related the reduction also, can't improve all sidedly data and write running.And, because this prior art will be simultaneously for two phase inverters of storage unit switch supply voltage in the lump, power consumption is higher, speed is also slower, and the time that completes switching is longer.In comparison, each phase inverter the present invention be directed in each storage unit carries out the supply voltage regulation and control separately, therefore can more fully promote, writes usefulness; And the present invention only is required to be phase inverter switching supply voltage, power consumption can be kept to half, and switch speed also can be accelerated.

Some prior art can increase by two phase inverters that extra transistor is the breech lock framework and carry out the supply voltage regulation and control in storage unit.But, this will make the layout area of storage unit increase, and be unfavorable for the lifting of layout aggregation degree.In addition, need to arrange extra transistor in each storage unit due to same row, therefore can significantly increase length and the load of bit line, the response speed of bit line is reduced, data are read and write adverse influence.Compared to this kind of prior art, the present invention does not need to change the basic framework of storage unit, can in storage unit, not set up extra transistor, same array storage unit is shared same power circuit, therefore the impact of pairs of bit line load, operational effectiveness, layout area and total lock number (gate count) is all very little.In addition, because the present invention carries out the supply voltage regulation and control according to the sequential of bit line data, thus do not need extra sequential control, but the various circuit characteristic variations that also resisting process, temperature and/or voltage drift cause.

The above, only embodiments of the invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with embodiment, yet not in order to limit the present invention, any those skilled in the art, within not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.

Claims

1. a random access memory, it includes:

A plurality of storage unit that are arranged as row, each storage unit is provided with one first power end, one second power end and an end, and the position end of described a plurality of storage unit all is coupled to same bit line, and each storage unit includes:

One first phase inverter, have a power end, an input end and an output terminal, couples respectively this first power end, one second back end and one first back end;

One second phase inverter, have a power end, an input end and an output terminal, couples respectively this second power end, this first back end and this second back end; And

One gateway transistor, an end couples this end, and the other end couples one of them of this second back end and this first back end; And

One power circuit, be provided with one first feeder ear and one second feeder ear, couples respectively the first power end and second power end of described a plurality of storage unit; This power circuit includes:

One power switch, couple this bit line and this feeder ear, and receive a write control signal, writing the fashionable decision of the voltage according to this bit line whether will be by this first feeder ear conducting to an operating voltage according to this, and when reading, make this first feeder ear and this second feeder ear all be maintained at this operating voltage

Wherein, this operating voltage is the nominal supply voltages of this random access memory.

2. random access memory according to claim 1, it is characterized in that: this power circuit separately includes:

One electric power maintainer, couple this first feeder ear; When this power switch, not by this feeder ear conducting during to this operating voltage, this electric power maintainer provides an electric current in this feeder ear.

3. random access memory according to claim 1, it is characterized in that: this power switch includes:

One power transistor, have a grid and two links, couples respectively this bit line, this operating voltage and this first feeder ear.

4. random access memory according to claim 3, it is characterized in that: this power switch separately includes:

One logical circuit, be coupled between this grid and this bit line; This logical circuit carries out logical operation by the voltage of this bit line and write control signal, and whether this power transistor is to determine this first feeder ear conducting to this operating voltage according to the operation result of this logical circuit.

5. random access memory according to claim 1, it is characterized in that: the gateway transistor in each storage unit is coupled between this first back end and this end, and each storage unit separately is provided with a second end, and separately include one second gateway transistor, be coupled between this second back end and this second end; The second end of described a plurality of storage unit all is coupled to one second bit line; And this power circuit separately includes:

Whether one second power switch, couple this second bit line and this second feeder ear, to write the fashionable decision of the voltage according to this second bit line will be by this second feeder ear conducting to this operating voltage.

6. random access memory according to claim 1, it is characterized in that: each storage unit in described a plurality of storage unit separately is provided with one the 3rd power end and one the 4th power end; The first phase inverter in each storage unit separately is provided with a second source end, couples the 3rd power end; The second phase inverter in each storage unit separately is provided with a second source end, couples the 4th power end; And this random access memory separately includes:

One second source circuit, be provided with one the 3rd feeder ear, couples the 4th power end of described a plurality of storage unit;

And this second source circuit includes:

One second power switch, couple the 3rd feeder ear of this bit line and this second source circuit, and whether with the voltage according to this bit line, determine will be by the 3rd feeder ear conducting to the second operating voltage of this second source circuit; Wherein this second operating voltage and this operating voltage are different.

7. random access memory according to claim 6, it is characterized in that: this second source circuit separately includes:

One second electric power maintainer, be coupled to the 3rd feeder ear of this second source circuit; When this second power switch, not by the feeder ear conducting of second source circuit during to this second operating voltage, this second electric power maintainer provides an electric current in the 3rd feeder ear of this second source circuit.

8. random access memory according to claim 1, it is characterized in that: the gateway transistor in each storage unit is coupled between this first back end and this end, and each storage unit separately is provided with a second end, one the 3rd power end and one the 4th power end, and separately include one second gateway transistor, be coupled between this second back end and this second end; And the first phase inverter in each storage unit separately is provided with a second source end, couple the 3rd power end; The second phase inverter in each storage unit separately is provided with a second source end, couples the 4th power end; The second end of described a plurality of storage unit all is coupled to one second bit line, and this random access memory separately includes:

And this second source circuit includes:

One second power switch, couple the feeder ear of this second bit line and this second source circuit, and whether with the voltage according to this second bit line, determine will be by the 3rd feeder ear conducting to the second operating voltage of this second source circuit; Wherein this second operating voltage and this operating voltage are different.

9. random access memory according to claim 1, it is characterized in that: the gateway transistor in each storage unit is coupled between this first back end and this end, and each storage unit separately is provided with a second end and one second gateway transistor, this second gateway transistor is coupled between this first back end and this second end; The second end of described a plurality of storage unit all is coupled to one second bit line, and the power switch in this power circuit according to the voltage of the voltage of this bit line and this second bit line whether determine write fashionable by this operating voltage conducting to this first feeder ear.

10. random access memory according to claim 9 is characterized in that: in this power switch, include:

One power transistor, have a grid and two links, and this two link couples respectively this operating voltage and this first feeder ear;

One logical circuit, be coupled between grid, this bit line and this second bit line of this power transistor; This logical circuit carries out logical operation by the voltage of the voltage of this bit line and this second bit line, and whether this power transistor is to determine this first feeder ear conducting to this operating voltage according to the operation result of this logical circuit.