CN102394844A - FPGA (Field Programmable Gate Array)-based spike potential signal parallel detection device and method - Google Patents
FPGA (Field Programmable Gate Array)-based spike potential signal parallel detection device and method Download PDFInfo
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- CN102394844A CN102394844A CN2011102296247A CN201110229624A CN102394844A CN 102394844 A CN102394844 A CN 102394844A CN 2011102296247 A CN2011102296247 A CN 2011102296247A CN 201110229624 A CN201110229624 A CN 201110229624A CN 102394844 A CN102394844 A CN 102394844A
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Abstract
The invention discloses an FPGA (Field Programmable Gate Array)-based spike potential signal parallel detection device and a method. The device comprises parallel modules, wherein each module comprises a signal receiver, a signal decomposition/reconfiguration device, a coefficient buffer, a coefficient processor, a signal detector and a signal output device. The method comprises the following steps of: receiving a signal sequence to be detected, and decomposing the signal sequence to be detected to obtain a decomposed coefficient sequence; and processing the decomposed coefficient sequence, carrying out signal sequence reconstruction to the processed coefficient sequence, detecting the reconstructed signal sequence to obtain a spike potential signal, and outputting the spike potential signal. According to the invention, the signal processing speed is improved by realizing the operation mode of the pipeline processing of the signal decomposition/reconstruction, and the multi-channel parallel detection is realized by a modularized design of the FPGA-based single-channel spike potential signal parallel detection device, so that the processing efficiency of a system is improved.
Description
Technical field
The invention belongs to the implanted field of brain-computer interfaces, be specifically related to a kind of spike signal parallel checkout gear and method based on FPGA.
Background technology
In implanted brain-computer interface technology, in the record spike, must the noise in the environment be brought in the tracer signal, also noisy interference in the electronic recording equipment simultaneously, even comprise environmental interference in the laboratory etc.And the amplitude of nerve signal is very faint, when through amplifying circuit nerve signal being amplified, inevitably noise is also amplified simultaneously, so the signal that experimental record obtains is by the serious interference signals of noise.
Spike is separated from background noise, and obtaining useful neuron information is the purpose that spike detects, and is in the implanted brain-computer interface technology nerve information to be carried out the first step in the preliminary treatment, also is a very important step.Because the correctness that nerve signal was analyzed after the mistake in the spike testing process (like spike number and positional information) all can have influence on.And spike detects and can extract useful information and to reduce redundant information, for the nerve information real time parsing lays the foundation.
In present implanted field of brain-computer interfaces; The collection of signal basically all is to accomplish through microelectrode array; Adopt multiple recording and high-frequency to sample and obtain nerve information; Have high flux property, the information scale is big and redundancy is high characteristics, with regard to facing the parallel processing problem of multi-channel electrode signal, the nerve signal processing speed based on spike has been had higher requirement in the case.Traditional spike detection algorithm can't be accomplished the multichannel parallel detection of spike on desktop computer or DSP.
FPGA (Field Programmable Gate Array is based on field programmable gate array) technology has obtained develop rapidly in recent years, can be towards the compute-intensive applications of complicacy from changing into towards the application that pure logic substitutes at first.In the FPGA device of up-to-date release; Not only be integrated with abundant configurable logic block resource (Configurable Logic Block; CLB); (Block RAM is BRAM) with the RocketIO GTP transceiver unit that is used for high-speed serial communication also to comprise a large amount of DSP unit towards the computation-intensive application, block RAM.For making things convenient for the debugging of FPGA, each FPGA manufacturer has also released logic analysis testing tool (like the ChipScope of Xilinx company) in the sheet, in the feasibility that has guaranteed on FPGA, to realize high-performance calculation on the software and hardware simultaneously.
To the parallel detection requirement of multichannel spike in the implanted brain-computer interface, the spike checkout gear that needs parallel processing capability is accomplished the parallel detection in real time of spike signal.And general employing computer is handled for the detection of spike signal in the prior art, can't satisfy the parallel requirement that detects in real time of present multichannel spike signal.
Summary of the invention
The invention provides the spike signal parallel checkout gear and the method based on FPGA of a kind of high reliability, high calculated performance, can realize the parallel processing in real time of spike signal, to improve neural decoding efficiency.
A kind of spike signal parallel checkout gear based on FPGA is made up of several parallel modules, and each module comprises: signal receiver, signal decomposition/reconstructor, coefficient buffer, coefficient processor, signal detector and signal output device; Wherein,
Described signal receiver is used to receive burst to be detected and transfers to described signal decomposition/reconstructor; Described burst to be detected is the nerve signal sequence that a path electrode is collected in the tiny array electrode in the implanted brain-computer interface;
Described signal decomposition/reconstructor; Be connected with signal detector with described signal receiver, system cache device; Be used to receive the burst to be detected that transmits by described signal receiver and decompose, the coefficient sequence after decomposing is delivered to described coefficient buffer; And be used to receive by the line reconstruction of going forward side by side of coefficient sequence after the processing of described coefficient buffer transmission, described signal detector is delivered in the reconstruct postamble sequence;
Described coefficient buffer; Be connected with coefficient processor with described signal decomposition/reconstructor; Be used to deposit the coefficient sequence after described signal decomposition/reconstructor is decomposed and be transferred to described coefficient processor, also be used to deposit the coefficient sequence after described coefficient processor is handled and be transferred to described signal decomposition/reconstructor;
Described coefficient processor is connected with described coefficient buffer, is used to receive by the coefficient sequence after the decomposition of described coefficient buffer transmission and to it handle the coefficient sequence after obtaining handling;
Described signal detector is connected with signal output device with described signal decomposition/reconstructor, is used to receive the reconstruct postamble sequence that is transmitted by described signal decomposition/reconstructor, therefrom detects the spike signal and transfers to described signal output device;
Described signal output device is connected with described signal detector, is used to receive spike signal and the output by described signal detector transmission.
In apparatus of the present invention; Described signal receiver, signal decomposition/reconstructor, coefficient buffer, coefficient processor, signal detector and signal output device are integrated on the fpga chip; The function of each part all adopts the specific function piece among the FPGA to realize, to accomplish higher spike detection efficiency.
Among the present invention; When described signal receiver receives burst to be detected; Judge the operating state of signal decomposition/reconstructor earlier, have only when the operating state of signal decomposition/reconstructor is the free time, just receive burst to be detected and transmit it to signal decomposition/reconstructor.
A kind of spike signal parallel detection method based on FPGA comprises:
(1) signal receiver is judged the operating state of signal decomposition/reconstructor, and when the operating state of signal decomposition/reconstructor was the free time, signal receiver received burst to be detected and transfers to signal decomposition/reconstructor again; Described burst to be detected is the nerve signal sequence that a path electrode is collected in the tiny array electrode in the implanted brain-computer interface;
(2) signal decomposition/reconstructor is decomposed according to selected analysis filter bank the burst to be detected that receives, and the coefficient sequence after obtaining decomposing and transferring in the coefficient buffer is deposited;
(3) will deposit in coefficient sequence after the decomposition of coefficient buffer and be delivered to coefficient processor and handle, the coefficient sequence after obtaining handling and transferring in the coefficient buffer is deposited;
(4) coefficient sequence that will deposit in after the processing of coefficient buffer is delivered to signal decomposition/reconstructor; Signal decomposition/reconstructor is carried out reconstruct according to selected reconfigurable filter group to the coefficient sequence after handling, and then the reconstruct postamble sequence is transferred to signal detector;
(5) signal detector detects according to the amplitude threshold method the reconstruct postamble sequence that receives and obtains the spike signal, and transfers to signal output device;
(6) the signal output device detection gained spike signal output that will receive.
In step (2) and (4), described selected analysis filter bank and selected reconfigurable filter group are according to the pairing bank of filters of Bior1.3 wavelet basis, comprise high pass filter group and low pass filter group.Described selected analysis filter bank and selected reconfigurable filter group multiplexing common computing module in realization based on FPGA.
In the step (2), signal decomposition/reconstructor is following to the process that the burst to be detected that receives decomposes the coefficient sequence after obtaining decomposing according to selected analysis filter bank:
Ground floor decomposes: the burst to be detected that signal receiver is received is divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains first and decomposes the approximation coefficient sequence and the first decomposition detail coefficients sequence;
The second layer decomposes: with ground floor decompose obtain first decompose the input source signal of approximation coefficient sequence as second layer analysis filter bank; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains second and decomposes the approximation coefficient sequence and the second decomposition detail coefficients sequence;
The 3rd layer of decomposition: with the second layer decompose obtain second decompose the input source signal of approximation coefficient sequence as the 3rd layer of analysis filter bank; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains the 3rd and decomposes approximation coefficient sequence and the 3rd decomposition detail coefficients sequence;
The 4th layer of decomposition: the 3rd decompose the input source signal of approximation coefficient sequence as the 4th layer of analysis filter bank with what the 3rd layer of decomposition obtained; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains the 4th and decomposes approximation coefficient sequence and the 4th decomposition detail coefficients sequence;
Layer 5 decomposes: the 4th decompose the input source signal of approximation coefficient sequence as the layer 5 analysis filter bank with what the 4th layer of decomposition obtained; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains the 5th and decomposes approximation coefficient sequence and the 5th decomposition detail coefficients sequence, decomposes and finishes.
Like this; After decomposing end; Obtain the coefficient sequence after six components are separated and deposit in the coefficient buffer, be respectively first and decompose detail coefficients sequence, second and decompose detail coefficients sequence, the 3rd and decompose detail coefficients sequence, the 4th and decompose detail coefficients sequence, the 5th and decompose detail coefficients sequence and the 5th and decompose the approximation coefficient sequence.
In the step (3), the coefficient sequence after the decomposition of depositing in the coefficient buffer is delivered to coefficient processor, and to handle the process of the coefficient sequence after obtaining handling following:
Because the 5th decomposes the approximation coefficient sequence corresponding to the shifted signal in the source signal sequence, therefore the 5th decomposition approximation coefficient sequence is done tax zero and handle, obtain the 5th approximation coefficient sequence after handling according to this;
Suffered most of noise in the source signal sequence because first decomposes the detail coefficients sequence sets, therefore decomposed the detail coefficients sequence and carry out noise removing, that is: passed through formula earlier through the hard-threshold method to first
Calculated threshold, wherein δ is a threshold value, σ
D1_noiseBe the noise variance of the first decomposition detail coefficients sequence, n is the length of the first decomposition detail coefficients sequence; Again each element and described threshold value in the first decomposition detail coefficients sequence are compared: if element then keeps initial value greater than described threshold value in the first decomposition detail coefficients sequence; If element is then thought noise less than described threshold value in the first decomposition detail coefficients sequence, do and compose zero processing; Obtain the first detail coefficients sequence after handling according to this;
Because it is less that the second decomposition detail coefficients sequence, the 3rd is decomposed detail coefficients sequence, the 4th decomposition detail coefficients sequence and the 5th decomposition detail coefficients sequence noise, therefore the second decomposition detail coefficients sequence, the 3rd being decomposed detail coefficients sequence, the 4th decomposition detail coefficients sequence and the 5th decomposition detail coefficients sequence can not process.Also can handle according to decomposing the identical method of detail coefficients sequence with processing first.Obtain the second detail coefficients sequence, the 3rd detail coefficients sequence, the 4th detail coefficients sequence and the 5th detail coefficients sequence from coefficient processor output.
Coefficient sequence after the processing of coefficient processor output comprises: the 5th approximation coefficient sequence, the first detail coefficients sequence, the second detail coefficients sequence, the 3rd detail coefficients sequence, the 4th detail coefficients sequence and the 5th detail coefficients sequence.Coefficient sequence after the processing is transferred in the coefficient buffer, and covers the coefficient sequence left in originally after the decomposition in the coefficient buffer, is stored in the middle of the coefficient buffer, gives over to signal reconstruction and uses.
In the step (4); The process that signal decomposition/reconstructor is carried out reconstruct according to described selected reconfigurable filter group to the coefficient sequence after handling is following: the coefficient sequence after will handling obtains from the coefficient buffer; As the data source of signal reconstruction, through the contrary operation of signal decomposition step being accomplished the reconstruct of signal.Be specially:
Layer 5 reconstruct: will be through the 5th detail coefficients sequence after step (3) is handled and the 5th approximation coefficient sequence input signal as layer 5 reconfigurable filter group; The 5th detail coefficients sequence is sent into high pass reconfigurable filter group; The 5th approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtains quadruple structure approximation coefficient sequence;
The 4th layer of reconstruct: with described quadruple structure approximation coefficient sequence and the input signal of the 4th detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as the 4th layer of bank of filters of reconstruct; The 4th detail coefficients sequence is sent into high pass reconfigurable filter group; Quadruple structure approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtains reconstructed approximation coefficient sequence;
The 3rd layer of reconstruct: with described reconstructed approximation coefficient sequence and the input signal of the 3rd detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as reconstructed layer bank of filters; The 3rd detail coefficients sequence is sent into high pass reconfigurable filter group; Reconstructed approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtain the second reconstruct approximation coefficient sequence;
Second layer reconstruct: with described second reconstruct approximation coefficient sequence and the input signal of the second detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as second layer reconfigurable filter group; The second detail coefficients sequence is sent into high pass reconfigurable filter group; The second reconstruct approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtain the first reconstruct approximation coefficient sequence;
Ground floor reconstruct: with described first reconstruct approximation coefficient sequence and the input signal of the first detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as ground floor reconfigurable filter group; The first detail coefficients sequence is sent into high pass reconfigurable filter group; The first reconstruct approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtain the reconstruct postamble sequence.
Among the present invention, in the realization based on FPGA of decomposition/reconstruct, adopted the stream treatment pattern to accelerate the processing of data, worked as follows:
After ground floor decomposes two approximation coefficient elements of acquisition; The second layer of cascade just can begin operation splitting so, and after the second layer decomposed two approximation coefficient elements of acquisition, then the 3rd of cascade the layer just can begin operation splitting; By that analogy, until the operation splitting of accomplishing five layers.
In like manner; The reconstruct of signal is the contrary operation of operation splitting, by after one deck calculates the approximation coefficient element that obtains a current layer down, just can begin the approximation coefficient element that calculates last layer of current layer at every turn; By that analogy, until the reconstructed operation of accomplishing five layers.
In the step (5), described amplitude threshold method detects the process that obtains the spike signal and is:
Try to achieve the standard deviation of reconstruct postamble sequence earlier; Then with the 3-5 of described standard deviation doubly as detection amplitude threshold; Each element in the reconstruct postamble sequence and described detection amplitude threshold are compared: element is then thought to detect the spike signal greater than described detection amplitude threshold in the reconstruct postamble sequence; Element is then thought noise signal less than described detected amplitude in the reconstruct postamble sequence, no spike signal.
Compared with prior art, the present invention has following beneficial technical effects:
Apparatus of the present invention and method can realize the data in high speed processing; Spike for the burst of a group length l=256 detects, and adopts all-purpose computer to handle, and needs the processing time of 2140 μ s; Adopt apparatus of the present invention and method to handle, only need the processing time of 9.68 μ s.
Apparatus of the present invention and method adopt the stream treatment pattern, and five layers of decompositions/reconstruct can maximized parallel processing, and is technological in conjunction with the FPGA Module Design, can realize that the multi-channel parallel of spike signal is handled in real time.During existing nerve signal is handled, generally be the processing of accomplishing off-line data through all-purpose computer.
Description of drawings
Fig. 1 is the structural representation block diagram of the spike signal parallel checkout gear based on FPGA of the present invention;
Fig. 2 is the sketch map based on five layers of decomposition/reconstruct in the spike signal parallel detection method of FPGA of the present invention;
Fig. 3 is the pile line operation sketch map of signal decomposition/reconstructor among the present invention.
Embodiment
Specify the present invention below in conjunction with embodiment and accompanying drawing, but the present invention is not limited to this.
Embodiment 1:
As shown in Figure 1; A kind of spike signal parallel checkout gear based on FPGA; Be made up of n parallel module, each module comprises: signal receiver 110, signal decomposition/reconstructor 120, coefficient buffer 130, coefficient processor 140, signal detector 150 and signal output device 160.
Signal decomposition/reconstructor 120; One side receives by the burst to be detected of signal receiver 110 transmission and decomposes; Coefficient sequence after decomposing is delivered to coefficient buffer 130; Receive on the other hand by the line reconstruction of going forward side by side of coefficient sequence after the processing of coefficient buffer 130 transmission, signal detector 150 is delivered in the reconstruct postamble sequence; Signal decomposition/reconstructor 120 is connected with signal receiver 110, system cache device 130 and signal detector 150;
In the said apparatus; Signal receiver 110 in each module, signal decomposition/reconstructor 120, coefficient buffer 130, coefficient processor 140, signal detector 150 and signal output device 160 are integrated on the fpga chip; The function of each part all adopts the specific function piece among the FPGA to realize, to accomplish higher spike detection efficiency.
Adopt said apparatus to realize spike signal parallel detection method, comprising based on FPGA:
(1) operating state of 110 pairs of signal decomposition/reconstructor 120 of signal receiver is judged, when the operating state of signal decomposition/reconstructor 120 was the free time, signal receiver 110 received burst to be detected and transfers to signal decomposition/reconstructor 120 again; Wherein, burst to be detected is the nerve signal that a path electrode is collected in the tiny array electrode in the implanted brain-computer interface.
(2) burst to be detected that receives of 120 pairs of signal decomposition/reconstructor decomposes according to selected analysis filter bank, and the coefficient sequence after obtaining decomposing and transferring in the coefficient buffer 130 is deposited; Selected analysis filter bank is according to the pairing bank of filters of Bior1.3 wavelet basis, comprises high pass filter group and low pass filter group.The process of decomposing is as shown in Figure 2, will be that the decomposable process of the burst X to be detected of l=256 is that example specifies below with length:
Ground floor decomposes: the length that signal receiver 110 is received is that the burst X to be detected of l=256 is divided into odd number burst and even signal sequence according to the odd even sequence number; The odd number burst is sent into high pass analysis filter bank g; The even signal sequence is sent into low pass analysis filter bank h, obtains first and decomposes the approximation coefficient sequence a1 and the first decomposition detail coefficients sequence d1;
The second layer decomposes: with ground floor decompose obtain first decompose the input source signal of approximation coefficient sequence a1 as second layer analysis filter bank; And be divided into odd number burst and even signal sequence according to the odd even sequence number; The odd number burst is sent into high pass analysis filter bank g; The even signal sequence is sent into low pass analysis filter bank h, obtains second and decomposes the approximation coefficient sequence a2 and the second decomposition detail coefficients sequence d2;
The 3rd layer of decomposition: with the second layer decompose obtain second decompose the input source signal of approximation coefficient sequence a2 as the 3rd layer of analysis filter bank; And be divided into odd number burst and even signal sequence according to the odd even sequence number; The odd number burst is sent into high pass analysis filter bank g; The even signal sequence is sent into low pass analysis filter bank h, obtains the 3rd and decomposes approximation coefficient sequence a3 and the 3rd decomposition detail coefficients sequence d3;
The 4th layer of decomposition: the 3rd decompose the input source signal of approximation coefficient sequence a3 as the 4th layer of analysis filter bank with what the 3rd layer of decomposition obtained; And be divided into odd number burst and even signal sequence according to the odd even sequence number; The odd number burst is sent into high pass analysis filter bank g; The even signal sequence is sent into low pass analysis filter bank h, obtains the 4th and decomposes approximation coefficient sequence a4 and the 4th decomposition detail coefficients sequence d4;
Layer 5 decomposes: the 4th decompose the input source signal of approximation coefficient sequence a4 as the layer 5 analysis filter bank with what the 4th layer of decomposition obtained; And be divided into odd number burst and even signal sequence according to the odd even sequence number; The odd number burst is sent into high pass analysis filter bank g; The even signal sequence is sent into low pass analysis filter bank h, obtains the 5th and decomposes approximation coefficient sequence a5 and the 5th decomposition detail coefficients sequence d5, decomposes and finishes.
Like this; After decomposing end; Obtain the coefficient sequence after six components are separated and deposit in the coefficient buffer, be respectively first and decompose detail coefficients sequence d1, second and decompose detail coefficients sequence d2, the 3rd and decompose detail coefficients sequence d3, the 4th and decompose detail coefficients sequence d4, the 5th and decompose detail coefficients sequence d5 and the 5th and decompose approximation coefficient sequence a5.
(3) will deposit in coefficient after the decomposition of coefficient buffer 130 and be delivered to coefficient processor 140 and handle, the coefficient after obtaining handling and transferring in the coefficient buffer 130 is deposited; The process of handling is following:
Because the 5th decomposes approximation coefficient sequence a5 corresponding to the shifted signal in the source signal sequence, therefore the 5th decomposition approximation coefficient sequence a5 is done tax zero and handle, obtain the 5th approximation coefficient sequence after handling according to this
A5
Concentrated most of noise in the source signal sequence because first decomposes detail coefficients sequence d1, therefore decomposed detail coefficients sequence d1 and carry out noise removing, that is: passed through formula earlier through the hard-threshold method to first
Calculated threshold, wherein δ is a threshold value, σ
D1_noiseBe the noise variance of the first decomposition detail coefficients sequence d1, n is the length of the first decomposition detail coefficients sequence d1; Again each element and threshold value δ among the first decomposition detail coefficients sequence d1 are compared: if element then keeps initial value greater than threshold value δ among the first decomposition detail coefficients sequence d1; If element is then thought noise less than threshold value δ among the first decomposition detail coefficients sequence d1, do and compose zero processing; Obtain the first detail coefficients sequence after handling according to this
D1
Because it is less that the second decomposition detail coefficients sequence d2, the 3rd decomposes detail coefficients sequence d3, the 4th decomposition detail coefficients sequence d4 and the 5th decomposition detail coefficients sequence d5 noise, therefore the second decomposition detail coefficients sequence d2, the 3rd being decomposed detail coefficients sequence d3, the 4th decomposition detail coefficients sequence d4 and the 5th decomposition detail coefficients sequence d5 can not process.Also can handle according to decomposing the identical method of detail coefficients sequence d1 with processing first.Obtain the second detail coefficients sequence from coefficient processor output
D2, the 3rd detail coefficients sequence
D3, the 4th detail coefficients sequence
D4With the 5th detail coefficients sequence
D5
Coefficient sequence after the processing of coefficient processor output comprises: the 5th approximation coefficient sequence
A5, the first detail coefficients sequence
D1, the second detail coefficients sequence
D2, the 3rd detail coefficients sequence
D3, the 4th detail coefficients sequence
D4With the 5th detail coefficients sequence
D5Coefficient sequence after the processing is transferred in the coefficient buffer 130, and covers the coefficient sequence left in originally after the decomposition in the coefficient buffer 130, is stored in the middle of the coefficient buffer 130, gives over to signal reconstruction and uses.
(4) coefficient sequence that will deposit in after the processing of coefficient buffer 130 is delivered to signal decomposition/reconstructor 120; Signal decomposition/reconstructor 120 is carried out reconstruct according to selected reconfigurable filter group to the coefficient sequence after handling, and then the reconstruct postamble sequence is transferred to signal detector 150; Selected reconfigurable filter group is according to the pairing bank of filters of Bior1.3 wavelet basis, comprises high pass filter group and low pass filter group.The process of reconstruct is as shown in Figure 2, and is specific as follows:
Layer 5 reconstruct: will be through the 5th detail coefficients sequence after step (3) is handled
D5With the 5th approximation coefficient
A5Sequence is as the input signal of reconstruct layer 5 bank of filters, with the 5th detail coefficients sequence
D5Send into high pass reconfigurable filter group
The 5th approximation coefficient sequence
A5Send into the low-pass reconstruction filters group
Obtain quadruple structure approximation coefficient sequence
A4
The 4th layer of reconstruct: with described quadruple structure approximation coefficient sequence
A4With the 4th detail coefficients sequence after step (3) is handled of depositing in coefficient buffer 130
D4As the input signal of the 4th layer of bank of filters of reconstruct, with the 4th detail coefficients sequence
D4Send into high pass reconfigurable filter group
Quadruple structure approximation coefficient sequence
A4Send into the low-pass reconstruction filters group
Obtain reconstructed approximation coefficient sequence
A3
The 3rd layer of reconstruct: with reconstructed approximation coefficient sequence
A3With the 3rd detail coefficients sequence after step (3) is handled of depositing in coefficient buffer 130
D3As the input signal of reconstructed layer bank of filters, with the 3rd detail coefficients sequence
D3Send into high pass reconfigurable filter group
With reconstructed approximation coefficient sequence
A3Send into the low-pass reconstruction filters group
Obtain the second reconstruct approximation coefficient sequence
A2
Second layer reconstruct: with the second reconstruct approximation coefficient sequence
A2With the second detail coefficients sequence after step (3) is handled of depositing in coefficient buffer 130
D2As the input signal of second layer reconfigurable filter group, with the second detail coefficients sequence
D2Send into high pass reconfigurable filter group
With the second reconstruct approximation coefficient sequence
A2Send into the low-pass reconstruction filters group
Obtain the first reconstruct approximation coefficient sequence
A1
Ground floor reconstruct: with the first reconstruct approximation coefficient sequence
A1With the first detail coefficients sequence after step (3) is handled of depositing in coefficient buffer 130
D1As the input signal of ground floor reconfigurable filter group, with the first detail coefficients sequence
D1Send into high pass reconfigurable filter group
With the first reconstruct approximation coefficient sequence
A1Send into the low-pass reconstruction filters group
Obtain reconstruct postamble sequence X '.
(5) the reconstruct postamble sequence X ' that receives of 150 pairs of signal detectors detects according to the amplitude threshold method and obtains the spike signal, and transfers to signal output device 160;
Try to achieve the standard deviation of reconstruct postamble sequence earlier; Then with the 3-5 of described standard deviation doubly as detection amplitude threshold; Each element in the reconstruct postamble sequence and this detection amplitude threshold are compared: element is then thought to detect the spike signal greater than this detection amplitude threshold in the reconstruct postamble sequence, and element is less than this detection amplitude threshold in the reconstruct postamble sequence; Then think noise signal, no spike signal.
(6) the signal output device 160 detection gained spike signal output that will receive.
As shown in Figure 3, the signal decomposition/reconstructor in apparatus of the present invention is taked the pipeline processes pattern, to accelerate the processing of data.
The streamline control of data processing is example with the decomposable process, works as follows:
Ground floor decomposes the first decomposition approximation coefficient sequence a1 and first that produces and decomposes detail coefficients sequence d1; First decomposes detail coefficients sequence d1 deposits in coefficient buffer 130; First decomposes the approximation coefficient sequence a1 conduct signal source of one deck decomposition down; Obtain first decompose among the approximation coefficient sequence a1 two elements after, can begin the operation splitting of the second layer, and the decomposition of this layer is until the processing of all elements of accomplishing list entries;
The second layer decomposes the second decomposition approximation coefficient sequence a2 and second that produces and decomposes detail coefficients sequence d2; Second decomposes detail coefficients sequence d2 deposits in coefficient buffer 130; Second decomposes the approximation coefficient sequence a2 conduct signal source of one deck decomposition down; Obtain second decompose among the approximation coefficient sequence a2 two elements after, can begin the 3rd layer operation splitting, and the decomposition of this layer is until the processing of all elements of accomplishing list entries;
The 3rd layer is decomposed the 3rd decomposition approximation coefficient sequence a3 and the 3rd that produces and decomposes detail coefficients sequence d3; The 3rd decomposes detail coefficients sequence d3 deposits in coefficient buffer 130; The 3rd decomposes the approximation coefficient sequence a3 conduct signal source of one deck decomposition down; Obtain the 3rd decompose among the approximation coefficient sequence a3 two elements after, can begin the 4th layer operation splitting, and the decomposition of this layer is until the processing of all elements of accomplishing list entries;
The 4th layer is decomposed the 4th decomposition approximation coefficient sequence a4 and the 4th that produces and decomposes detail coefficients sequence d4; The 4th decomposes detail coefficients sequence d4 deposits in coefficient buffer 130; The 4th decomposes the approximation coefficient sequence a4 conduct signal source of one deck decomposition down; Obtain the 4th decompose among the approximation coefficient sequence a4 two elements after, can begin the operation splitting of layer 5, and the decomposition of this layer is until the processing of all elements of accomplishing list entries;
Layer 5 decomposes the 5th decomposition approximation coefficient sequence a5 and the 5th that produces and decomposes detail coefficients sequence d5; The 5th decomposition approximation coefficient sequence a5 and the 5th is decomposed detail coefficients sequence d5 all deposit in coefficient buffer 130, and the decomposition of this layer is until the processing of all elements of accomplishing list entries.
The inverse process that constitutes decomposable process of reconstruct, contrary operation gets final product.
Claims (6)
1. spike signal parallel checkout gear based on FPGA; It is characterized in that; Be made up of several parallel modules, each module comprises: signal receiver, signal decomposition/reconstructor, coefficient buffer, coefficient processor, signal detector and signal output device; Wherein,
Described signal receiver is used to receive burst to be detected and transfers to described signal decomposition/reconstructor; Described burst to be detected is the nerve signal sequence that a path electrode is collected in the tiny array electrode in the implanted brain-computer interface;
Described signal decomposition/reconstructor; Be connected with signal detector with described signal receiver, system cache device; Be used to receive the burst to be detected that transmits by described signal receiver and decompose, the coefficient sequence after decomposing is delivered to described coefficient buffer; And be used to receive by the line reconstruction of going forward side by side of coefficient sequence after the processing of described coefficient buffer transmission, described signal detector is delivered in the reconstruct postamble sequence;
Described coefficient buffer; Be connected with coefficient processor with described signal decomposition/reconstructor; Be used to deposit the coefficient sequence after described signal decomposition/reconstructor is decomposed and be transferred to described coefficient processor, also be used to deposit the coefficient sequence after described coefficient processor is handled and be transferred to described signal decomposition/reconstructor;
Described coefficient processor is connected with described coefficient buffer, is used to receive by the coefficient sequence after the decomposition of described coefficient buffer transmission and to it handle the coefficient sequence after obtaining handling;
Described signal detector is connected with signal output device with described signal decomposition/reconstructor, is used to receive the reconstruct postamble sequence that is transmitted by described signal decomposition/reconstructor, therefrom detects the spike signal and transfers to described signal output device;
Described signal output device is connected with described signal detector, is used to receive spike signal and the output by described signal detector transmission.
2. the spike signal parallel detection method based on FPGA is characterized in that, comprising:
(1) signal receiver is judged the operating state of signal decomposition/reconstructor, and when the operating state of signal decomposition/reconstructor was the free time, signal receiver received burst to be detected and transfers to signal decomposition/reconstructor again; Described burst to be detected is the nerve signal sequence that a path electrode is collected in the tiny array electrode in the implanted brain-computer interface;
(2) signal decomposition/reconstructor is decomposed according to selected analysis filter bank the burst to be detected that receives, and the coefficient sequence after obtaining decomposing and transferring in the coefficient buffer is deposited;
(3) will deposit in coefficient sequence after the decomposition of coefficient buffer and be delivered to coefficient processor and handle, the coefficient sequence after obtaining handling and transferring in the coefficient buffer is deposited;
(4) coefficient sequence that will deposit in after the processing of coefficient buffer is delivered to signal decomposition/reconstructor; Signal decomposition/reconstructor is carried out reconstruct according to selected reconfigurable filter group to the coefficient sequence after handling, and then the reconstruct postamble sequence is transferred to signal detector;
(5) signal detector detects according to the amplitude threshold method the reconstruct postamble sequence that receives and obtains the spike signal, and transfers to signal output device;
(6) the signal output device detection gained spike signal output that will receive.
3. the spike signal parallel detection method based on FPGA as claimed in claim 2 is characterized in that, in step (2) and (4), described selected analysis filter bank and selected reconfigurable filter group are according to the pairing bank of filters of Bior1.3 wavelet basis.
4. like claim 2 or 3 described spike signal parallel detection methods based on FPGA; It is characterized in that; In the step (2), signal decomposition/reconstructor is following to the process that the burst to be detected that receives decomposes the coefficient sequence after obtaining decomposing according to selected analysis filter bank:
Ground floor decomposes: the burst to be detected that signal receiver is received is divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains first and decomposes the approximation coefficient sequence and the first decomposition detail coefficients sequence;
The second layer decomposes: with ground floor decompose obtain first decompose the input source signal of approximation coefficient sequence as second layer analysis filter bank; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains second and decomposes the approximation coefficient sequence and the second decomposition detail coefficients sequence;
The 3rd layer of decomposition: with the second layer decompose obtain second decompose the input source signal of approximation coefficient sequence as the 3rd layer of analysis filter bank; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains the 3rd and decomposes approximation coefficient sequence and the 3rd decomposition detail coefficients sequence;
The 4th layer of decomposition: the 3rd decompose the input source signal of approximation coefficient sequence as the 4th layer of analysis filter bank with what the 3rd layer of decomposition obtained; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains the 4th and decomposes approximation coefficient sequence and the 4th decomposition detail coefficients sequence;
Layer 5 decomposes: the 4th decompose the input source signal of approximation coefficient sequence as the layer 5 analysis filter bank with what the 4th layer of decomposition obtained; And be divided into odd number burst and even signal sequence according to the odd even sequence number; Described odd number burst is sent into the high pass analysis filter bank; Described even signal sequence is sent into the low pass analysis filter bank, obtains the 5th and decomposes approximation coefficient sequence and the 5th decomposition detail coefficients sequence, decomposes and finishes.
5. the spike signal parallel detection method based on FPGA as claimed in claim 4 is characterized in that, in the step (3), it is following that the coefficient sequence after the decomposition of depositing in the coefficient buffer is delivered to the process that coefficient processor handles:
Decompose the approximation coefficient sequence to the 5th and do tax zero processing, obtain the 5th approximation coefficient sequence after handling according to this;
Decompose the detail coefficients sequence to first and carry out noise removing, that is: pass through formula earlier through the hard-threshold method
Calculated threshold, wherein δ is a threshold value, σ
D1_noiseBe the noise variance of the first decomposition detail coefficients sequence, n is the length of the first decomposition detail coefficients sequence; Again each element and described threshold value in the first decomposition detail coefficients sequence are compared: if element then keeps initial value greater than described threshold value in the first decomposition detail coefficients sequence; If element is then thought noise less than described threshold value in the first decomposition detail coefficients sequence, do and compose zero processing; Obtain the first detail coefficients sequence after handling according to this;
Decompose detail coefficients sequence, the 3rd decomposition detail coefficients sequence, the 4th decomposition detail coefficients sequence and the 5th decomposition detail coefficients sequence to second and do not process, obtain the second detail coefficients sequence, the 3rd detail coefficients sequence, the 4th detail coefficients sequence and the 5th detail coefficients sequence from coefficient processor output.
6. the spike signal parallel detection method based on FPGA as claimed in claim 5 is characterized in that, in the step (4), the process that signal decomposition/reconstructor is carried out reconstruct according to described selected reconfigurable filter group to the coefficient sequence after handling is following:
Layer 5 reconstruct: will be through the 5th detail coefficients sequence after step (3) is handled and the 5th approximation coefficient sequence input signal as layer 5 reconfigurable filter group; The 5th detail coefficients sequence is sent into high pass reconfigurable filter group; The 5th approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtains quadruple structure approximation coefficient sequence;
The 4th layer of reconstruct: with described quadruple structure approximation coefficient sequence and the input signal of the 4th detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as the 4th layer of bank of filters of reconstruct; The 4th detail coefficients sequence is sent into high pass reconfigurable filter group; Quadruple structure approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtains reconstructed approximation coefficient sequence;
The 3rd layer of reconstruct: with described reconstructed approximation coefficient sequence and the input signal of the 3rd detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as reconstructed layer bank of filters; The 3rd detail coefficients sequence is sent into high pass reconfigurable filter group; Reconstructed approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtains the second reconstruct approximation coefficient sequence;
Second layer reconstruct: with described second reconstruct approximation coefficient sequence and the input signal of the second detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as second layer reconfigurable filter group; The second detail coefficients sequence is sent into high pass reconfigurable filter group; The second reconstruct approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtains the first reconstruct approximation coefficient sequence;
Ground floor reconstruct: with described first reconstruct approximation coefficient sequence and the input signal of the first detail coefficients sequence after step (3) is handled of depositing in the coefficient buffer as ground floor reconfigurable filter group; The first detail coefficients sequence is sent into high pass reconfigurable filter group; The first reconstruct approximation coefficient sequence is sent into the low-pass reconstruction filters group, obtains the reconstruct postamble sequence.
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