CN105322903A - Implementation method of digital lock-in amplifier based on FPGA - Google Patents
Implementation method of digital lock-in amplifier based on FPGA Download PDFInfo
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- CN105322903A CN105322903A CN201410380672.XA CN201410380672A CN105322903A CN 105322903 A CN105322903 A CN 105322903A CN 201410380672 A CN201410380672 A CN 201410380672A CN 105322903 A CN105322903 A CN 105322903A
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Abstract
The invention relates to an implementation method of a digital lock-in amplifier based on a field programmable gate array (FPGA). The digital lock-in amplifier comprises an orthogonal reference signal generation module, a carrier signal synthesis module, a CIC comb filter module, an FIR (Far Infrared Ray) low-pass filter module and a CORDIC (Coordinated Rotation Digital Computer) vector calculation module. The orthogonal reference signal generation module is used for generating SIN and COS waves of an orthogonal trigonometric function of unit amplitude in common frequency with a target signal. Product operation is carried out on an original signal and orthogonal reference signals SIN and COS through the carrier synthesis module to generate two paths of carrier signals. Underclocking is carried out on the two paths of carrier signals respectively through the CIC comb filter module, filtering processing is carried out through the FIR low-pass filter module, and then demodulation and vector calculation are carried out through the CORDIC vector calculation module, so that the amplitude and phase of the target signal are obtained. The implementation method overcomes the requirement that the phase of a one-channel reference signal must be the same as that of the target signal in a conventional digital lock-in amplifier.
Description
Technical field
The present invention relates to signal transacting field, be specifically related to the implementation method of a kind of digital lock-in amplifier based on FPGA in the detection and treatment of small-signal.
Background technology
Relative to other method for detecting weak signals, lock-in amplifier has higher stability and flexibility.Lock-in amplifier utilizes the correlation of signal to extract signal, and correlation detection can compression bandwidth to greatest extent, restraint speckle.Traditional lock-in amplifier adopts analog component to realize, but can introduce more noise like this.At present, digital lock-in amplifier is more and more applied.
But the phase requirements of the reference signal of the digital lock-in amplifier of routine is consistent with echo signal, not only add the complexity of system to a certain extent, also reduce the accuracy of detection of digital lock-in amplifier.
FPGA, i.e. field programmable gate array, its inside is made up of a large amount of gate arrays, can carry out the Digital Signal Processing computing of various complexity, and the hardware configuration of parallel data processing is its advantage in digital processing field.
FPGA is applied to digital lock-in amplifier, has given full play to the advantage of FPGA in Digital Signal Processing, further increased the performance of digital lock-in amplifier.
Summary of the invention
The object of the invention is to solve conventional numerical lock-in amplifier reference signal phase place and the necessary synchronous deficiency of echo signal, propose a kind of based on FPGA technology, low-power consumption, low cost, the implementation method of the digital lock-in amplifier that accuracy of detection is high.
The technical scheme that the present invention is adopted for achieving the above object is: a kind of implementation method of the digital lock-in amplifier based on FPGA, and the mode with functional module in FPGA realizes, and specifically comprises:
Produce frequency same with echo signal and phase place have nothing to do, the ORTHOGONAL TRIANGULAR function SIN ripple of unit amplitude, COS ripple, as the orthogonal reference signal of digital lock-in amplifier;
According to correlation detection principle, the signal to be detected of digital lock-in amplifier input is carried out product calculation with two-way orthogonal reference signal respectively, produce two-way carrier signal;
Low-pass filtering treatment is carried out to every road carrier signal, thus reaches elimination alternating current component, retain the object of DC component;
Adopt cordic algorithm to carry out demodulation to filtered signal, row vector computing of going forward side by side, thus obtain amplitude and the phase place of echo signal.
Described low-pass filtering treatment is carried out to every road carrier signal, thus reach elimination alternating current component, retain the object of DC component, be specially: by CIC comb filter, reduction frequency processing is carried out to every road carrier signal, then carries out filtering by FIR low pass filter.
The exponent number of described CIC comb filter depends on and is specially the relation between echo signal frequency and systematic sampling rate:
The present invention has the following advantages and beneficial effect:
1. the two-way reference signal in the present invention overcomes single channel reference signal phase place and necessary this requirement of same-phase of echo signal in conventional numerical lock-in amplifier;
2. the feature adopting CIC comb filter to combine with FIR low pass filter, improves the quality factor of filter, further increases the accuracy of detection of digital lock-in amplifier.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
The implementation method of a kind of digital lock-in amplifier based on FPGA involved in the present invention, by the carrier signal obtained primary signal and orthogonal reference signal product calculation, carry out the frequency reducing of CIC comb filter, the filtering of FIR low pass filter, again by CORDIC vector calculus, thus obtain amplitude and the phase place of echo signal.
As shown in Figure 1, the implementation method based on the digital lock-in amplifier of FPGA mainly comprises orthogonal reference signal generation module, carrier wave synthesis module, CIC comb filter module, FIR low pass filter blocks and CORDIC vector calculus module.
Orthogonal reference signal generation module, produce the ORTHOGONAL TRIANGULAR function SIN of the unit amplitude of frequency same with echo signal, COS ripple, as the orthogonal reference signal of digital lock-in amplifier, reference signal and echo signal have phase place independence.Two-way orthogonal reference signal efficiently solves single channel reference signal phase place and the necessary synchronous problem of echo signal in conventional numerical lock-in amplifier.
Carrier wave synthesis module, according to correlation detection principle, carries out product calculation with two-way orthogonal reference signal respectively by primary signal, reaches the effect weakening non-correlation signal strength signal intensity, produces two-way carrier signal.
Cic filter module, carries out down conversion process to two-way carrier signal respectively.The exponent number of this filter depends on the relation between echo signal frequency and systematic sampling rate; For the situation of echo signal frequency far above system sampling frequency, this module makes FIR low pass filter can by less exponent number, while reducing waveform settling time, effectively improves the filtering performance of FIR low pass filter.
FIR low pass filter blocks, carries out low-pass filtering to carrier signal, eliminates alternating current component, retains DC component.Its low-pass filtering performance is the key index of digital lock-in amplifier, determines the high accuracy that lock-in amplifier detects.
CORDIC vector calculus module, adopts cordic algorithm to carry out demodulation to filtered signal, row vector computing of going forward side by side, thus obtains amplitude and the phase place of echo signal.Cordic algorithm is existing algorithm, specifically can with reference to " FPGA of Digital Signal Processing realizes " ((U.S.) Bei Yeer work, Liu Lingyi, 2011-3-1).
Claims (3)
1. based on an implementation method for the digital lock-in amplifier of FPGA, it is characterized in that, the mode with functional module in FPGA realizes, and specifically comprises:
Produce frequency same with echo signal and phase place have nothing to do, the ORTHOGONAL TRIANGULAR function SIN ripple of unit amplitude, COS ripple, as the orthogonal reference signal of digital lock-in amplifier;
According to correlation detection principle, the signal to be detected of digital lock-in amplifier input is carried out product calculation with two-way orthogonal reference signal respectively, produce two-way carrier signal;
Low-pass filtering treatment is carried out to every road carrier signal, thus reaches elimination alternating current component, retain the object of DC component;
Adopt cordic algorithm to carry out demodulation to filtered signal, row vector computing of going forward side by side, thus obtain amplitude and the phase place of echo signal.
2. the implementation method of a kind of digital lock-in amplifier based on FPGA according to claim 1, it is characterized in that, described low-pass filtering treatment is carried out to every road carrier signal, thus reach elimination alternating current component, retain the object of DC component, be specially: by CIC comb filter, reduction frequency processing is carried out to every road carrier signal, then carries out filtering by FIR low pass filter.
3. the implementation method of a kind of digital lock-in amplifier based on FPGA according to claim 2, is characterized in that, the exponent number of described CIC comb filter depends on and is specially the relation between echo signal frequency and systematic sampling rate:
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410380672.XA CN105322903A (en) | 2014-08-04 | 2014-08-04 | Implementation method of digital lock-in amplifier based on FPGA |
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| CN201410380672.XA CN105322903A (en) | 2014-08-04 | 2014-08-04 | Implementation method of digital lock-in amplifier based on FPGA |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106483402A (en) * | 2016-09-28 | 2017-03-08 | 深圳市太赫兹科技创新研究院 | Lock-in amplifier test structure and method |
| CN107121586A (en) * | 2017-05-04 | 2017-09-01 | 吉林大学 | A kind of pair of Phase Lock Technique 20Hz ~ 20kHz multiple-frequency signal amplitude-phase detects distributed system in real time |
| CN112697762A (en) * | 2021-01-07 | 2021-04-23 | 中山复旦联合创新中心 | High-precision dissolved oxygen meter system and special SoC |
-
2014
- 2014-08-04 CN CN201410380672.XA patent/CN105322903A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106483402A (en) * | 2016-09-28 | 2017-03-08 | 深圳市太赫兹科技创新研究院 | Lock-in amplifier test structure and method |
| CN107121586A (en) * | 2017-05-04 | 2017-09-01 | 吉林大学 | A kind of pair of Phase Lock Technique 20Hz ~ 20kHz multiple-frequency signal amplitude-phase detects distributed system in real time |
| CN112697762A (en) * | 2021-01-07 | 2021-04-23 | 中山复旦联合创新中心 | High-precision dissolved oxygen meter system and special SoC |
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Application publication date: 20160210 |