CN114978181A - Signal frequency component detection system based on multi-frequency digital lock-in amplifier and FPGA implementation method - Google Patents

Abstract

The invention discloses a signal frequency component detection system based on a multi-frequency digital phase-locked amplifier and an FPGA (field programmable gate array) implementation method.A data type conversion module converts a signed shaping data type signal acquired by an ADC (analog to digital converter) into a single-precision floating point type data type signal; the signal preprocessing module carries out preprocessing of Hilbert envelope demodulation and FIR low-pass filtering on the signals after the data type conversion; the reference signal generation module adopts a DDS signal generator to generate orthogonal sine reference signals M and cosine reference signals N with different specified frequencies; the multi-frequency digital phase-locked amplifier module inputs the preliminary demodulation signals obtained by preprocessing into each digital phase-locked amplifier in a multi-path mode for further demodulation and noise reduction, removes the interference of random noise, obtains the amplitude characteristics of a plurality of frequency components in the input signals, and synthesizes reconstructed signals as output signals. The invention can effectively reduce the influence of noise interference and realize the rapid detection of a plurality of specified frequency components.

Description

Signal frequency component detection system based on multi-frequency digital phase-locked amplifier and FPGA implementation method

Technical Field

The invention relates to the technical field of digital signal processing, in particular to a multi-frequency digital lock-in amplifier-based signal frequency component detection system and an FPGA (field programmable gate array) implementation method.

Background

In the process of signal transmission, in order to transmit a baseband signal with low energy to a longer distance and keep the signal undistorted, the transmitting end needs to mix the signal with another carrier signal with high energy to generate a new signal with high energy, which is called modulated signal, and this process is called modulation. In order to obtain the frequency component information of the modulated signal, the receiving end needs to demodulate the modulated signal and detect the frequency component of interest.

Modulated signal can inevitably receive the interference of noise in transmission process, and present analog lock-in amplifier is expensive, and the structure is complicated, and is relatively poor to the detection result of use of a plurality of frequency components, and traditional multifrequency digital lock-in amplifier easily receives the noise interference influence, and can't satisfy the high-speed requirement of present signal processing to the detection of a plurality of frequencies.

Disclosure of Invention

The purpose of the invention is as follows: the invention aims to provide a signal frequency component detection system based on a multi-frequency digital phase-locked amplifier and an FPGA (field programmable gate array) realization method, and an FIR (finite impulse response) low-pass filter is designed to reduce the influence of noise interference; the DDS is adopted to generate orthogonal reference signals with different specified frequencies, and the parallel processing capability of the FPGA is utilized to realize the rapid detection of a plurality of specified frequency components.

The technical scheme is as follows:

a signal frequency component detection system based on a multi-frequency digital phase-locked amplifier comprises:

the type conversion module is used for converting the signals of the signed reshaping data type collected by the ADC into signals of a single-precision floating point type data type;

the preprocessing module is used for preprocessing Hilbert envelope demodulation and FIR low-pass filtering on the signals after the data type conversion;

the signal generating module is used for providing orthogonal sine reference signals M and cosine reference signals N with different specified frequencies for the multi-frequency digital phase-locked amplifier module to use;

and the digital phase-locked amplifier module is used for further demodulating the preliminary demodulation signal and reducing noise, removing the interference of random noise and synthesizing a reconstruction signal as an output signal.

Furthermore, the multi-frequency digital phase-locked amplifier module is composed of a plurality of digital phase-locked amplifiers and an adder, and the adder adopts an addition tree structure to synthesize a reconstructed signal.

An FPGA implementation method of a signal frequency component detection system based on a multi-frequency digital phase-locked amplifier comprises the following steps:

1) the data type conversion module converts the signals of the signed shaping data type collected by the ADC into signals of a single-precision floating point type data type, so that the data precision is ensured, and the subsequent modules can process the signals conveniently;

2) the signal preprocessing module carries out preprocessing of Hilbert envelope demodulation and FIR low-pass filtering on the signals after the data type conversion in the step 1) to obtain preliminary demodulation signals;

3) the reference signal generation module adopts a DDS signal generator to generate orthogonal sine reference signals M and cosine reference signals N with different specified frequencies for the multi-frequency digital phase-locked amplifier module to use;

4) the multi-frequency digital phase-locked amplifier module consists of a plurality of digital phase-locked amplifiers and adders, and is used for inputting preliminary demodulation signals obtained by preprocessing in the step 2) into each digital phase-locked amplifier in a multi-path parallel manner for further demodulation and noise reduction, removing the interference of random noise, obtaining the amplitude characteristics of a plurality of frequency components in the input signals, and synthesizing reconstructed signals as output signals.

Further, the hilbert envelope demodulation in step 2) is implemented in the form of convolution operation in the FPGA, so that complex operation in the hilbert transform process is avoided, and implementation in hardware systems such as the FPGA is facilitated.

Further, the DDS signal generator in step 3) is driven by a clock signal, and the system clock period is used as a step length, so that the DDS signal generator can continuously adjust the frequency of the output signal, and simultaneously, the output signal is guaranteed not to be distorted; in addition, a DDS signal generator is directly used for synchronously generating two paths of orthogonal periodic signals in the FPGA implementation process, and the phase shifting pressure of subsequent design is reduced.

Further, step 4) of each digital lock-in amplifier comprises the following steps:

s1, multiplying the preliminarily demodulated signals by a sine reference signal M and a cosine reference signal N with specified frequencies respectively to generate a first path of signal P and a second path of signal Q;

s2, performing FIR low-pass filtering processing on the first path of signal P and the second path of signal Q to obtain two paths of filtered signals;

s3, squaring and then squaring the two paths of filtered signals to obtain the amplitude of the specified frequency component;

and S4, constructing a signal of the specified frequency component according to the amplitude.

Further, FIR low-pass filtering is implemented in the form of a mole-type finite state machine in an FPGA. The operation process is to register the current signal, multiply the coefficient and then accumulate. The implementation process can ensure that the calculation of an input signal is completed in a sampling clock under the condition that the order of the filter is larger.

Has the advantages that: the invention can effectively reduce the influence of random noise interference in the transmission process of input signals and signals; the data precision of the FPGA internal data can be guaranteed to the maximum extent by using a single-precision floating point type; and a multi-path parallel processing mode is adopted to carry out frequency component detection on the preliminary demodulation signal obtained by preprocessing, so that the system structure is simplified and the system operation rate is improved.

Drawings

FIG. 1 is a block diagram of a multi-frequency digital lock-in amplifier based signal frequency component detection system;

FIG. 2 is a block diagram of an FIR low pass filter structure;

FIG. 3 is a schematic of a Moore-type state machine for an FIR low pass filter;

fig. 4 is a block diagram of a digital phase locked amplifier;

FIG. 5 is a time domain diagram of a baseband signal (a), a carrier signal (b), and a modulated signal (c) in sequence;

FIG. 6(a) is a time domain diagram of a noisy modulated signal, and FIG. 6(b) is a spectral diagram of a noisy modulated signal;

FIG. 7 shows a demodulated signal output by the signal preprocessing module;

fig. 8 is a frequency spectrum diagram of an output signal of the multi-frequency digital lock-in amplifier module.

Detailed Description

The invention is described in further detail below with reference to the examples of the drawings. Those skilled in the art will appreciate that the description is illustrative only, and is not to be construed as limiting the scope of the invention.

As shown in fig. 1, the system for detecting frequency components of a signal based on a multi-frequency digital lock-in amplifier is composed of a data type conversion module, a signal preprocessing module, a reference signal generation module and a multi-frequency digital lock-in amplifier module. Analog signals are input into a data type conversion module of the FPGA in a data type form of signed shaping after being sampled by the ADC, a signal preprocessing module carries out Hilbert envelope demodulation and FIR low-pass filtering and outputs demodulated signals, wherein the Hilbert envelope demodulation is realized in a convolution mode. For an FIR filter of order N-1, which includes N multiplication operations, N-1 delay operations, and N-1 addition operations, FIG. 2 is a block diagram of the FIR filter. The FIR low-pass filter is implemented by a mole finite state machine, fig. 3 is a state machine diagram, which is totally divided into four states, wherein the jump condition from the idle state to the ready state is the rising edge of the reference clock, and the jump conditions of other states are all counted by a counter to a specified value.

The multi-frequency digital phase-locked amplifier module is composed of a plurality of digital phase-locked amplifiers and adders, fig. 4 is a structural block diagram of the digital phase-locked amplifiers, under the control of a reference clock, a reference signal generating module generates a sine reference signal M and a cosine reference signal N with orthogonal assigned frequencies, and a series of operations are carried out on the sine reference signal M and the cosine reference signal N and a preliminary demodulation signal obtained by preprocessing, so as to detect a signal with assigned frequency components. A plurality of reference signal generating modules are instantiated in the FPGA, reference clocks with different frequencies are appointed and input into each digital phase-locked amplifier in a multi-path parallel mode, and therefore different frequency components of signals can be detected.

Taking baseband signals as impulse signals

Frequency of impact f ₀ 100Hz, and the carrier signal is a high-energy sine periodic signal S ₂ (t) sin (2 π ft), a frequency f of 2000Hz, a modulated signal of

For example, to illustrate the implementation of the present invention, fig. 5 is a time domain diagram of a baseband signal, a carrier signal, and a modulated signal in sequence. To verify the ability of the present invention to process noise interference and detect multiple frequency components, random noise is added to the modulated signal. FIG. 6(a) is a time domain diagram of a modulated signal with noise, and comparing FIG. 5(c) shows that the modulated signal is severely distorted by noise interference; fig. 6(b) is a waveform diagram of the noise-added modulated signal in the frequency domain, and it can be seen from the frequency domain that the impact frequency component of the noise-added signal is difficult to distinguish.

A DC2290A development board is used as an ADC (analog to digital converter) to collect analog signals, the noisy modulated signals are quantized into 18-bit signed digital signals after being sampled by the ADC, and the digital signals are converted into 32-bit single-precision floating-point digital signals after being processed by a data type conversion module. As shown in fig. 7, after hilbert envelope demodulation and FIR filtering, the signal preprocessing module can effectively demodulate the modulated signal subjected to noise interference.

In order to detect the fundamental frequency to 3 frequency multiplication components of the baseband signal, the reference signal generation module is instantiated for 4 times in this example, the reference clock frequencies are respectively set to 100Hz, 200Hz, 300Hz and 400Hz, and the number of digital phase-locked amplifiers included in the multi-frequency digital phase-locked amplifier is set to 4. FIG. 8 is a frequency spectrum diagram of an output signal of a multi-frequency digital lock-in amplifier module, which is capable of accurately and effectively detecting a fundamental frequency component to a frequency multiplication component of 3 modulated signals interfered by noise; comparing fig. 6(b), it is easy to see that the present invention can effectively reduce the influence of random noise interference in the input analog signal.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (7)

1. A system for detecting frequency components of a signal based on a multi-frequency digital lock-in amplifier, comprising:

the data type conversion module is used for converting the signals of the signed shaping data type collected by the ADC into signals of a single-precision floating point type data type;

the signal preprocessing module is used for preprocessing Hilbert envelope demodulation and FIR low-pass filtering on the signals after the data type conversion;

the reference signal generating module is used for providing orthogonal sine reference signals M and cosine reference signals N with different specified frequencies for the multi-frequency digital phase-locked amplifier module to use;

and the multi-frequency digital phase-locked amplifier module is used for further demodulating and denoising the preliminary demodulation signal, removing the interference of random noise and synthesizing a reconstruction signal as an output signal.

2. The system according to claim 1, wherein the multi-frequency digital lock-in amplifier module comprises a plurality of digital lock-in amplifiers and adders, and the adders adopt an addition tree structure for synthesizing the reconstructed signals.

3. The FPGA implementation method of the multi-frequency digital lock-in amplifier-based signal frequency component detection system according to claim 1, comprising the following steps:

1) the data type conversion module converts the signals of the signed shaping data type collected by the ADC into signals of a single-precision floating point type data type, so that the data precision is ensured, and the subsequent modules can process the signals conveniently;

2) the signal preprocessing module carries out preprocessing of Hilbert envelope demodulation and FIR low-pass filtering on the signals after the data type conversion in the step 1) to obtain preliminary demodulation signals;

3) the reference signal generation module adopts a DDS signal generator to generate orthogonal sine reference signals M and cosine reference signals N with different specified frequencies for the multi-frequency digital phase-locked amplifier module to use;

4) the multi-frequency digital phase-locked amplifier module consists of a plurality of digital phase-locked amplifiers and adders, and is used for inputting preliminary demodulation signals obtained by preprocessing in the step 2) into each digital phase-locked amplifier in a multi-path parallel manner for further demodulation and noise reduction, removing the interference of random noise, obtaining the amplitude characteristics of a plurality of specified frequency components in the input signals, and synthesizing reconstructed signals as output signals.

4. The FPGA realization method of claim 3, wherein the Hilbert envelope demodulation of step 2) is realized in a convolution operation form in the FPGA, so that complex operation in the Hilbert transform process is avoided, and the implementation in a hardware system such as the FPGA is facilitated.

5. The FPGA implementation method of claim 3, wherein the DDS signal generator in step 3) is driven by a clock signal, and the system clock period is taken as a step length, so that the DDS signal generator can continuously adjust the frequency of the output signal, and simultaneously, the output signal is ensured not to be distorted; and in the FPGA implementation, a DDS signal generator is directly used for synchronously generating two paths of orthogonal periodic signals, so that the phase-shifting pressure of the subsequent design is reduced.

6. The FPGA implementation method of claim 3, wherein the step 4) of each digital lock-in amplifier comprises the following steps:

s1, multiplying the preliminarily demodulated signals with a sine reference signal M and a cosine reference signal N with specified frequencies respectively to generate a first path of signal P and a second path of signal Q;

s2, performing FIR low-pass filtering processing on the first path of signal P and the second path of signal Q to obtain two paths of filtered signals;

s3, squaring and then squaring the two paths of filtered signals to obtain the amplitude of the specified frequency component;

and S4, constructing a signal of the specified frequency component according to the amplitude.

7. The FPGA implementation method of claim 3, wherein the FIR low-pass filtering is implemented in the FPGA in the form of a Moore finite state machine; the operation process is to register the current signal, multiply the coefficient and then accumulate.

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