CN102394652B - Current type digital to analog converter - Google Patents
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- CN102394652B CN102394652B CN 201110356002 CN201110356002A CN102394652B CN 102394652 B CN102394652 B CN 102394652B CN 201110356002 CN201110356002 CN 201110356002 CN 201110356002 A CN201110356002 A CN 201110356002A CN 102394652 B CN102394652 B CN 102394652B
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Abstract
The invention relates to the digital to analog conversion circuit technology field, especially relating to a current type digital to analog converter. The current type digital to analog converter comprises two sub digital to analog converters with same structures, same digital input signals and same clock input signals, wherein a positive output terminal of a first sub digital to analog converteris connected with a positive output terminal of a second sub digital to analog converter, a negative output terminal of the first sub digital to analog converter is connected with a negative output terminal of the second sub digital to analog converter, sums of difference currents of the two sub digital to analog converters are combined to form difference output of the current type digital to analog converter. In the invention, output currents of the two sub digital to analog converters are collected together, dual digital random complementation technology is employed, in the condition of notincreasing a work speed requirement of the digital to analog converter, a spurious-free dynamic range is raised, by employing a simple structure, improvement of a digital to analog converter dynamic characteristic is realized, a circuit design is easy to realize and a control mode is simple, and the current type digital to analog converter has strong application prospect.
Description
Technical field
The present invention relates to the D/A converting circuit technical field, particularly a kind of current mode digital-to-analog converter.
Background technology
Along with the continuous development of signal processing technology and the communication technology, the interfacing between digital signal and the analog signal becomes the bottleneck of restriction digital-to-analogue hybrid system.In order to satisfy the data transaction requirement of high-speed, high precision, digital to analog converter and analog to digital converter need reach high as far as possible speed and precision.In the Modern High-Speed digital to analog converter, current mode digital-to-analog converter becomes numerous engineers' first-selected structure, because it can directly drive resistive load, and has fast speeds.
Common current mode digital-to-analog converter structure mainly comprises following components as shown in Figure 1: supplied with digital signal decoding and buffer module (decoder), current supply switch array (current source and switch unit array).Wherein, comprise a plurality of current supply switchs unit in the current supply switch array, each current supply switch unit comprises current source and switch, and switch is sent to the electric current of current source output positive output end or the negative output terminal of digital to analog converter under the effect of control signal; The supplied with digital signal decoding module is used for the digital signal of input is deciphered and handled (comprise synchronously and level conversion etc.), make the signal exported can be directly as the control signal of the switch in the current supply switch array.The positive output end of digital to analog converter and any output in the negative output terminal can also can use the difference of these two outputs as the output of digital to analog converter as the output of digital to analog converter.
The performance of digital to analog converter is weighed from static characteristic and dynamic characteristic two aspects usually; consider that circuit is imperfect; digital to analog converter always has some nonlinear distortions; such as; because the current value size of current source does not match to cause usually and can cause static non linear, these nonlinear distortions can influence the overall performance of digital to analog converter.And the dynamic characteristic of digital to analog converter uses SFDR (Spurious-free Dynamic Range, Spurious Free Dynamic Range) to describe usually, and Spurious Free Dynamic Range is more little generally speaking, and kinematic nonlinearity is more obvious, and the digital to analog converter effect is also more unstable.At traditional current mode DAC (Digital to Analog Converter, digital to analog converter) in, when frequency raise, Spurious Free Dynamic Range can descend rapidly, and the reason of decline mainly contains three: the one, and the component relevant with signal non-linear that the switch motion of circuit is introduced; The 2nd, the limited output impedance of digital to analog converter is relevant with input signal; The 3rd, control signal or output current are asynchronous in the digital to analog converter.Therefore, in order to improve the dynamic range of output, improve the operating frequency of digital to analog converter, circuit should improve aspect two at this.
In order to reduce the deterioration to SFDR of above-mentioned article one factor as much as possible, be in the american documentation literature of US6061010A at publication number, people such as Adams have proposed the digital to analog converter of a kind of use Dual Return-to-Zero technology (or claiming Delayed Return-to-Zero technology).Its basic fundamental thinking is: the output of DAC be two-way RTZ (Return to Zero makes zero) signal and, wherein one road RTZ signal is normally exported at the positive half period of clock, is set to zero at the negative half-cycle of clock; Another road RTZ signal is set to zero at the positive half period of clock, normally exports (this technology can also be used the more RTZ signal of multichannel in a clock cycle) at the negative half-cycle of clock.According to the description of this patent, in scheme, the difference of all RTZ signals only is the delay on the clock, is identical at signal form.This technology has reduced nonlinear distortion to a certain extent, has improved SFDR, but also has some problems.At first be the DAC clock signal that usually needs higher frequencies (for example 2 times or more times) to generate control two-way or multichannel RTZ signal more; Secondly, more noise has been introduced in the conversion of each road RTZ signal: though these noises and signal are uncorrelated, but increased the energy size at the end of making an uproar, reduced the big or small ratio of signal and global noise; At last, DAC's making zero and stable finishing being no more than in half clock cycle, and this makes that the operating rate of DAC is higher, and design difficulty increases.
In addition, people such as Wei-Hsin Tseng have also proposed DRRZ (Digital Random Return-to-Zero, digital random makes zero) technology (sees and is published in the A CMOS 8-Bit 1.6-GSs DAC With Digital Random Return-to-Zero on the JTCASII in 2010, and be published in A 12b 1.25GSs DAC in 90nm CMOS with 70dB SFDR up to 500MHz on the ISSCC2011), with the unlatching of switch with disconnect the distortion that action causes and break up in the entire spectrum, can effectively carry SFDR.Its basic fundamental thinking is: at the positive half period of clock, and the DAC normal output signal; At the negative half-cycle of clock, the mode by DRZ (Digital Return-to-Zero, numeral makes zero) makes the output of DAC make zero.When the mode of using numeral to make zero made zero output, concrete mode was by the digital random coding, selected the electric current of half among the DAC to be sent to the positive output end of DAC randomly, selected the electric current of remaining half to be sent to the negative output terminal of DAC simultaneously.Because it is the same to be sent to the size of current of positive-negative output end of DAC, so the difference output valve of DAC is zero, namely " makes zero ".The DRRZ technology has reduced nonlinear distortion to a certain extent, has improved SFDR, but also have some problems, at first is exactly that the signal energy of DAC output is compared with the signal energy of traditional DAC output and reduced half; Secondly, DAC's making zero and stablely finishing in half clock cycle, and this makes that the operating rate of DAC is higher, and design difficulty increases.
Summary of the invention
(1) technical problem that will solve
Above-mentioned defective at prior art, the present invention improves the bigger technical problem of DAC dynamic characteristic design difficulty in order to solve in the prior art, a kind of current mode digital-to-analog converter is provided, adopt DDRC (Dual Digital Random Complementation, the even numbers word is complementary at random) technology, improved the Spurious Free Dynamic Range of circuit under the situation that does not increase the DAC design difficulty.
(2) technical scheme
For achieving the above object, the present invention adopts following technical scheme:
A kind of current mode digital-to-analog converter, described current mode digital-to-analog converter comprises: two sub-digital to analog converters with same structure and same numbers input signal and clock input signal, each subnumber weighted-voltage D/A converter comprises decoder and current supply switch array, and each unit of current supply switch array comprises at least one current source and at least one pair of switch; Decoder converts the digital input signals of corresponding subnumber weighted-voltage D/A converter to control signal with the switch of switch element in the control current supply switch array, makes at least one current source in the current supply switch array electric current be outputed to positive output end or the negative output terminal of corresponding subnumber weighted-voltage D/A converter;
Wherein, the positive output end of the positive output end of the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter positive output end of current mode digital-to-analog converter as a whole that links to each other, the negative output terminal of the negative output terminal of the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter negative output terminal of current mode digital-to-analog converter as a whole that links to each other; The difference current sum of two sub-digital to analog converters, the difference that is combined into described current mode digital-to-analog converter is exported;
And, the first subnumber weighted-voltage D/A converter is at the output of odd number clock cycle and the corresponding analog current of digital signal, in the even number clock cycle output current is resetted, control signal by switch in the current supply switch array when resetting makes the electric current in one part of current source in the current supply switch array be sent to positive output end, make the electric current of another part current source in the current supply switch array be sent to negative output terminal, and the described first subnumber weighted-voltage D/A converter is sent to positive output end at every turn when resetting electric current is identical when resetting with the last time, and the electric current that is sent to negative output terminal is identical when also resetting with the last time; And, the second subdata transducer is at the output of even number clock cycle and the corresponding analog current of digital signal, output makes current reset in the odd number clock cycle, control signal by switch in the current supply switch array when resetting makes the electric current in one part of current source in the current supply switch array be sent to positive output end, make the electric current of another part current source in the current supply switch array be sent to negative output terminal, and described second digital to analog converter is sent to positive output end at every turn when resetting electric current is identical when resetting with the last time, and the electric current that is sent to negative output terminal is identical when also resetting with the last time.
Preferably, the decoder of the described first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter is merged into a whole decoder.
Preferably, each subnumber weighted-voltage D/A converter is when the current supply switch array resets, and electric current is sent to the current source of positive output end and selects at random with the current source that is sent to negative output terminal.
The size of current that is sent to positive output end when preferably, each subnumber weighted-voltage D/A converter resets is identical with the size of current that is sent to negative output terminal.
Preferably, the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter make electric current be sent to the positive output end of digital to analog converter or the control signal of negative output terminal is generated by the pseudo-random signal maker when resetting.
Preferably, described pseudo-random signal maker is linear feedback shift register.
(3) beneficial effect
In the solution of the present invention, utilize even numbers word that the output current of two sub-digital to analog converters pools together complementary technology at random, improved Spurious Free Dynamic Range need not to improve under the situation that the digital to analog converter operating rate requires, adopt simple structure to realize the lifting of digital to analog converter dynamic characteristic, circuit design more easily realize and control mode simple, have very strong application prospect.
Description of drawings
Fig. 1 is the exemplary block diagram of current mode digital-to-analog converter in the prior art;
Fig. 2 is current supply switch cellular construction figure in the current supply switch array of current mode digital-to-analog converter among the present invention;
Fig. 3 is the output signal generating mode schematic diagram of current mode digital-to-analog converter among the present invention;
Fig. 4 is control signal schematic diagram in the current mode digital-to-analog converter circuit among the present invention;
The function truth table that Fig. 5 uses when generating for associated control signal among the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work belongs to the scope of protection of the invention.
The present invention proposes a kind of current mode digital-to-analog converter, be actually a kind of digital to analog converter that the output current with two sub-digital to analog converters pools together, adopt DDRC (Dual Digital Random Complementation, the even numbers word is complementary at random) technology, improved the Spurious Free Dynamic Range of circuit under the situation that does not increase the DAC design difficulty.The positive output end of the first subnumber weighted-voltage D/A converter links to each other with the positive output end of the second subnumber weighted-voltage D/A converter in the current mode digital-to-analog converter of the present invention, and the negative output terminal of the first subnumber weighted-voltage D/A converter links to each other with the negative output terminal of the second subnumber weighted-voltage D/A converter; Because the structure of the current supply switch array of two sub-digital to analog converters that current mode digital-to-analog converter of the present invention comprises is the same, therefore the corresponding current supply switch array of two sub-digital to analog converters can be merged the current supply switch array that namely obtains whole digital to analog converter.
More specifically, referring to accompanying drawing 2, pair of switches (first switch S 1 and second switch S2), the second current source I2 and the pair of switches that links to each other with the second current source I2 (the 3rd switch S 3 and the 4th switch S 4) that each the current supply switch unit in the current supply switch array of the current mode digital-to-analog converter that patent of the present invention proposes comprises the first current source I1, links to each other with the first current source I1; Wherein the first current source I1 and the switch S 1 that links to each other with the first current source I1 and S2 be corresponding to a current supply switch unit in the current supply switch array of the first subnumber weighted-voltage D/A converter, and the second current source I2 and the switch S 3 that links to each other with the second current source I2 and S4 are corresponding to a current supply switch unit in the current supply switch array of the second subnumber weighted-voltage D/A converter; The first current source I1 and the second current source I2 also are connected respectively on the fixed potential; First switch S 1 and second switch S2 also are subjected to the control of switch controlling signal P1 and switch controlling signal N1 respectively; The 3rd switch S 3 and the 4th switch S 4 also are subjected to the control of switch controlling signal P2 and switch controlling signal N2 respectively; And, when switch controlling signal P1 and N1 make switch S 1 conducting S2 close, S2 conducting when switch S 1 is closed; When switch controlling signal P2 and N2 make switch S 3 conductings S4 close, S4 conducting when switch S 3 is closed.
Above-mentioned switch controlling signal P1, N1 and P2, N2 are generated by the decoder of digital to analog converter.Design and control signal P1 by decoder, N1 and P2, the control of N2, first subnumber weighted-voltage D/A converter is at normal output of odd number clock cycle analog current, in the even number clock cycle output current is resetted, control signal by switch in the current supply switch array when resetting makes the electric current in one part of current source in the current supply switch array be sent to positive output end, make the electric current of another part current source in the current supply switch array be sent to negative output terminal, and the described first subnumber weighted-voltage D/A converter is sent to the electric current identical (electric current that is sent to positive output end when at every turn resetting is same value) of positive output end at every turn when resetting, the electric current that is sent to negative output terminal is identical (electric current that is sent to negative output terminal when namely at every turn resetting also is same value, and this value deducts the positive output end current value for the current source current value) also; And, the second subdata transducer is at the output of even number clock cycle and the corresponding analog current of digital signal, output makes current reset in the odd number clock cycle, control signal by switch in the current supply switch array when resetting makes the electric current in one part of current source in the current supply switch array be sent to positive output end, make the electric current of another part current source in the current supply switch array be sent to negative output terminal, and described second digital to analog converter is sent to positive output end at every turn when resetting electric current identical (electric current that is sent to positive output end when at every turn resetting is same value), the electric current that is sent to negative output terminal is identical (electric current that is sent to negative output terminal when namely at every turn resetting also is same value, and this value deducts the positive output end current value for the current source current value) also.
Need to prove: when resetting, the electric current that each subnumber weighted-voltage D/A converter is sent to positive output end and the electric current that is sent to negative output terminal can be identical also can be inequality.When the electric current that is sent to positive output end and the electric current that is sent to negative output terminal are inequality, be equal in the difference output of last digital to analog converter and have a fixing DC component, this does not influence the use of actual number weighted-voltage D/A converter, because the broadband digital to analog converter only utilizes it to exchange output usually.
The example that the output signal that accompanying drawing 3 has provided current mode digital-to-analog converter of the present invention when adopting the DDRC technical work generates.In accompanying drawing 3, clock signal clk is providing the frequency synchronization signal of system works regularly, and saltus step when parity signal began in each clock cycle is to show the odd even of present clock period; Parity signal can directly be obtained by the clock signal clk two divided-frequency.NRZ (None Return to Zero, non-return-to-zero) output signal and RZ output signal have shown that all the digital signal sequences that current mode digital-to-analog converter of the present invention will be exported in this example is 1,3,2,4,1,0.Current mode digital-to-analog converter of the present invention is when work, and output represents the current output signal of current period digital signal value (1,2,1) to the first subnumber weighted-voltage D/A converter in the 1st, 3,5 clock cycle, makes zero in the 2nd, 4,6 clock cycle output signals; The second subnumber weighted-voltage D/A converter makes zero in the 1st, 3,5 clock cycle output signals, and output represents the current output signal of current period digital signal value (3,4,0) in the 2nd, 4,6 clock cycle.Whole current mode digital-to-analog converter pools together the output current of two sub-digital to analog converters, obtains final current output signal.
After having used DDRC technology of the present invention, in the output signal of whole DAC, the nonlinear distortion that the make and break process of switch is introduced is greatly reduced.This is all to have used resetting technique at random because form any way DAC of whole DAC.By resetting at random, the nonlinear distortion that switch on and off is introduced can be broken up in the passband of whole DAC.It is similar that people such as this and Wei-Hsin Tseng propose the DRRZ know-why, but then, DDRC technology of the present invention has more advantage than DRRZ: the amount of the noise that the switch in the technical solution of the present invention is introduced is identical with DRRZ, but signal energy but than DRRZ height 100%, so SFDR also can be more than the high 6dB; And DDRC technology of the present invention do not require that signal finishes conversion in half clock cycle, but finishes conversion in a clock cycle, and this has just alleviated the requirement of DAC operating rate; At last, the size of current that DRRZ specification requirement DAC when making zero is sent to the reversal output is the same, be that the difference output valve is zero, but the size of current that arbitrary sub-DAC allows it to be sent to whole DAC reversal output when resetting in the art of this patent is different, and namely the difference output valve of sub-DAC can be non-vanishing.
In addition, the Dual Return-to-Zero technology that people such as the DDRC technology among the present invention and Adams propose is diverse, main difference mainly contains following several aspect: 1, the Dual Return-to-Zero technology that proposes of people such as Adams is used be waveform identical, but have the adding up of several RTZ signals of different delayed time, be the adding up of signal of waveform DAC inequality fully and the present invention uses; 2, the RTZ signal all made zero in each clock cycle in the DualReturn-to-Zero technology that proposes of people such as Adams, however the present invention in the whole clock cycle normal output or in the whole clock cycle, reset to can be non-vanishing certain dc state; 3, the Dual Return-to-Zero technology that proposes of people such as Adams is not used randomized technology, and its return-to-zero mode that provides is to use the mode of by-pass switch to realize in analog circuit; And the present invention has used the randomized technique in the digital circuit, and modular circuit is consistent with traditional non-return-to-zero circuit structure, does not need to use by-pass switch.Compare with the Dual Return-to-Zero technology that people such as Adams proposes, the advantage that the present invention has comprises: 1, the signal conversion need not finished in half period, but finishes in one-period, and this has just greatly alleviated the requirement of DAC operating rate; 2, the current switch control signal occurs in pairs, this is identical with traditional DAC, the present invention compares with traditional DAC designing technique, except having more a way DAC, the circuit that needs to change only is the digital circuit part, and this makes circuit design carry out easily, and the extra bypass control signal of Dual Return-to-Zero Technology Need that people such as Adams propose, its generating mode complexity, sequential is wayward; 3, the present invention has used the randomized technique in the digital circuit, and modular circuit is consistent with traditional non-return-to-zero circuit structure, does not need to use by-pass switch.
Above execution mode only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. a current mode digital-to-analog converter is characterized in that, described current mode digital-to-analog converter comprises:
Two sub-digital to analog converters with same structure and same numbers input signal and clock input signal, each subnumber weighted-voltage D/A converter comprises decoder and current supply switch array, and wherein each unit of current supply switch array comprises at least one current source and the anti-phase switch of at least one pair of control signal; Decoder converts the digital input signals of corresponding subnumber weighted-voltage D/A converter to control signal with the switch in the control current supply switch array, makes at least one current source in the current supply switch array electric current be outputed to positive output end or the negative output terminal of corresponding subnumber weighted-voltage D/A converter;
Wherein, the positive output end of the positive output end of the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter positive output end of current mode digital-to-analog converter as a whole that links to each other, the negative output terminal of the negative output terminal of the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter negative output terminal of current mode digital-to-analog converter as a whole that links to each other; The difference current sum of two sub-digital to analog converters, the difference that is combined into described current mode digital-to-analog converter is exported;
And, the first subnumber weighted-voltage D/A converter is at the output of odd number clock cycle and the corresponding analog current of digital signal, in the even number clock cycle output current is resetted, control signal by switch in the current supply switch array when resetting makes the electric current in one part of current source in the current supply switch array be sent to positive output end, make the electric current of another part current source in the current supply switch array be sent to negative output terminal, and the described first subnumber weighted-voltage D/A converter is sent to positive output end at every turn when resetting electric current is identical when resetting with the last time, and the electric current that is sent to negative output terminal is identical when also resetting with the last time; And, the second subdata transducer is at the output of even number clock cycle and the corresponding analog current of digital signal, output makes current reset in the odd number clock cycle, control signal by switch in the current supply switch array when resetting makes the electric current in one part of current source in the current supply switch array be sent to positive output end, make the electric current of another part current source in the current supply switch array be sent to negative output terminal, and described second digital to analog converter is sent to positive output end at every turn when resetting electric current is identical when resetting with the last time, and the electric current that is sent to negative output terminal is identical when also resetting with the last time.
2. current mode digital-to-analog converter according to claim 1 is characterized in that, the decoder of the described first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter is merged into a whole decoder.
3. current mode digital-to-analog converter according to claim 1 and 2 is characterized in that, each subnumber weighted-voltage D/A converter is when the current supply switch array resets, and electric current is sent to the current source of positive output end and selects at random with the current source that is sent to negative output terminal.
4. current mode digital-to-analog converter according to claim 1 and 2 is characterized in that, each subnumber weighted-voltage D/A converter is sent to positive output end when resetting size of current is identical with the size of current that is sent to negative output terminal.
5. current mode digital-to-analog converter according to claim 3 is characterized in that, each subnumber weighted-voltage D/A converter is sent to positive output end when resetting size of current is identical with the size of current that is sent to negative output terminal.
6. current mode digital-to-analog converter according to claim 1 and 2, it is characterized in that, the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter make electric current be sent to the positive output end of digital to analog converter or the control signal of negative output terminal is generated by the pseudo-random signal maker when resetting.
7. current mode digital-to-analog converter according to claim 3, it is characterized in that, the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter make electric current be sent to the positive output end of digital to analog converter or the control signal of negative output terminal is generated by the pseudo-random signal maker when resetting.
8. current mode digital-to-analog converter according to claim 4, it is characterized in that, the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter make electric current be sent to the positive output end of digital to analog converter or the control signal of negative output terminal is generated by the pseudo-random signal maker when resetting.
9. current mode digital-to-analog converter according to claim 5, it is characterized in that, the first subnumber weighted-voltage D/A converter and the second subnumber weighted-voltage D/A converter make electric current be sent to the positive output end of digital to analog converter or the control signal of negative output terminal is generated by the pseudo-random signal maker when resetting.
10. current mode digital-to-analog converter according to claim 8 is characterized in that, described pseudo-random signal maker is linear feedback shift register.
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Citations (2)
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|---|---|---|---|---|
| US6061010A (en) * | 1997-09-25 | 2000-05-09 | Analog Devices, Inc. | Dual return-to-zero pulse encoding in a DAC output stage |
| CN101800531A (en) * | 2010-03-09 | 2010-08-11 | 清华大学 | Switching device and current mode digital-to-analog converter with same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6061010A (en) * | 1997-09-25 | 2000-05-09 | Analog Devices, Inc. | Dual return-to-zero pulse encoding in a DAC output stage |
| CN101800531A (en) * | 2010-03-09 | 2010-08-11 | 清华大学 | Switching device and current mode digital-to-analog converter with same |
Non-Patent Citations (2)
| Title |
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| 《数模转换器无杂散动态范围的改善》;李俊仕等;《内蒙古科技与经济》;20091130(第21期);第68-69页 * |
| 李俊仕等.《数模转换器无杂散动态范围的改善》.《内蒙古科技与经济》.2009,(第21期),第68-69页. |
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