CN102388165B

CN102388165B - Mems device with integrated via and spacer

Info

Publication number: CN102388165B
Application number: CN2010800085404A
Authority: CN
Inventors: 罗伯特·奥斯特罗姆
Original assignee: Capella Photonics Inc
Current assignee: Capella Photonics Inc
Priority date: 2009-02-25
Filing date: 2010-02-18
Publication date: 2013-12-04
Anticipated expiration: 2030-02-18
Also published as: EP2401421A4; JP2012517913A; US7863752B2; JP5192088B2; US20100214643A1; WO2010099027A1; CN102388165A; CA2752746A1; CA2752746C; EP2401421A1

Abstract

A MEMS device and fabrication method are disclosed. A bottom substrate having an insulating layer sandwiched between an upper layer and a lower layer may be bonded to a device layer. One or more portions of the upper layer may be selectively removed to form one or more device cavities. Conductive vias may be formed through the lower layer at locations that underlie the one or more device cavities and electrically isolated from the lower layer. Devices may be formed from the device layer. Each device overlies a corresponding device cavity. Each device may be connected to the rest of the device layer by one or more corresponding hinges formed from the device layer. One or more electrical contacts may be formed on a back side of the lower layer. Each contact is electrically connected to a corresponding conductive via.

Description

MEMS device with integrated via and interval

Require priority

The application requires the benefit of priority of the U.S. Patent Application Serial Number 12/392,947 submitted on February 25th, 2009, by reference to the full content by this U.S. Patent application, is incorporated into this.

Technical field

Embodiments of the present invention relate to the MEMS manufacturing process of MEMS device, and it is for using follow-up manufacturing process flexibly accurately in the control interval, to realize high interconnection density.More particularly, embodiments of the present invention relate to the method that forms the MEMS device array.

Background technology

At present, the MEMS two-axis mirror comprises accurate interval and electrode layer.This is undertaken by the multi-wafer adhesion technique, causes poor manufacture output.The present invention replaces interval-polar stack with an interval-through hole substrate.This technique allows multiple adhesive bonding method for subsequent technique, therefore reduces the complexity of manufacturing process and improves whole yield rate.The MEMS technology is employed in the optics field, and in optics, the small size speculum (micro mirror) of 10 μ m-500 μ m magnitudes can be activated by applied voltage.There are a large amount of prior aries (document of discovery) about mirror structure.Usually, the diaxon speculum is more useful, because speculum can be handled light beam along two-dimensional directional.Usually, these designs comprise the double-strand chain with gimmal.There are two kinds of classification actuator structures.The first classification is to make actuator be positioned at the similar face of MEMS mirror layer but be positioned at outside optical region.The example of the actuator of these types comprises that pectination drives or thermal actuator.The second classification is to make actuator be positioned at MEMS speculum below.The actuator of these types is normally electrostatic.The structure of the second classification adopts more at large in the application that requires high fill factor and/or high density speculum.An example of these structures is at United States Patent (USP) 6,984, describes in 917, and illustrates in Fig. 1.

As shown in Figure 1, speculum 1 and framework 2 are formed by same sheet material.Speculum 1 is connected to framework 2 by the thin layer member 3 formed by described sheet material.The rotation that thin layer member 3 extends along the plane perpendicular in Fig. 1 is placed.Thin layer member 3 is as the torsion spring hinge.Speculum 1 is suspended in the top of cavity 4, so that it rotates freely.Electrode 5A and 5B are arranged in cavity 4.The part of

electrode

5A and 5B supporting reflex mirror 1, wherein each side at the rotation limited by thin layer member 3 has an electrode.

When speculum 1 and below

electrode

5A, 5B in one between the time apply current potential, support rotates and leaves plane around its rotation towards charged electrode, leaves the plane limited by support frame 2.The twisting resistance formed by thin layer member 3 tends to offset the electrostatic force attracted between electrode and support.Speculum 1 can be around the axis anglec of rotation limited by thin layer member 3

, angle

Depend on the spacing of the voltage, speculum and the electrode that are applied to charged electrode and the torsional rigidity of hinge.Direction of rotation depends on which electrode is charged.For example, if apply current potential between speculum 1 and electrode 5B, speculum 1 leaves the plane of framework 2 around the axis X rotation, make the part be positioned on electrode 5B of speculum 1 move down towards this electrode.

In the device of type shown in Figure 1,

electrode

5A and 5B electricity each other separate, to avoid the large electric current between them when applying voltage.In fact, in order to allow speculum along tilting clockwise and counterclockwise in Fig. 1, need two electrodes.For the twin shaft operation, need 3 or 4 electrodes.In order to simplify control algolithm, each speculum adopts 4 electrodes usually.

Because this device operates by electrostatic force, the physical clearance between electrode and speculum is very crucial.Need to control this gap to guarantee device performance with high accuracy.Typically, in the situation that gap is less, need lower voltage by mirror tilt to certain angle.Yet maximum angle (before the hasp behavior occurs) is less.In the situation that gap is larger, mirror tilt to certain angle is needed to higher voltage, but maximum angle also increases.Therefore, there is best clearance for every kind of application.

Although it is available that through-wafer (though-wafer) is interconnected in commercial, in the situation that do not have this integrated interval Integrated Solution unavailable.To be positioned at the electrode under the MEMS mirror in order approaching, by dedicated electrode layers, to come and do not have the zone of MEMS mirror to electrically contact, start to carry out passage or approach etching (access etch) from top structure subsequently.This consumes a large amount of parts that form the zone of MEMS speculum on wafer, and this reduces the quantity of the tube core of each wafer.Adopt commercial available through hole or through-wafer interconnections can change from laterally to vertical interconnection direction.Yet, can not be with enough for the integrated wall of the thickness and precision of device operation.Result is to be combined and to provide large-scale technique free leeway with the perpendicular interconnection substrate in integrated interval.The competitor must build wall on the top of through hole wafer.The selection of technique and material will limit the selection of subsequent technique.For example, if select organic material, the subsequent technique temperature is by limited.

In multiple application, require highdensity micro mirror, no matter be 1 * N form or N * M form.The quantity of speculum increases the quantity of control electrode.For the twin shaft operation, for each micro mirror, may need 3 or 4 electrodes.Therefore, for example, for 10 * 10 micro mirror arrays, the quantity of electrode can be greatly to 300 to 400.

As seeing in Fig. 1, electrode is positioned under micro mirror.Therefore, must exist and be electrically connected to (interconnection) between the adhesive pad to electrode.In most applications, the size of adhesive pad is greater than the size of micro mirror.This usable area that causes whole tube core is the sub-fraction of whole die area, therefore greatly reduces the quantity of the tube core of each wafer.As the example of this problem of diagram, Fig. 2 shows the top view of MEMS 1 * N micro mirror array.Because the spacing of micro mirror is usually narrow than the spacing of the adhesive pad for the standard wire adhesion technique, the interconnect area 6 of fan-out shape is used for being electrically connected to optical region 7 and adhesive pad zone 8.As seen from Figure 2, can not utilize by this method the true useful zone of MEMS wafer fully.A kind of method that solves aforementioned true useful zone is that the dorsal part, the use that are placed on the MEMS wafer by the electrode contacts by adhesive pad zone 8 proceed to the electrical connection of driver electronics by solder bump technique, vertically interconnected.The solder bump technique of developing for the assembling of the flip chip for silicon (Si) CMOS provides much higher interconnection density.In order vertically to electrically contact, feasible is integrated commercial available through-wafer interconnections technology.As described the example of this interconnection technique in Application No. 20080122031,20080157339 and 20080157361, by these U.S. Patent applications are incorporated into to this.

Figure 3 illustrates common through-wafer interconnections.The through-wafer interconnections technology also can be undertaken by the standard MEMS manufacturing process.At first, can form through hole through the substrate 9 such as silicon (Si) wafer, then deposition insulating passivation layer 10 on the sidewall of through hole.Subsequently, conductive material 11 is used for filling remaining through hole.Through hole can be formed by the anisotropic etch process such as deep reaction ion etching (DRIE).Insulating passivation layer is the SiO of heat growth normally ₂.But, also can adopt other deposition technique (PECVD, CVD).The selection of conductive material is based on application.For the wherein important application of conductibility, usually adopt plated metal.If low conductibility is acceptable, in order to substrate, to there is similar thermal coefficient of expansion, usually adopt polysilicon.

The example of the MEMS gyroscope of the employing through-wafer interconnections of describing in the U.S. Patent number 7,015,060 that licenses to Kubena is shown in Figure 4, by reference this United States Patent (USP) is incorporated into to this.Adopt 4 wafers to form this gyroscope.Resonator 23 is formed by the top silicon layer of silicon-on-insulator (SOI) wafer.Pillar 12 is formed by the bottom silicon layer of this SOI wafer.The second wafer that is attached to the first wafer is used for forming another pillar 13.The 3rd wafer 14 with silicon substrate 15 is etched to form pillar and through hole.Substrate 15 is oxidized at its front and back, to form coating, and uses SiO ₂The wall lining that layer 16 is given through hole.By with filling hole with metal, forming conductive interconnection 17.In this case, due to the electricity requirement of device, electro-coppering or copper alloy are preferred to conductive material.Metal is formed in pillar and interconnection 17, and is patterned to form the electrode that is connected to interconnection.Form subsequently hole to hold pillar 13 in the 3rd wafer 14.The resonator 23 metal place on pillar subsequently is bonded to the 3rd wafer 14.Cavity 18 is formed in the basic unit 19 of the 4th wafer 20 (another SOI wafer) to hold resonator 23 and pillar 12.Adopt subsequently sealed eyelet 21 and scolder 22 that the 4th wafer 20 is bonded to the 3rd wafer 14.The 4th wafer 20 is as the lid of resonator 23.As seeing in Fig. 4, through-wafer interconnections is more than the interconnection complexity in Fig. 2.This is because it is not directly the perpendicular interconnection concept directly to be integrated into to the multiple-working mode of MEMS device.

Particularly, if the MEMS mirror device of type shown in Fig. 1 will combine with vertical through-wafer interconnections, hope is accurately controlled to the layer that forms speculum and under speculum and the spacing between the electrode on the top of through-wafer interconnections.Unfortunately, adopt as United States Patent (USP) 7,015, the technique of describing in 060 is difficult in the situation that high finished product rate obtains this precision.

In the micro mirror array application, utilize through-wafer interconnections also to have challenge.These challenges comprise, for example, and the required precision in the gap between interconnection density, electrode position and electrode and speculum.The spacing of micro mirror array is typically between 50 μ m-500 μ m.The spacing of standard solder crowing technique is about 200 μ m typically.If each speculum needs 4 electrodes, clearly, require the wiring of some form, distribute electrode with the desired pattern of the operation from by the MEMS device to the acceptable contact patterns of solder bump technique.

Embodiments of the present invention occur in this background.

Summary of the invention

Overcome the deficiencies in the prior art by the method for manufacture MEMS of the present invention (MEMS) device and the embodiment of MEMS device.

According to the first embodiment, can form one or more conductive paths through the lower floor of base substrate, base substrate has the insulating barrier be clipped between the upper and lower.Each path and lower floor's electric insulation.Path is electrically connected to the electric contact of the one or more correspondences on the dorsal part that is formed on lower floor.Optionally remove one or more parts above the one or more paths of covering of upper strata to form one or more device cavitys.Device layer is bonded to base substrate.One or more devices are formed by device layer.Each device covers one corresponding in described device cavity.The chain connection of each device by one or more correspondences of being formed by device layer is to the remainder of device layer.Each device and path electric insulation.

In some forms of the first embodiment, after forming the device cavity and before path is connected to contact, can in described one or more device cavitys, form one or more device electrodes.Each device electrode can be electrically connected to one corresponding in described path.In these forms, device electrode can be formed on the one or more parts that exposed by one or more parts of removing upper strata of insulating barrier.

In some forms of the first embodiment, base substrate can be silicon-on-insulator substrate.

In some forms of the first embodiment, can form device to form device and hinge by the selected part of removal devices layer.

In some forms of the first embodiment, one or more devices can comprise one or more speculums.

In some forms of the first embodiment, the step that forms cavity can be included in during the selection section of removing upper strata is divided the dorsal part of protecting lower floor.

In some forms of the first embodiment, device layer can be the layer of top substrate, and this top substrate has the insulating barrier be clipped between device layer and extra play.In these forms, before forming device, can remove described extra play.

In some forms of the first embodiment, device layer and base substrate can be bonded together by the high temperature adhesives process.In these forms, after device layer is bonded to base substrate, the conductive adhesion material can be set on the electric contact be formed on the dorsal part of lower floor.

In some forms of the first embodiment, can pass through the bonding device layer of low temperature adhesion process and base substrate.In these forms, before device layer is bonded to base substrate, the conductive adhesion material can be set on the electric contact be formed on the dorsal part of lower floor.

According to the second embodiment, MEMS (MEMS) device can comprise base substrate and be bonded to the device layer of base substrate.Base substrate has the insulating barrier be clipped between the upper and lower.Form one or more conductive paths in the position be positioned under described one or more device cavity through lower floor.Each path and lower floor's electric insulation.One or more parts on upper strata are optionally removed to form one or more device cavitys.One or more devices are formed by device layer.Each device covers on corresponding device cavity.The chain connection of each device by one or more correspondences of being formed by device layer is to the remainder of device layer.One or more electric contacts are formed on the dorsal part of lower floor.Each contact is electrically connected to corresponding conductive path.

In some forms of the second embodiment, base substrate can be silicon-on-insulator substrate.

In some forms of the second embodiment, the selected part of mirror layer has been removed to form device and hinge.

In some forms of the second embodiment, one or more devices comprise one or more speculums.

In some forms of the second embodiment, one or more device electrodes can be formed in described one or more device cavity.Each device electrode can be electrically connected to one corresponding in described one or more path.In these forms, one or more parts of passing through to remove upper strata that device electrode can be formed on insulating barrier are with on the one or more parts that form described one or more cavity and expose.

The accompanying drawing explanation

The profile of the MEMS speculum that Fig. 1 is prior art (prior art, US 6984917).

Fig. 2 is the example according to the top view of MEMS 1 * N micro mirror array of prior art.

The cross section of the typical through-wafer interconnections that Fig. 3 is prior art.

Fig. 4 is the example for existing MEMS device by through-wafer interconnections.

Fig. 5-19 are a series of cutaway views of the technique of detailed description manufacture MEMS device according to the embodiment of the present invention.

The specific embodiment

Although ensuing detailed description comprises for illustrating a plurality of details of purpose, it will be recognized by those skilled in the art, to the multiple variation of ensuing details with change within the scope of the present invention.Therefore, in the situation that do not lose the summary of claimed invention and claimed invention do not applied to restriction, the example of the embodiment of describing hereinafter of the present invention has been proposed.

Introduction

In embodiments of the present invention, through-wafer interconnections can integrate with the base substrate of accurate wall is provided in the MEMS device.Wall is sometimes referred to as the have through-wafer interconnections spaced walls of (STW) in this article.

The MEMS device is manufactured

By way of example rather than by the mode of restriction, Fig. 5 to Figure 19 illustrates the feasible operating sequence for the manufacture of MEMS device according to the embodiment of the present invention.Notice, in Fig. 5 to Figure 19, the size not drawn on scale.Especially, bed thickness and width are plotted as seen with the diagram related notion.In illustrated example, in order to simplify and to know purpose, described 1 * N array in Fig. 5 to Figure 19.It will be recognized by those skilled in the art, embodiments of the present invention are not limited to 1 * N structure.

Manufacturing process can be divided into three major parts: the 1) manufacture of bottom (STW) substrate; 2) manufacture of the device layer on another substrate (as, SOI substrate); And 3) base substrate and device layer are bonded together and discharge device.

As shown in Figure 5, start to manufacture the process of STW from the base substrate 101 with the insulating barrier 103 between top layer 102 and bottom 104.Top layer 102 and bottom 104 can be made by conduction or semi-conducting material.By way of example, base substrate can be commercial available semiconductor-on-insulator (SOI) wafer, is clipped in the silica (SiO between the upper and lower layer formed by silicon as had ₂) layer.Due to the wafer polishing technique of the advanced person in the manufacture that is used in the SOI wafer, can accurately obtain the thickness of top layer 102 and following insulating barrier 103.The thickness of top layer can be from several microns to hundreds of microns.By way of example, the thickness of bottom 104 can be in the magnitude of 500 μ m, thereby provides enough intensity to avoid destroying substrate during follow-up manufacturing process.Yet, when in case of necessity, substrate 101 can form thinner, to simplify the etch process of through-wafer.

In the illustrated embodiment, at first carry out the processing of bottom.For fear of during the processing at bottom 104 to the damage of top layer 102, usually at certain protective layer of the upper deposition of exposure (being sometimes referred to as front side) of top layer 102.The example that is applicable to the material of top protective layer includes but not limited to polymer, silica, silicon nitride and metal.Yet, for simplicity, not shown this protection technique here.

The exposure of bottom 104 (being sometimes referred to as rear side herein) can be by standard photoetching process patterning, to form etching mask.Etch away bottom 104 by the one or more openings in mask from rear side subsequently, to form one or more through holes 105, as shown in Figure 6.By way of example, anisotropic etching, as deep reaction ion etching (DRIE) can be used for etching through hole 105.Etching technics can have enough etching selection rates, makes insulating barrier 103 as etching stopping layer.For example, depend on adopted etching technics, SiO ₂With the etch rate of Si can (for example, the SiOs of 1: 100 very different from silicon and silica ₂: Si etching selection rate).There is SiO when adopting this etching technics to be etched between top and bottom silicon layer ₂The SOI wafer time, SiO ₂Layer can be used as etching stop layer.At Fig. 6, the hole pattern of etching is shown has straight sidewall 106.Yet in fact, sidewall may not be straight on micro-scale.

After thoroughly cleaning, insulation material layer 107 (as, SiO ₂) can be formed on the sidewall 106 of the dorsal part of bottom 104 and through hole 105, as shown in Figure 7.By way of example, insulating barrier 107 can comprise that thermal growth oxide is to guarantee good covering.Yet, because the growth rate of thermal oxide is very slow, additional insulating materials can be deposited on the top of thermal oxide, to increase base substrate and to be deposited on subsequently the breakdown voltage between the electrode on insulating barrier 107.

Conductive material 108 deposits or otherwise forms to apply the dorsal part of base substrate 104 and fills or apply through hole subsequently, as shown in Figure 8.Conductive material in through hole provides the conductive path 109 with the base substrate electric insulation by insulating materials 107.The size of through hole 105 is key parameter normally, depends on for forming the technique of conductive material 108.For example, if adopt galvanoplastic, the constriction due to the opening of through hole, may form cavity sometimes.Polysilicon is for realizing the good good conductive material covered, because it can be deposited by chemical vapor deposition (CVD).After forming conductive material 108, dorsal part can be smoothless like that as shown in Figure 8.For other photoetching process, can implement polishing step, with the planarization dorsal part, remove the conductive material outside bore region, as shown in Figure 9 simultaneously.

After planarization, can deposit interconnecting metal and be patterned, to form the one or more electrodes 110 that electrically contact with path 109, as shown in figure 10.Can deposit at the dorsal part of bottom 104 another insulating barrier 111 subsequently, and patterning, as shown in figure 11.Insulating barrier can be patterned, in order to expose the bump pad zone of electrode 110.Conductive bump material 112, as scolder, can optionally be deposited on the elevated regions of the opening exposure in the second insulating barrier 111, as shown in figure 12.Alternatively, as fruit instant, can be at fabrication stage deposition raised material after a while.Also feasible, adopt jet printing technique to apply conductive epoxy resin and replace pad.And, notice, as discussed below, also can form and patterning interconnecting metal 110 and insulating barrier 111 in the later phases of manufacturing.

Once form path 109, can start to process the front side of base substrate 101.On upset base substrate 101 and after removing protective layer, for example, by the combination of photoetching and etching technics, can optionally remove the part of top layer 102, stay the gap 113 of a part that exposes insulating barrier 103, as shown in figure 13.Due to the thickness that can accurately control top layer 102 during the manufacture in base substrate 101 (as, be less than 0.5 μ m), the etching of top layer 102 produces for example, gap with precise thickness (, being less than 0.5 μ m).

The thickness and precision of top layer 102 can be in 0.05um for the layer that is less than 5 μ m, and the thickness and precision of top layer 102 can be in 0.3 μ m for thicker layer.For similar gap thickness scope, the thickness and precision in gap 113 can be identical.Preferably, the thickness and precision in gap 113 is better than 0.5 μ m.

As shown in figure 14, can remove the selected part of insulating barrier 103 of base substrate 101 to expose the conductor of the formation path 109 in through hole.Notice, due to the interconnecting metal on dorsal part, the position of positioning through hole easily.A kind of possibility is by the control electrode that acts on device operation for conductive path 109 (that is, the conductive material in through hole).Yet, can expect to adopt other conductive layer to form electrode pattern.In this case, on the expose portion electrically contacted with path 109 that conductive electrode material 114 can be deposited on insulating barrier 103, and be patterned to form electrode, as shown in figure 15.

At the upper device architecture of manufacturing of the substrate 115 (being called device substrate herein) separated.One or more MEMS devices are made by device substrate.Be by restrictive mode by way of example and not, the MEMS device can be the MEMS speculum.Yet, in interchangeable embodiment, can manufacture other MEMS device.The example of other MEMS device comprises but is limited to accelerometer, gyroscope, pressure sensor, chemical sensor and switch.

There is multiple design option for device architecture and device substrate.Be by restrictive mode by way of example and not, device substrate 115 can be composite crystal, for example, the SOI wafer, it has the insulating barrier 117 be clipped between top layer 116 (being called device layer herein) and bottom 118.Can design the thickness of top layer 116 to realize best device performance.

Following step is that base substrate 101 and device substrate 115 are combined.Exist various ways to carry out this operation.An advantage of the method based on SOI is, whole substrate can nearly all can be made by silicon, only has the different materials of fraction.This allows the treatment temperature window of non-constant width.

For example, if select heat seal bond (wherein technological temperature is up to>1000 ℃), the filled conductive material 108 that forms path 109 can be polysilicon.After adhesion technique completes, can form and patterning interconnecting metal 110 and insulating barrier 111.Yet, if select low temperature adhesion technique, as bonding as congruent melting, after dorsal part technique completes, can deposit jointing material, as shown in figure 16.

Adhesion technique can combine base substrate 101 and device substrate 115, and wherein their corresponding top layers 102,116 face with each other, as shown in figure 17.The thick bottom 118 of device substrate 115 provides support structure for device layer 116 and insulating barrier 117 during adhesion technique.After bonding, standard technology can be for the bottom 118 of removal devices substrate 115, as shown in figure 18.The exposure of insulating barrier 117 (or, if the part of insulating barrier is removed, be the downside of the exposure of device layer 116) can be patterned subsequently, to limit the device 119 that will be formed by the device layer 116 of device substrate 115.This device is formed on the cavity formed by the gap 113 between the device layer 116 of the insulating barrier 103 of base substrate 101 and device substrate 115.As long as enough accurately control the thickness of top layer 102 during the initial manufacture of base substrate 101, the thickness of cavity can be formed to the precision of expectation.

Another etching technics of selected part by removal devices layer 116, can discharge device 119, as shown in figure 19 from top layer 116.Device 119 can be by being connected to as the one or more thin part 120 of torsion hinge the other parts of device layer 116.Device 119 is by insulating barrier 103 and insulating materials 107 and electrode 114 and path 109 electric insulations.When voltage is applied in electrode 114, device can be around hinge 120 towards electrode 114 rotations.The precise thickness of the top layer 102 of base substrate 101 provides accurate gap between device 119 and electrode 114.

Embodiments of the present invention provide for in the situation that the novel method that the yield rate (number of die of every wafer) of improving and larger technological flexibility are realized the MEMS device.Although the manufacture of individual devices for the sake of clarity is shown, it will be recognized by those skilled in the art, above-described technique can extend to the device of simultaneously manufacturing any amount on common substrate.

Although be above the complete description of the preferred embodiment of the present invention, can adopt multiple replacement, modification and equivalent.Therefore should be with reference to above not describing and determine scope of the present invention, replacement, should determine scope of the present invention with reference to the complete preservation scope of enclose claim and their equivalent.Any feature (no matter whether being preferred) can combine with any further feature (no matter whether being preferred).In ensuing claim, unless otherwise clearly indicated, indefinite article " A " or " An " relate to the quantity of one or more objects of following this article.The claim of enclosing is not to be interpreted as comprising device+functional specification, unless adopt term " for ... device " quoted clearly this restriction in given claim.

Claims

1. the method for the manufacture of MEMS (MEMS) device, comprise the steps:

A) lower floor through base substrate forms one or more conductive paths, and base substrate has the insulating barrier be clipped between the upper and lower, wherein each path and lower floor's electric insulation;

B) path is electrically connected to the electric contact of the one or more correspondences on the dorsal part that is formed on lower floor;

C) optionally remove the one or more parts above the described one or more paths of covering of upper strata, to form one or more device cavitys;

D) device layer is bonded to base substrate; And

E) form one or more devices by device layer, each in wherein said one or more device covers on of correspondence in described one or more device cavity, and each chain connection by one or more correspondences in wherein said one or more device is to the remainder of device layer, wherein each hinge is formed by device layer, and each and described one or more path electric insulations in wherein said one or more device.

2. method according to claim 1, also comprise the steps:

At step c) afterwards and in steps d) before, form one or more device electrodes in described one or more device cavitys, wherein each device electrode is electrically connected to one corresponding in described one or more path.

3. method according to claim 2, wherein one or more device electrodes be formed on insulating barrier pass through remove on one or more parts that one or more parts on upper strata expose.

4. method according to claim 1, wherein base substrate is silicon-on-insulator substrate.

5. method according to claim 1, wherein step e) comprise that the selected part of removal devices layer is to form described one or more device and one or more hinge.

6. method according to claim 1, wherein said one or more devices comprise one or more speculums.

7. method according to claim 1, wherein step c) be included in the selection section of removing upper strata and divide during the dorsal part of protection lower floor.

8. method according to claim 1, the layer that wherein device layer is top substrate, described top substrate has the insulating barrier be clipped between device layer and extra play.

9. method according to claim 8, also be included in step e) remove before the step of extra play.

10. method according to claim 1, wherein steps d) comprise the high temperature adhesives process.

11. method according to claim 9, also comprise the steps:

In steps d) afterwards, form the conductive adhesion material on the electric contact be formed on the dorsal part of lower floor.

12. method according to claim 1, wherein steps d) comprise the low temperature adhesion process.

13. method according to claim 11, also comprise the steps:

In steps d) before, form the conductive adhesion material on the electric contact be formed on the dorsal part of lower floor.

14. a MEMS (MEMS) device comprises:

A) base substrate, have the insulating barrier be clipped between the upper and lower, wherein optionally removed one or more parts on upper strata to form one or more device cavitys;

B) the one or more conductive paths that form through lower floor in the position be positioned under described one or more device cavity, wherein each path and lower floor's electric insulation;

C) be formed on the one or more electric contacts on the dorsal part of lower floor, each in wherein said one or more electric contacts is electrically connected to of correspondence in described one or more conductive path;

D) be bonded to the device layer of base substrate; With

E) the one or more devices that formed by device layer, each in wherein one or more devices covers on of correspondence in one or more device cavitys, and the chain connection of each in wherein one or more devices by one or more correspondences is to the remainder of device layer, and wherein each hinge is formed by device layer.

15. device according to claim 14, wherein base substrate is silicon-on-insulator substrate.

16. device according to claim 14, wherein the selected part of device layer has been removed to form one or more devices and one or more hinge.

17. device according to claim 14, wherein one or more devices comprise one or more speculums.

18. device according to claim 14, also comprise the one or more device electrodes that are formed in one or more device cavitys, wherein each device electrode is electrically connected to one corresponding in one or more paths.

19. device according to claim 18, wherein one or more device electrodes be formed on insulating barrier pass through remove on one or more parts that one or more parts on upper strata expose.