CN102386910A - Novel gate modulation reading circuit structure - Google Patents
Novel gate modulation reading circuit structure Download PDFInfo
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- CN102386910A CN102386910A CN2011102120273A CN201110212027A CN102386910A CN 102386910 A CN102386910 A CN 102386910A CN 2011102120273 A CN2011102120273 A CN 2011102120273A CN 201110212027 A CN201110212027 A CN 201110212027A CN 102386910 A CN102386910 A CN 102386910A
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Abstract
The invention discloses a novel gate modulation reading circuit structure, comprising a signal reading module, an integrating capacitor and a resetting switch as well as a direct current offset eliminating module, wherein the direct current offset eliminating module comprises a dark unit, a dark unit direct current offset circuit, a second gate modulation NMOS (N-channel metal oxide semiconductor) tube and a current mirror; the gate terminal of the second gate modulation NMOS tube is connected with a direct current offset level of the dark unit; and the input terminal of the current mirror is connected with the drain terminal of the second gate modulation NMOS tube of the direct current offset eliminating module, and the output terminal of the current mirror is connected with the drain terminal of a first modulation NMOS tube of the signal reading module. By applying the novel gate modulation reading circuit structure disclosed by the invention, direct current on the integrating capacitor is effectively eliminated, dynamic range of the reading circuit is widened and the sensitivity of system is improved; meanwhile, no fixed pattern noise can be introduced. Besides, a manner that a cascade tube is introduced is adopted in the invention, thus a circuit can effectively inhibit the short channel effect and the novel gate modulation reading circuit structure disclosed by the invention is applicable to an advanced deep submicron integrated circuit manufacturing process.
Description
Technical field
The present invention relates to a kind of novel grid modulation reading circuit structure, belong to the Detection of Weak Signals field.
Background technology
Along with improving constantly of scientific and technological level, the technology of integrated circuit is developed, and this array for transducer and reading circuit thereof provides guarantee.Along with Internet of Things deepens continuously what national every field was used, people are also changed sensor array into from single-sensor to the requirement of information acquisition system.This just requires the reading circuit of transducer also must accord with the requirement of extensive face battle array.Be in particular in that circuit is simpler, have higher sensitivity when realizing face battle array integrated more easily.
Demand for the reading circuit of adaptive surface battle arrayization; The Mitsubishi of Japan has proposed with the reading circuit of grid modulation circuit as extensive face battle array, (Masafumi Kimata et al., " SOI diode uncooled infrared plane arrays " as shown in Figure 1; Quantum sensing and Nanophotonic Devices III; Proc.of SPIE Vol.6127,61270X, 2006).This grid modulation electric routing sensor dc bias circuit 1, grid modulation metal-oxide-semiconductor 2, integrating capacitor 3 and MOS switch 4 connect to form through lead.The circuit form of this structure is simple, be easy to the integrated of large scale array, and noise is less.Problems such as but it exists direct current biasing excessive, makes integrating capacitor saturated easily, and dynamic range is limited.
In order to eliminate the dc bias current on the grid modulation circuit integrating capacitor, the sensitivity that further improves read-out system, traditional way is to add removing DC road as shown in Figure 2.This grid modulation electric routing sensor dc bias circuit 1, grid modulation metal-oxide-semiconductor 2, integrating capacitor 3, MOS switch 4 and PMOS pipe 5 connect to form through lead.This circuit is through introducing the form of a PMOS pipe as current source; Grid being modulated the direct current of metal-oxide-semiconductor eliminates; Make the signal code that only has transducer to produce on integrating capacitor, carry out integration, thereby improved the sensitivity of the dynamic range and the system of circuit.
Yet the grid of Mitsubishi modulation reading circuit promptly uses the PMOS pipe to remove direct current, because the unmatched reason of PMOS and NMOS also can't effectively be eliminated the grid modulation direct current that metal-oxide-semiconductor produced.And be difficult for managing a grid voltage accurately, cause the generation of fixed pattern noise, the performance that reduces whole array system to PMOS.
In addition, along with face battle array scale is increasing, reading circuit also must adopt more advanced integrated circuit production technology.More advanced production technology means the characteristic size that metal-oxide-semiconductor is littler, and this is with unavoidable introducing short-channel effect.And two kinds of circuit of Fig. 1 and Fig. 2 can't effectively suppress short-channel effect, can't be applicable to advanced deep submicron integrated circuit technology.
Summary of the invention
The objective of the invention is to overcome above-mentioned weak point; Thereby a kind of novel grid modulation reading circuit structure is provided; This circuit can effectively have been eliminated the direct current on the integrating capacitor, can not introduce fixed pattern noise again when effectively raising the sensitivity of dynamic range and system of reading circuit.
According to technical scheme provided by the invention, a kind of novel grid modulation reading circuit structure comprises that signal reads module, integrating capacitor and reset switch, and said signal is read module and is made up of transducer, transducer dc bias circuit and first grid modulation NMOS pipe; The transducer dc bias circuit that said signal is read module links to each other with the output of transducer, for transducer provides the direct current biasing; The grid end that said signal is read the first grid modulation NMOS pipe of module is the output of input termination transducer, the output voltage of transducer is converted into electric current exports at drain terminal; Drain terminal connects integrating capacitor, and the first grid modulation NMOS pipe drain terminal that step and signal are read module on the said integrating capacitor joins and realizes the integration of signal code; The last step of one termination integrating capacitor of said reset switch; Another termination reference level; Characteristic is: also comprise the direct current biasing cancellation module, said direct current biasing cancellation module is made up of dark unit, dark unit dc bias circuit, second grid modulation NMOS pipe and current mirror; The dark unit dc bias circuit of said direct current biasing cancellation module is that dark unit provides direct current biasing; And for second grid modulation NMOS pipe of direct current biasing cancellation module quiescent point is provided together with dark unit;
The DC biased level of the dark unit of grid termination of second grid modulation NMOS pipe of said direct current biasing cancellation module, drain terminal output dc bias current, source termination reference level;
The direct current of the heavy form of electric current that said current mirror provides second grid of direct current biasing cancellation module modulation NMOS pipe converts the direct current of current source form into;
The drain terminal of second grid modulation NMOS pipe of said current mirror input and direct current biasing cancellation module joins, and the drain terminal that output and signal are read the first grid modulation NMOS pipe of module joins.
As further improvement of the present invention, said dark unit dc bias circuit and transducer dc bias circuit are the isostructure circuit, have identical characteristic.
As further improvement of the present invention, said dark unit has identical characteristic with transducer, makes second grid modulation NMOS pipe of direct current biasing cancellation module have the same DC operation state with the first grid modulation NMOS pipe that signal is read module.
As further improvement of the present invention, said current mirror is made up of the PMOS pipe.
As further improvement of the present invention, said reset switch adopts cmos switch, and said reset switch is realized by cmos transmission gate, injects and clock feed-through effect to eliminate electric charge.
As further improvement of the present invention; The control termination clock signal clk of said reset switch, anti-phase control termination inversion clock signal
Compared with present technology the present invention has the following advantages:
The present invention is simple, compact and reasonable for structure; Through introducing a grid modulation metal-oxide-semiconductor of setovering by dark unit; And carry out mirror image with the direct current biasing that current mirror will be managed; Thereby a direct current equirotal dc bias current with the grid modulation metal-oxide-semiconductor of transducer is provided; Effectively eliminate the direct current on the integrating capacitor, can not introduce fixed pattern noise again when can effectively raise the sensitivity of dynamic range and system of reading circuit.In addition, the present invention also through introducing the mode of cascade pipe, makes circuit can effectively suppress short-channel effect, thereby is applicable to advanced producing process of deep submicron integrated circuit.
Description of drawings
Fig. 1 is a grid modulation reading circuit sketch map in the prior art.
Fig. 2 is the grid modulation reading circuit sketch map behind the traditional removing DC road of adding.
Fig. 3 is a novel grid modulation reading circuit sketch map of the present invention.
Embodiment
Following the present invention will combine the embodiment in the accompanying drawing to further describe:
As shown in Figure 3, the present invention is a kind of novel grid modulation reading circuit structure, reads module, direct current biasing cancellation module, integrating capacitor 3 and reset switch 4 by signal and forms.Wherein signal is read module and is made up of transducer 6, transducer dc bias circuit 1 and first grid modulation NMOS pipe 2.The direct current biasing cancellation module is made up of dark unit 7, dark unit dc bias circuit 8, second grid modulation NMOS pipe and current mirror 5.The transmission gate that reset switch 4 is made up of the NMOS and the PMOS pipe of complementation is realized.
The transducer dc bias circuit 1 that said signal is read module links to each other with the output of transducer 6, for transducer provides the direct current biasing, makes that transducer can operate as normal.During normal operation of sensor, its output provides a direct current bias level Vref1, and the first grid modulation NMOS pipe 2 of reading module for signal provides quiescent point; The grid end that signal is read the first grid modulation NMOS pipe 2 of module is an input, and drain terminal is an output, source termination reference level VSS; The output of its input termination transducer 6 is converted into electric current with the output voltage of transducer 6 and exports at drain terminal; Drain terminal connects integrating capacitor 3, and dc bias current and signal code are outputed to integrating capacitor simultaneously; The reference level VSS of source end is used for regulating the state of first grid modulation NMOS pipe 2, is in the saturation region to guarantee first grid modulation NMOS pipe 2;
The dark unit dc bias circuit 8 of said direct current biasing cancellation module provides direct current biasing for dark unit 7; And provide quiescent point (in the art for the grid modulation NMOS pipe of direct current biasing cancellation module together with dark unit 7; Dark unit and reference unit are close term; In special applications,, be public's known technology term) as being equal in the infrared imaging; Dark unit dc bias circuit 8 is the isostructure circuit with transducer dc bias circuit 1, has identical characteristic.Dark unit 7 also has identical characteristic with transducer 6, makes the NMOS pipe of direct current biasing cancellation module B have the same DC operation state with the NMOS pipe that signal is read module.
The DC biased level Vref1 of the dark unit 7 of grid termination of second grid modulation NMOS pipe 9 of said direct current biasing cancellation module, drain terminal output dc bias current, source termination reference level VSS; It is in full accord that the first grid modulation NMOS that second grid modulation NMOS pipe 9 of direct current biasing cancellation module and signal are read module manages 2 laying out pattern, has identical characteristics.Because the DC operation state of two pipes is identical, tube construction is identical, so the direct current of its output has identical value.The direct current of the heavy form of electric current that current mirror 5 provides second grid of direct current biasing cancellation module modulation NMOS pipe converts the direct current of current source form into.Current mirror 5 is made up of the PMOS pipe, and the drain terminal of second grid modulation NMOS pipe 9 of input and direct current biasing cancellation module joins, and the drain terminal that output and signal are read the first grid modulation NMOS pipe 2 of module joins.The direct current that the first grid modulation NMOS that the direct current of the current source form of its output and signal are read module manages the heavy form of electric current of 2 drain terminals disappears mutually, makes integrating capacitor 3 not carry out integration to direct current.
The first grid modulation NMOS pipe drain terminal that step and signal are read module on the integrating capacitor 3 joins and realizes the integration of signal code, subordinate's plate earthing.Reduce the influence of parasitic capacitance through such connected mode, improve the speed and the sensitivity of system circuit.
Claims (6)
1. novel grid modulation reading circuit structure comprises that signal reads module, integrating capacitor (3) and reset switch (4), and said signal is read module and modulated NMOS by transducer (6), transducer dc bias circuit (1) and the first grid and manage (2) and form; The transducer dc bias circuit (1) that said signal is read module links to each other with the output of transducer (6), for transducer provides the direct current biasing; The grid end that said signal is read the first grid modulation NMOS pipe (2) of module is the output of input termination transducer (6), the output voltage of transducer 6 is converted into electric current exports at drain terminal; Drain terminal connects integrating capacitor (3), and said integrating capacitor (3) goes up step and signal and reads the first grid modulation NMOS of module and manage (2) drain terminal and join and realize the integration of signal code; The last step of one termination integrating capacitor (3) of said reset switch (4); Another termination reference level; It is characterized in that: also comprise the direct current biasing cancellation module, said direct current biasing cancellation module is made up of dark unit (7), dark unit dc bias circuit (8), second grid modulation NMOS pipes (9) and current mirror (5); The dark unit dc bias circuit (8) of said direct current biasing cancellation module provides direct current biasing for dark unit (7); And for second grid modulation NMOS pipe of direct current biasing cancellation module quiescent point is provided together with dark unit (7);
The DC biased level of the dark unit of grid termination (7) of second grid modulation NMOS pipes (9) of said direct current biasing cancellation module, drain terminal output dc bias current, source termination reference level;
The direct current of the heavy form of electric current that said current mirror (5) provides second grid of direct current biasing cancellation module modulation NMOS pipes (9) converts the direct current of current source form into;
The drain terminal of second grid modulation NMOS pipes (9) of said current mirror (5) input and direct current biasing cancellation module joins, and the drain terminal that output and signal are read the first grid modulation NMOS pipe (2) of module joins.
2. a kind of novel grid modulation reading circuit structure as claimed in claim 1, it is characterized in that: said dark unit dc bias circuit (8) and transducer dc bias circuit (1) are the isostructure circuit, have identical characteristic.
3. a kind of novel grid modulation reading circuit structure as claimed in claim 1; It is characterized in that: said dark unit (7) has identical characteristic with transducer (6), makes second grid modulation NMOS pipes (9) of direct current biasing cancellation module have the same DC operation state with the first grid modulation NMOS pipe (2) that signal is read module.
4. a kind of novel grid modulation reading circuit structure as claimed in claim 1, it is characterized in that: said current mirror (5) is made up of the PMOS pipe.
5. a kind of novel grid modulation reading circuit structure as claimed in claim 1, it is characterized in that: said reset switch (4) adopts cmos switch, and said reset switch is realized by cmos transmission gate, injects and clock feed-through effect to eliminate electric charge.
6. a kind of novel grid modulation reading circuit structure as claimed in claim 1; It is characterized in that: the control termination clock signal clk of said reset switch (4), anti-phase control termination inversion clock signal
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| CN201110212027.3A CN102386910B (en) | 2011-07-27 | 2011-07-27 | A kind of Novel gate modulation reading circuit structure |
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| CN201110212027.3A CN102386910B (en) | 2011-07-27 | 2011-07-27 | A kind of Novel gate modulation reading circuit structure |
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| CN102386910B CN102386910B (en) | 2016-05-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102685641A (en) * | 2012-05-22 | 2012-09-19 | 天津大学 | Miniature microphone reading circuit and reading method |
| CN102818637A (en) * | 2012-08-03 | 2012-12-12 | 中国科学院上海技术物理研究所 | CTIA (Capacitive Transimpedance Amplifier) structure input stage applicable to readout circuit of IRFPA (Infrared Focus Plane Arrray) |
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| US5422854A (en) * | 1992-08-13 | 1995-06-06 | Nippondenso Co., Ltd. | Sense amplifier for receiving read outputs from a semiconductor memory array |
| CN101022218A (en) * | 2006-12-27 | 2007-08-22 | 杭州安特电力电子技术有限公司 | Medium-voltage hybrid active power filter |
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2011
- 2011-07-27 CN CN201110212027.3A patent/CN102386910B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5422854A (en) * | 1992-08-13 | 1995-06-06 | Nippondenso Co., Ltd. | Sense amplifier for receiving read outputs from a semiconductor memory array |
| CN101022218A (en) * | 2006-12-27 | 2007-08-22 | 杭州安特电力电子技术有限公司 | Medium-voltage hybrid active power filter |
Non-Patent Citations (2)
| Title |
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| CHIN-CHENG HSIEH ET AL: "《Focal-Plane-Arrays and CMOS Readout Techniques of Infrared Imaging Systems》", 《IEEE TRANSACTIONS ON CIRCUITS AND VIDEO TECHNOLOGY》 * |
| T.ISHIKAWA ET AL: "《Low-cost 320×240 uncooled IRFPA using conventional silicon IC process》", 《OPTO-ELECTRONICS REVIEW》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102685641A (en) * | 2012-05-22 | 2012-09-19 | 天津大学 | Miniature microphone reading circuit and reading method |
| CN102685641B (en) * | 2012-05-22 | 2014-09-24 | 天津大学 | Miniature microphone reading circuit and reading method |
| CN102818637A (en) * | 2012-08-03 | 2012-12-12 | 中国科学院上海技术物理研究所 | CTIA (Capacitive Transimpedance Amplifier) structure input stage applicable to readout circuit of IRFPA (Infrared Focus Plane Arrray) |
| CN102818637B (en) * | 2012-08-03 | 2014-06-04 | 中国科学院上海技术物理研究所 | CTIA (Capacitive Transimpedance Amplifier) structure input stage applicable to readout circuit of IRFPA (Infrared Focus Plane Arrray) |
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| CN102386910B (en) | 2016-05-04 |
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Effective date of registration: 20190725 Address after: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3, building 15, room 328 Patentee after: Beijing Zhongke micro Investment Management Co., Ltd. Address before: 214135 Jiangsu New District of Wuxi City Linghu Road No. 200 China Sensor Network International Innovation Park C building 4 floor Patentee before: Jiangsu Internet of Things Research & Develoment Co., Ltd. |
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Effective date of registration: 20210113 Address after: 610200 in the concentration area of Chengdu Xingu Industrial Park, Dongsheng Street, Shuangliu District, Chengdu City, Sichuan Province Patentee after: China core Microelectronics Technology Chengdu Co.,Ltd. Address before: 100029 room 328, building 15, 3 Beitucheng West Road, Chaoyang District, Beijing Patentee before: Beijing Zhongke micro Investment Management Co.,Ltd. |