CN102386865B - Operational amplification circuit - Google Patents
Operational amplification circuit Download PDFInfo
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- CN102386865B CN102386865B CN201110282437.5A CN201110282437A CN102386865B CN 102386865 B CN102386865 B CN 102386865B CN 201110282437 A CN201110282437 A CN 201110282437A CN 102386865 B CN102386865 B CN 102386865B
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Abstract
The invention relates to an operational amplification circuit, which comprises a first input end, a second input end, a first output end, a second output end, a control circuit, an adjusting circuit connected with the control circuit and a bias circuit connected with the control circuit and the adjusting circuit; the control circuit comprises a first field effect tube, a second field effect tube, a third field effect tube, a first resistor and a second resistor; the adjusting circuit comprises a comparator, a first adjustable current source connected with the comparator, a second adjustable current source connected with the comparator and the first adjustable current source, a third resistor connected with the comparator and a fourth resistor connected with the comparator; and the bias circuit comprises a bias current source, a fifth resistor connected with the bias current, a fourth field effect tube connected with the fifth resistor and a fifth field effect tube connected with the fourth field effect tube. The invention also provides an operational amplification system. The common-mode rejection ratio is increased.
Description
Technical field
The present invention relates to a kind of operational amplifier, espespecially a kind of operational amplification circuit of the high cmrr with low supply voltage and system.
Background technology
Operational amplification circuit is to have the very circuit unit of high-amplification-factor.In order to illustrate that operational amplification circuit suppresses the ability of common-mode signal, conventional common mode inhibition is compared to a technical indicator and weighs, its be defined as amplifying circuit to the voltage amplification factor of difference mode signal the ratio with the voltage amplification factor to common-mode signal, be called common-mode rejection ratio.
Difference mode signal voltage amplification factor is larger, and common-mode signal voltage amplification factor is less, and common-mode rejection ratio is higher.The ability of now operational amplification circuit inhibition common-mode signal is stronger, and the performance of operational amplification circuit is better.
And in existing operational amplification circuit, in order to obtain high cmrr, the tail current of operational amplification circuit often adopts the structure of cascade, need under high pressure work, cannot be at operation at low power supply voltage, be therefore necessary to provide a kind of operational amplification circuit and system of the high cmrr with low supply voltage.
Summary of the invention
In view of above content, be necessary to provide a kind of operational amplification circuit and system of the high cmrr with low supply voltage.
A kind of operational amplification circuit, comprise a first input end, one second input, one first output and one second output, described operational amplification circuit also comprise one with described first input end, described the second input, described the first output and the connected control circuit of described the second output, one is connected with described control circuit for regulating the regulating circuit and of electric current of described control circuit to be connected with described control circuit and described regulating circuit for the biasing circuit of proper operation electric current is provided to described operational amplification circuit, described control circuit comprises first field effect transistor being connected with described first input end, one the second field effect transistor being connected with described the second input, one the 3rd field effect transistor being connected with described the first field effect transistor and described the second field effect transistor, one the first resistance being connected with described the first field effect transistor and second resistance being connected with described the second field effect transistor, described regulating circuit comprises a comparator, one the first adjustable current source being connected with described comparator, one the second adjustable current source being connected with described comparator and described the first adjustable current source, one the 3rd resistance being connected with described comparator and the 4th resistance being connected with described comparator, described biasing circuit comprises a bias current sources, one the 5th resistance being connected with described bias current sources, one the 4th field effect transistor being connected with described the 5th resistance and the 5th field effect transistor being connected with described the 4th field effect transistor.
A kind of operation amplifier system, comprise a first input end, one second input, one first output and one second output, described operational amplification circuit also comprise one with described first input end, described the second input, described the first output and the connected control circuit of described the second output, one is connected with described control circuit is connected with described control circuit and described regulating circuit for the biasing circuit of proper operation electric current is provided to described operation amplifier system for the regulating circuit and that regulates the electric current of described control circuit and compensate the channel modulation effect of described operation amplifier system tail current.
Prior art relatively, operational amplification circuit of the present invention and system have effectively suppressed the channel modulation effect of the tail current of operational amplification circuit and system, the electric current that flows through this first field effect transistor M1 while changing with the common-mode voltage VCM ensureing at input signal and the electric current sum that flows through this second field effect transistor M2 equal to flow through the electric current of the 4th field effect transistor M4, thereby suppress common-mode gain, improved common-mode rejection ratio.
Brief description of the drawings
Fig. 1 is the system block diagram of operation amplifier system preferred embodiments of the present invention.
Fig. 2 is the circuit block diagram of operation amplifier system preferred embodiments of the present invention.
Fig. 3 is the circuit diagram of operational amplification circuit preferred embodiments of the present invention.
Embodiment
Refer to Fig. 1, operation amplifier system preferred embodiments of the present invention comprises that a first input end VIN+, one second input VIN-, one first output VOUT+, one second output VOUT-, one are connected with this control circuit for regulating the regulating circuit and of electric current of this control circuit to be connected with this control circuit and this regulating circuit for the biasing circuit of suitable operating current is provided to this operation amplifier system for the control circuit, that the differential signal of this first input end VIN+ and this second input VIN-input is amplified.The a pair of differential signal of the common reception of this first input end VIN+ and this second input VIN-, this first output VOUT+ and this second output VOUT-export a pair of differential signal after amplification jointly.
Please refer to Fig. 2, Fig. 2 is the circuit block diagram of operation amplifier system preferred embodiments of the present invention.Wherein, this control circuit comprises one first field effect transistor M1, one second field effect transistor M2, one the 3rd field effect transistor M3, one first resistance R D1 and one second resistance R D2, this regulating circuit comprises a comparator C MP, one first adjustable current source IP, one second adjustable current source IN, one the 3rd resistance R D3 and one the 4th resistance R D4, and this biasing circuit comprises a bias current sources I1, one the 5th resistance R D5, one the 4th field effect transistor M4 and one the 5th field effect transistor M5.
The annexation of operation amplifier system preferred embodiments of the present invention is as follows: the grid of this first field effect transistor M1 is connected with one end of this first input end VIN+ and the 3rd resistance R D3, the drain electrode of this first field effect transistor M1 is connected with one end and this second output VOUT-of this first resistance R D1, the grid of this second field effect transistor M2 is connected with one end of this second input VIN-and the 4th resistance R D4, and the drain electrode of this second field effect transistor M2 is connected with one end and this first output VOUT+ of this second resistance R D2.Drain electrode, one end of this first adjustable current source IP and one end of this second adjustable current source IN of the source class of this first field effect transistor M1, the source class of this second field effect transistor M2, the 3rd field effect transistor M3 connect jointly, the grid of the 3rd field effect transistor M3 is connected with one end, the drain electrode of the 4th field effect transistor M4 and the grid of the 5th field effect transistor M5 of the 5th resistance R D5, and the source class of the 4th field effect transistor M4 is connected with the drain electrode of the 5th field effect transistor M5.One end of a normal phase input end of this comparator C MP and this bias current sources I1, the grid of the other end of the 5th resistance R D5 and the 4th field effect transistor M4 is connected, and receive a reference voltage VREF, an inverting input of this comparator C MP is connected with the other end of the other end of the 3rd resistance R D3 and the 4th resistance R D4, and receive a common-mode voltage VCM of the other end of the 3rd resistance R D3 and the other end of the 4th resistance R D4 output, a positive output end of this comparator C MP is connected with a control end of this first adjustable current source IP, and export the control end of a voltage VN to this first adjustable current source IP, a reversed-phase output of this comparator C MP is connected with a control end of this second adjustable current source IN, and export the control end of a voltage VP to this second adjustable current source IN.The common power end VDD that connects of the other end of this bias current sources I1, the other end of this first resistance R D1, the other end of this second resistance R D2 and the other end of this first adjustable current source IP, the common earth terminal GND that connects of the other end of the source class of the 5th field effect transistor M5, the source class of the 3rd field effect transistor M3 and this second adjustable current source IN.
Please refer to Fig. 2 and Fig. 3, Fig. 3 is the physical circuit figure of operational amplification circuit preferred embodiments of the present invention.Wherein, this first adjustable current source IP is one the 6th field effect transistor M6, this second adjustable current source IN is one the 7th field effect transistor M7, and this comparator C MP comprises one the 8th field effect transistor M8, one the 9th field effect transistor M9,1 the tenth field effect transistor M10,1 the 11 field effect transistor M11,1 the 12 field effect transistor M12,1 the 13 field effect transistor M13 and 1 the 14 field effect transistor M14.
The physical circuit annexation of operational amplification circuit preferred embodiments of the present invention is as follows: the grid of this first field effect transistor M1 is connected with one end of this first input end VIN+ and the 3rd resistance R D3, the drain electrode of this first field effect transistor M1 is connected with one end and this second output VOUT-of this first resistance R D1, the grid of this second field effect transistor M2 is connected with one end of this second input VIN-and the 4th resistance R D4, and the drain electrode of this second field effect transistor M2 is connected with one end and this first output VOUT+ of this second resistance R D2.Drain electrode, the drain electrode of the 6th field effect transistor M6 and the drain electrode of the 7th field effect transistor M7 of the source class of this first field effect transistor M1, the source class of this second field effect transistor M2, the 3rd field effect transistor M3 connect jointly, the grid of the 3rd field effect transistor M3 is connected with one end of the 5th resistance R D5, drain electrode, the 5th grid of field effect transistor M5 and the grid of the 12 field effect transistor M12 of the 4th field effect transistor M4, and the source class of the 4th field effect transistor M4 is connected with the drain electrode of the 5th field effect transistor M5.The grid of the 6th field effect transistor M6 is connected with the drain electrode of grid, drain electrode and the tenth field effect transistor M10 of the 8th field effect transistor M8, and the drain electrode of the 7th grid of field effect transistor M7 and grid, drain electrode and the 13 field effect transistor M13 of the 14 field effect transistor M14 is connected.The grid of the 9th field effect transistor M9, drain electrode is connected with the 11 drain electrode of field effect transistor M11 and the grid of the 13 field effect transistor M13, the grid of the tenth field effect transistor M10 is connected with the other end of the 3rd resistance R D3 and the other end of the 4th resistance R D4, the source class of the tenth field effect transistor M10 and the source class of the 11 field effect transistor M11 are connected the drain electrode of the 12 field effect transistor M12 jointly, the grid of the 11 field effect transistor M11, one end of this bias current sources I1, the common reference voltage end VREF that connects of grid of the other end of the 5th resistance R D5 and the 4th field effect transistor M4.The other end of the other end of this bias current sources I1, the other end of this first resistance R D1, this second resistance R D2, the source class of the 6th field effect transistor M6, source class, the 9th source class of field effect transistor M9 and the source class of the 13 field effect transistor M13 of the 8th field effect transistor M8 connect power end VDD jointly, and source class, the 12 source class of field effect transistor M12 and the source class of the 14 field effect transistor M14 of the source class of the 5th field effect transistor M5, the source class of the 3rd field effect transistor M3, the 7th field effect transistor M7 connect earth terminal GND jointly.
The operation principle of operational amplification circuit of the present invention and system is as described below: a pair of differential signal of the common reception of this first input end VIN+ and this second input VIN-, after control circuit amplifies, export the differential signal after a pair of amplification by this first output VOUT+ and this second output VOUT-.In order to suppress common-mode gain, improve common-mode rejection ratio, make this operational amplification circuit and system works stable, when the common-mode voltage VCM that need to ensure in input differential signal changes, the electric current that flows through this first field effect transistor M1 and the electric current sum that flows through this second field effect transistor M2 equal to flow through the electric current of the 4th field effect transistor M4.
First the 5th field effect transistor M5 is set identical with the breadth length ratio of the 3rd field effect transistor M3, the breadth length ratio sum of this first field effect transistor M1 and this second field effect transistor M2 equals the breadth length ratio of the 4th field effect transistor M4, the grid voltage of the 5th field effect transistor M5 and the 3rd field effect transistor M3 is VB1, the drain voltage of the 3rd field effect transistor M3 is VB2, and the drain voltage of the 5th field effect transistor M5 is VB3.In the time that common-mode voltage VCM equals reference voltage VREF, voltage VB3 equals voltage VB2, flowing through the 3rd field effect transistor M3 equates completely with the electric current that flows through the 5th field effect transistor M5, can obtain voltage VP and equal voltage VN, the electric current of this first adjustable current source IP is in such cases set and equals the electric current of this second adjustable current source IN, now do not have extra electric current to inject the 3rd field effect transistor M3, the electric current that flows through the 4th field effect transistor M4 equals to flow through the electric current and the electric current sum that flows through this second field effect transistor M2 of this first field effect transistor M1.
In the time that common-mode voltage VCM is greater than reference voltage VREF, voltage VB2 can follow the rising of input voltage and raise, voltage VB2 is greater than voltage VB3, the 3rd field effect transistor M3 starts to occur channel modulation effect, the electric current that flows through the 3rd field effect transistor M3 can change along with the variation of drain-source voltage, has more electric current and flows through the 3rd field effect transistor M3.Because common-mode voltage VCM is greater than reference voltage VREF, after comparator C MP, voltage VP is less than voltage VN, when voltage VP be set be less than voltage VN, the electric current of this first adjustable current source IP is greater than the electric current of this second adjustable current source IN, this first adjustable current source IP can have more one part of current and flows through the 3rd field effect transistor M3, thereby balance out the channel modulation electric current of the 3rd field effect transistor M3, the electric current that flows through the electric current of the 4th field effect transistor M4 and flow through this first field effect transistor M1 is equated with the electric current sum that flows through this second field effect transistor M2.
In the time that common-mode voltage VCM is less than reference voltage VREF, voltage VB2 can follow the decline of input voltage and decline, voltage VB2 is less than voltage VB3, the 3rd field effect transistor M3 starts to occur channel modulation effect, the electric current that flows through the 3rd field effect transistor M3 can correspondingly reduce, because common-mode voltage VCM is less than reference voltage VREF, after comparator C MP, voltage VP is greater than voltage VN, when voltage VP be set be greater than voltage VN, the electric current of this first adjustable current source IP is less than the electric current of this second adjustable current source IN, this second adjustable current source IN can have more one part of current and flows through this first field effect transistor M1 and this second field effect transistor M2, thereby compensate the channel modulation electric current of the 3rd field effect transistor M3, the electric current that flows through the electric current of the 4th field effect transistor M4 and flow through this first field effect transistor M1 is equated with the electric current sum that flows through this second field effect transistor M2.
Suppose △ V=VCM-VREF, △ I=IP-IN, the gain of this comparator C MP is Av, voltage VP controls the coefficient that the coefficient of the first adjustable current source IP and voltage VN control the second adjustable current source IN and is gm, has:
VN―VP=Av*（VCM―VREF）=Av*△V；
Again because △ I=IP-IN=gm*(VN-VP)=Av* △ V*gm;
The 3rd field effect transistor M3, due to current increment △ I '=λ * (VB2-VB1) * I1 that channel modulation effect produces, make compensating effect best, must have △ I=△ I ', that is:
Av*△V*gm=λ*（VB2―VB1）*I1 （1）
Due to △ V=VCM-VREF=VB2-VB1, expression formula (1) can be written as:
Av*gm=λ*I1 （2）
Wherein λ is channel modulation coefficient, because the value of λ and bias current sources I1 is determined by physical circuit, therefore only need regulate the gain A v of comparator C MP and Current Control coefficient gm can make expression formula (2) set up.
If expression formula (2) set up, known for operational amplification circuit and system, whenever flow through the electric current that the P shown in Fig. 2 orders and all remain unchanged, the equivalent resistance infinity that P is ordered, due to common-mode gain
ACM=（RD）/((1/gm)+2*RP) （3）
Wherein RD=RD1=RD2, RP is the equivalent resistance that P is ordered, due to RP → ∞, ACM → 0, the common-mode gain of operation amplifier system is about 0;
Because ACMRR=is ADM/ACM, wherein ACMRR represents common-mode rejection ratio, and ADM represents difference mode gain, and known ACMRR has been improved greatly.
Operational amplification circuit of the present invention and system have effectively suppressed the channel modulation effect of the tail current of operational amplification circuit and system, the electric current that flows through this first field effect transistor M1 while changing with the common-mode voltage VCM ensureing at input signal and the electric current sum that flows through this second field effect transistor M2 equal to flow through the electric current of the 4th field effect transistor M4, thereby inhibition common-mode gain, improves common-mode rejection ratio; And in the situation that not using cascade, greatly improve common-mode rejection ratio, thereby saved voltage remaining, made it can be at operation at low power supply voltage.
Claims (5)
1. an operational amplification circuit, comprise a first input end, one second input, one first output and one second output, it is characterized in that: described operational amplification circuit also comprise one with described first input end, described the second input, described the first output and the connected control circuit of described the second output, one is connected with described control circuit for regulating the regulating circuit and of electric current of described control circuit to be connected with described control circuit and described regulating circuit for the biasing circuit of proper operation electric current is provided to described operational amplification circuit, described control circuit comprises first field effect transistor being connected with described first input end, one the second field effect transistor being connected with described the second input, one the 3rd field effect transistor being connected with described the first field effect transistor and described the second field effect transistor, one the first resistance being connected with described the first field effect transistor and second resistance being connected with described the second field effect transistor, described regulating circuit comprises a comparator, one the first adjustable current source being connected with described comparator, one the second adjustable current source being connected with described comparator and described the first adjustable current source, one the 3rd resistance being connected with described comparator and the 4th resistance being connected with described comparator, described biasing circuit comprises a bias current sources, one the 5th resistance being connected with described bias current sources, one the 4th field effect transistor being connected with described the 5th resistance and the 5th field effect transistor being connected with described the 4th field effect transistor, described the first adjustable current source is one the 6th field effect transistor, described the second adjustable current source is one the 7th field effect transistor, described comparator comprises one the 8th field effect transistor, one the 9th field effect transistor, one the tenth field effect transistor being connected with described the 8th field effect transistor, one the 11 field effect transistor being connected with described the 9th field effect transistor, one the 12 field effect transistor being connected with described the tenth field effect transistor and described the 11 field effect transistor, one the 13 field effect transistor being connected with described the 9th field effect transistor and the 14 field effect transistor being connected with described the 13 field effect transistor, the grid of the grid of described the 6th field effect transistor and described the 8th field effect transistor, the drain electrode of drain electrode and described the tenth field effect transistor is connected, described the 6th field effect transistor, the 8th field effect transistor, the source electrode of the 9th field effect transistor and the 13 field effect transistor is all connected with a power end, and the drain electrode of described the 6th field effect transistor, the drain electrode of the 7th field effect transistor, the drain electrode of the 3rd field effect transistor, the source electrode of the source electrode of the first field effect transistor and the second field effect transistor connects jointly, described the 7th grid of field effect transistor and the grid of described the 14 field effect transistor, the drain electrode of drain electrode and described the 13 field effect transistor is connected, the source ground of described the 7th field effect transistor, one end of described the 3rd resistance is connected with the grid of described the first field effect transistor, one end of described the 4th resistance is connected with the grid of described the second field effect transistor, the grid of described the 9th field effect transistor, drain electrode is connected with described the 11 drain electrode of field effect transistor and the grid of described the 13 field effect transistor, the grid of described the tenth field effect transistor is connected with the other end of described the 3rd resistance and the other end of described the 4th resistance, described the tenth source electrode of field effect transistor and the source electrode of described the 11 field effect transistor are connected the drain electrode of described the 12 field effect transistor jointly, the grid of described the 11 field effect transistor connects a reference voltage end, the grid of described the 12 field effect transistor is connected with biasing circuit, the source grounding of described the 12 field effect transistor and the 14 field effect transistor.
2. operational amplification circuit as claimed in claim 1, it is characterized in that: the grid of described the first field effect transistor is connected with one end of described first input end and described the 3rd resistance, the drain electrode of described the first field effect transistor is connected with one end and described second output of described the first resistance, the grid of described the second field effect transistor is connected with one end of described the second input and described the 4th resistance, and the drain electrode of described the second field effect transistor is connected with one end and described first output of described the second resistance.
3. operational amplification circuit as claimed in claim 2, it is characterized in that: the source electrode of described the first field effect transistor, the source electrode of described the second field effect transistor, the drain electrode of described the 3rd field effect transistor, the drain electrode of described the 6th field effect transistor and the drain electrode of described the 7th field effect transistor connect jointly, the grid of described the 3rd field effect transistor is connected with the drain electrode of one end of described the 5th resistance, described the 4th field effect transistor, described the 5th grid of field effect transistor and the grid of described the 12 field effect transistor, and the source electrode of described the 4th field effect transistor is connected with the drain electrode of described the 5th field effect transistor.
4. operational amplification circuit as claimed in claim 3, is characterized in that: the common reference voltage end that connects of grid of one end of described bias current sources, the other end of described the 5th resistance and described the 4th field effect transistor.
5. operational amplification circuit as claimed in claim 4, is characterized in that: a common power end, the source ground of described the 5th field effect transistor of connecting of the other end of the other end of described bias current sources, the other end of described the first resistance, described the second resistance.
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| CN103178788B (en) * | 2013-01-29 | 2016-05-04 | 嘉兴联星微电子有限公司 | A kind of low-noise amplifier biasing circuit of wide power voltage power supply |
| US8872685B2 (en) * | 2013-03-15 | 2014-10-28 | Qualcomm Incorporated | Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5321370A (en) * | 1992-05-14 | 1994-06-14 | Nec Corporation | Operational amplifier with common-mode feedback amplifier circuit |
| CN101106339A (en) * | 2007-06-18 | 2008-01-16 | 河南科技大学 | Ultrasonic motor closed loop control circuit |
| CN101651477A (en) * | 2009-09-04 | 2010-02-17 | 惠州市正源微电子有限公司 | Efficiency intensifying method of radio frequency power amplifiers and efficiency intensifying circuit thereof |
| CN201690419U (en) * | 2010-05-12 | 2010-12-29 | 四川和芯微电子股份有限公司 | Common mode feedback circuit |
| CN102075169A (en) * | 2011-03-03 | 2011-05-25 | 四川和芯微电子股份有限公司 | High speed comparator |
| CN201966873U (en) * | 2011-05-03 | 2011-09-07 | 四川和芯微电子股份有限公司 | Point of intersect moves down the circuit |
| CN202210783U (en) * | 2011-09-22 | 2012-05-02 | 四川和芯微电子股份有限公司 | Calculation amplifying circuit |
-
2011
- 2011-09-22 CN CN201110282437.5A patent/CN102386865B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5321370A (en) * | 1992-05-14 | 1994-06-14 | Nec Corporation | Operational amplifier with common-mode feedback amplifier circuit |
| CN101106339A (en) * | 2007-06-18 | 2008-01-16 | 河南科技大学 | Ultrasonic motor closed loop control circuit |
| CN101651477A (en) * | 2009-09-04 | 2010-02-17 | 惠州市正源微电子有限公司 | Efficiency intensifying method of radio frequency power amplifiers and efficiency intensifying circuit thereof |
| CN201690419U (en) * | 2010-05-12 | 2010-12-29 | 四川和芯微电子股份有限公司 | Common mode feedback circuit |
| CN102075169A (en) * | 2011-03-03 | 2011-05-25 | 四川和芯微电子股份有限公司 | High speed comparator |
| CN201966873U (en) * | 2011-05-03 | 2011-09-07 | 四川和芯微电子股份有限公司 | Point of intersect moves down the circuit |
| CN202210783U (en) * | 2011-09-22 | 2012-05-02 | 四川和芯微电子股份有限公司 | Calculation amplifying circuit |
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