CN102386087A - Improved construction method of metal front dielectric layer - Google Patents
Improved construction method of metal front dielectric layer Download PDFInfo
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- CN102386087A CN102386087A CN2010102726147A CN201010272614A CN102386087A CN 102386087 A CN102386087 A CN 102386087A CN 2010102726147 A CN2010102726147 A CN 2010102726147A CN 201010272614 A CN201010272614 A CN 201010272614A CN 102386087 A CN102386087 A CN 102386087A
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Abstract
The invention provides an improved construction method of a metal front dielectric layer. The improved construction method comprises the following steps of: manufacturing a silicon chip comprising a silicon substrate, wherein the upper surface of the silicon substrate is provided with a polycrystalline silicon gate, and the two sides of the polycrystalline silicon gate are provided with a source region and a drain region; depositing a contact etching stop layer on the upper surface of the silicon chip; using ultraviolet ray to irradiate the surface of a silicon nitride layer so as to further improve the tensile stress of the silicon nitride layer; introducing gas plasma rich in hydrogen into a reaction chamber where the silicon chip is put continuously for time T1, and introducing precursor gas containing silicon into the reaction chamber where the silicon chip is put continuously for time T2; and depositing the metal front dielectric layer on the upper surface of the silicon nitride layer. By the adoption of the scheme provided by the invention, the flatness of the metal front dielectric layer and the filling capability of the groove can be improved.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, particularly a kind of building method of improved before-metal medium layer.
Background technology
High depth is widely used in undersized preceding metal medium (PMD, Pre-Metal Dielectric) the trench fill process than technology (HARP, High Aspect Ratio Process).The medium of oxides layer that HARP forms has good trench fill ability and film quality, but regrettably, this medium of oxides layer is very high for the sensitiveness of growth substrates.
As shown in Figure 1 in the prior art to the building method of medium before the undersized metal, comprise the steps:
Step 101: process a silicon chip with following structure, this silicon chip comprises a silicon substrate, and the silicon substrate upper surface has polysilicon gate, and there are source area and drain region in the polysilicon gate both sides;
Step 102: in this silicon chip upper surface deposited silicon nitride layer as contact etch stop layer (ESL, Etch Stop Layer);
Step 103: with ultraviolet ray said silicon nitride layer surface is shone, in order to improve the tensile stress of silicon nitride layer;
Step 104: adopt HARP technology at the upper surface silicon oxide deposition film of said silicon nitride layer as PMD.This step is to adopt the method for chemical vapor deposition (CVD), in the CVD reative cell, feeds tetraethyl orthosilicic acid (TEOS, Tetraethyl Orthosilicate) gas and ozone (O
3) mist, under the normal condition, lower deposition speed and higher O
3/ TEOS ratio will obtain higher trench fill ability.
HARP PMD technology comprised for two steps: first step silicon oxide deposition is to the trench fill of accomplishing silicon chip surface; Second step was the thickness that further increases silicon oxide film, formed smooth silicon oxide film surface, so that the processing of subsequent technique.
Silicon nitride with high tensile stress can improve the mobility of electronics, and this electricity performance for small size device has crucial effects.Simultaneously, high tensile stress silicon nitride also plays a part very important as metal front insulation layer (PMD) etching stopping layer.
Yet, adopt the silicon chip that obtains after the above-mentioned technology of sem observation to find, be deposited to the quality+minute bad luck of the silicon oxide film of silicon nitride surface: the phenomenon that serious height rises and falls appears in the silicon oxide film surface; And, the phenomenon in " cavity " also appears between silicon oxide film and silicon nitride layer.
This explanation; In the building method of medium, adopt the flatness and the trench fill ability silicon oxide film surperficial of the silicon oxide layer of HARP technology deposit that decline is significantly all arranged on high tensile stress silicon nitride layer surface before the small sized metallic of prior art with respect to the silicon nitride layer that is deposited to common tensile stress.
Summary of the invention
The invention provides a kind of building method of improved before-metal medium layer, can greatly improve the quality and the trench fill ability that adopt HARP technology metals deposited front medium layer.
The embodiment of the invention has proposed a kind of building method of improved before-metal medium layer, comprises the steps:
Process a silicon chip that comprises silicon substrate, the silicon substrate upper surface has polysilicon gate, and there are source area and drain region in the polysilicon gate both sides;
At this silicon chip upper surface deposition contact etch stop layer;
With ultraviolet ray said silicon nitride layer surface is shone, further improved the tensile stress of silicon nitride layer;
In the reative cell at silicon chip place, feed the gaseous plasma that is rich in protium, the duration is T1;
In the reative cell at silicon chip place, feed the precursor gas that contains silicon, the duration is T2;
Upper surface depositing metal front medium layer at said silicon nitride layer.
Preferably, said contact etch stop layer is the silicon nitride film with tensile stress.
Preferably, said before-metal medium layer is a silicon oxide film.
Preferably, the technology of depositing metal front medium layer employing is that high depth is than HARP technology.
Preferably, the said gas that is rich in protium is ammonia NH
3
Preferably, the flow of feeding ammonia is 5000sccm to 20000sccm in said reative cell.
Preferably, said T1 is 20 seconds to 40 seconds.
Preferably, in the reative cell at silicon chip place, feeding in the process of the gaseous plasma that is rich in protium, the temperature of silicon chip place reative cell remains on 400 degrees centigrade to 480 degrees centigrade, and pressure is that 1 holder is to 7 holders.
Preferably, the said precursor gas that contains silicon is tetraethyl orthosilicic acid TEOS steam.
Preferably, the flow of said TEOS steam is that 0.2 gram is to 0.6 gram/minute.
Preferably, said T2 is 10 seconds to 20 seconds.
Preferably; In the said process that in the reative cell at silicon chip place, feeds the precursor gas that contains silicon; The temperature of silicon chip place reative cell remains on 400 degrees centigrade to 480 degrees centigrade, pressure be 300 holders to 600 holders, the flow of carrier gas is 1000sccm to 6000sccm.
Can find out from above technical scheme, adopt the gaseous plasma that is rich in protium that silicon chip surface is handled,, not reduce the tensile stress at silicon nitride layer interface though make the hydrogen atom content on silicon nitride layer surface increase.Silicon chip surface with sem observation embodiment of the invention PROCESS FOR TREATMENT obtains finds that with respect to prior art, the flatness of silicon oxide film increases greatly, and does not observe tangible cavity, shows that the trench fill ability also strengthens greatly.
Description of drawings
Fig. 1 is the building method sketch map of the preceding medium of metal of prior art;
Fig. 2 is the sketch map that is rich in the silicon nitride layer interface adhesion TEOS molecule of hydrogen;
Fig. 3 is the building method sketch map of the preceding medium of metal of the embodiment of the invention.
Embodiment
The inventor adopts after the ultraviolet irradiation silicon nitride layer through researching and analysing discovery, and the hydrogen atom on silicon nitride layer surface is eliminated basically fully.So, precursor TEOS molecule is difficult to stick on the silicon nitride surface through forming the H key, and the silica that therefore forms through CVD also is difficult to fit tightly with silicon nitride surface, and this is the major reason that influences the trench fill ability.
The present invention program mainly improves the quality of silicon oxide film from following two aspects: first aspect is to improve the hydrophily of silicon nitride interface; Second aspect is to improve the nucleation ability of TEOS.
For first aspect, the present invention adopts the plasma of the gas formation of being rich in hydrogen that silicon nitride surface is handled, to improve the hydrophily (polarity) of silicon nitride surface.Silicon nitride layer surface after the processing is as shown in Figure 2, and the nitrogen-atoms at the interface (N) of silicon nitride layer 201 combines through the Si-H key with silicon atom (Si).Nitrogen-atoms is in undersaturated condition, therefore can catch hydrogen atom (H) and form the N-H key.The form of TEOS molecule 202 is that a silicon atom (Si) connects four oxygen atoms (O) through the Si-O key, and each oxygen atom connects an ethyl (Et).The electronegativity of said oxygen atom is very strong, and the electronics of the hydrogen atom that silicon nitride surface is caught is attracted by nitrogen-atoms strongly, so this hydrogen atom has stronger electropositivity.Therefore said hydrogen atom and oxygen atom make the TEOS molecule sticked to the surface of silicon nitride layer under the effect that positive negative is inhaled.
For second aspect, the present invention improves the technology of silicon oxide deposition, at first in reative cell, feeds the TEOS steam, and guaranteeing has abundant precursor TEOS molecule to be sticked to silicon nitride surface equably; And then in reative cell, add ozone or helium etc., carry out the deposition process of silica.
The building method of the before-metal medium layer that the embodiment of the invention proposes is as shown in Figure 3, comprises the steps:
Step 301: process a silicon chip with following structure, this silicon chip comprises a silicon substrate, and the silicon substrate upper surface has polysilicon gate, and there are source area and drain region in the polysilicon gate both sides.
Step 302: at the silicon nitride film of this silicon chip upper surface deposition tensile stress as contact etch stop layer.
Step 303: with ultraviolet ray said silicon nitride layer surface is shone, further improved the tensile stress of silicon nitride layer;
Step 304: in the reative cell at silicon chip place, feed ammonia (NH
3) plasma.Ammonia ionization forms the hydrogen of free state, is caught by the silicon nitride layer surface, makes the hydrophily on silicon nitride layer surface strengthen greatly.
The flow of the ammonia that the embodiment of the invention adopts is 5000sccm to 20000sccm, and the duration is 20 seconds to 40 seconds.The temperature of silicon chip place reative cell remains on 400 degrees centigrade to 480 degrees centigrade, and pressure is that 1 holder is to 7 holders.
In other replacement schemes, can adopt the gas that hydrogen or other are rich in protium to replace ammonia.
Step 305: precursor key and process.In the reative cell at silicon chip place, feed the precursor gas that contains silicon.
Preferably, the said precursor gas that contains silicon is tetraethyl orthosilicic acid TEOS steam, and flow is that 0.2 gram is to 0.6 gram/minute.The TEOS steam is taken to silicon chip surface by carrier gas (being generally nitrogen) from the reative cell entrance area, the TEOS molecule is fully sticked to have higher hydrophilic silicon nitride layer surface.The duration of this process is 10 seconds to 20 seconds.The temperature of silicon chip place reative cell remains on 400 degrees centigrade to 480 degrees centigrade, and pressure is that 300 holders are to 600 holders.The flow of carrier gas is 1000sccm to 6000sccm.
Step 306: adopt HARP technology at the upper surface silicon oxide deposition film of said silicon nitride layer as PMD.This step is identical with step 104 among Fig. 1.
Wherein, the processing of step 304 though make the hydrogen atom content on silicon nitride layer surface increase, does not reduce the tensile stress at silicon nitride layer interface.Silicon chip surface with sem observation embodiment of the invention PROCESS FOR TREATMENT obtains finds that with respect to prior art, the flatness of silicon oxide film increases greatly, and does not observe tangible cavity, shows that the trench fill ability also strengthens greatly.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (12)
1. the building method of an improved before-metal medium layer is characterized in that, comprises the steps:
Process a silicon chip that comprises silicon substrate, the silicon substrate upper surface has polysilicon gate, and there are source area and drain region in the polysilicon gate both sides;
At this silicon chip upper surface deposition contact etch stop layer;
With ultraviolet ray said silicon nitride layer surface is shone, further improved the tensile stress of silicon nitride layer;
In the reative cell at silicon chip place, feed the gaseous plasma that is rich in protium, the duration is T1;
In the reative cell at silicon chip place, feed the precursor gas that contains silicon, the duration is T2;
Upper surface depositing metal front medium layer at said silicon nitride layer.
2. method according to claim 1 is characterized in that, said contact etch stop layer is the silicon nitride film with tensile stress.
3. method according to claim 2 is characterized in that, said before-metal medium layer is a silicon oxide film.
4. method according to claim 3 is characterized in that, the technology that the depositing metal front medium layer adopts is that high depth is than HARP technology.
5. method according to claim 4 is characterized in that, the said gas that is rich in protium is ammonia NH3.
6. method according to claim 5 is characterized in that, the flow that in said reative cell, feeds ammonia is 5000sccm to 20000sccm.
7. method according to claim 5 is characterized in that, said T1 is 20 seconds to 40 seconds.
8. method according to claim 7 is characterized in that, in the reative cell at silicon chip place, is feeding in the process of the gaseous plasma that is rich in protium, and the temperature of silicon chip place reative cell remains on 400 degrees centigrade to 480 degrees centigrade, and pressure is that 1 holder is to 7 holders.
9. method according to claim 4 is characterized in that, the said precursor gas that contains silicon is tetraethyl orthosilicic acid TEOS steam.
10. method according to claim 9 is characterized in that, the flow of said TEOS steam is that 0.2 gram is to 0.6 gram/minute.
11. method according to claim 10 is characterized in that, said T2 is 10 seconds to 20 seconds.
12. method according to claim 11; It is characterized in that; In the said process that in the reative cell at silicon chip place, feeds the precursor gas that contains silicon; The temperature of silicon chip place reative cell remains on 400 degrees centigrade to 480 degrees centigrade, pressure be 300 holders to 600 holders, the flow of carrier gas is 1000sccm to 6000sccm.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030124873A1 (en) * | 2001-12-28 | 2003-07-03 | Guangcai Xing | Method of annealing an oxide film |
| US20040012048A1 (en) * | 2002-07-18 | 2004-01-22 | Hynix Semiconductor Inc. | Gate structure in flash memory cell and method of forming the same, and method of forming dielectric film |
| US20090283874A1 (en) * | 2008-05-15 | 2009-11-19 | Toshiaki Idaka | Semiconductor device manufacturing method and semiconductor device |
| US20100012991A1 (en) * | 2007-03-27 | 2010-01-21 | Fujitsu Microelectronics Limited | Semiconductor device and method for fabricating semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030124873A1 (en) * | 2001-12-28 | 2003-07-03 | Guangcai Xing | Method of annealing an oxide film |
| US20040012048A1 (en) * | 2002-07-18 | 2004-01-22 | Hynix Semiconductor Inc. | Gate structure in flash memory cell and method of forming the same, and method of forming dielectric film |
| US20100012991A1 (en) * | 2007-03-27 | 2010-01-21 | Fujitsu Microelectronics Limited | Semiconductor device and method for fabricating semiconductor device |
| US20090283874A1 (en) * | 2008-05-15 | 2009-11-19 | Toshiaki Idaka | Semiconductor device manufacturing method and semiconductor device |
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