CN102376655A - Chip packaging structure with metal layer - Google Patents
Chip packaging structure with metal layer Download PDFInfo
- Publication number
- CN102376655A CN102376655A CN2011103400337A CN201110340033A CN102376655A CN 102376655 A CN102376655 A CN 102376655A CN 2011103400337 A CN2011103400337 A CN 2011103400337A CN 201110340033 A CN201110340033 A CN 201110340033A CN 102376655 A CN102376655 A CN 102376655A
- Authority
- CN
- China
- Prior art keywords
- chip
- packaging structure
- metal level
- effective coverage
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention aims at providing a chip packaging structure. The chip packaging structure comprises a substrate, a chip, a metal layer and a plastic packaging material, wherein the chip is arranged on the substrate, the metal layer is arranged on a non-effective region surface of the chip, and the plastic package material comprises the chip is used for packing the chip. According to the chip packaging structure of the invention, compared with the heat emission performance of the traditional chip packaging structure, the heat dissipation performance of the chip packaging structure is increased by arranging the metal layer on the non-effective region surface of the chip.
Description
Technical field
The present invention relates to a kind of chip-packaging structure, more particularly, thereby the present invention relates to a kind ofly on the non-effective coverage face that is not electrically connected with the outside of chip, have the chip-packaging structure that metal level has excellent heat dispersion performance with metal level.
Background technology
Along with the develop rapidly of semiconductor industry and to the rapid permeability of every profession and trade; Electronic Packaging has progressively become a bottleneck realizing the semiconductor chip function; Therefore Electronic Packaging has obtained huge development at nearly twenty or thirty in year, and has obtained significant progress.
Present Electronic Packaging not only will provide the chip protection, also will when controlling cost, satisfy performances such as ever-increasing function, reliability, thermal diffusivity.The design of Electronic Packaging and manufacturing are just becoming more and more important to system applies, and the design of Electronic Packaging and manufacturing need be started with to obtain the best ratio of performance to price from system from the beginning.
The actuating force of Electronic Packaging development is mainly derived from the development and the market demand of semiconductor chip, may be summarized to be following some: the increase of speed and disposal ability needs more pins number, clock frequency and better power distribution faster.The market demand electronic product has greater functionality, longer battery life and littler physical dimension.The requirement of electronic device and electronic product constantly increases, and new device continues to bring out.Market competition is increasingly sharpened, the development of manufacture of microchips and the market demand of electronic product with the developing trend of final decision Electronic Packaging in littler, thinner, lighter, with better function, energy consumption is littler, better reliability, more compliance with environmental protection requirements, cheapness etc. more.
The consumer expects that electronic product is all compact in every respect, and this also is the major impetus that electronic product dwindles day by day.So enterprise is constantly dwindling the overall dimension of end product, and this will utilize less semiconductor packages to realize.Therefore, dwindling encapsulation is a main development trend of semiconductor packages industry.
Various packing forms in using now mainly comprise individual layer, bilayer or sandwich construction more, and encapsulating structure comprises metal lead wire, the inner cabling of realizing electric interconnection and provides support the substrate of single or a plurality of chips and chip is provided and the glue/film of substrate adhesion and plastic cement.In existing encapsulating structure, stacked package is a kind of good way that realizes microminiaturization with high integration degree.In stacked package, it is more and more important to Packaging Industry that encapsulation (PoP) is gone up in encapsulation (PiP) and encapsulation in the encapsulation, because this technology can be piled up highdensity equipment.The PoP product has encapsulation more than two, and a top that is encapsulated in another combines their encapsulation with soldered ball.This encapsulation is integrated in logic and memory component respectively in the different encapsulation.For example, mobile phone just adopts the PoP encapsulation to come integrated application processor and memory usually.
Though existing encapsulating structure size is less and packaging density is higher, also produced some problems thus, particularly in the PoP encapsulation, heat dissipation problem is especially outstanding.
Summary of the invention
The object of the present invention is to provide a kind of chip-packaging structure, said chip-packaging structure comprises: substrate; Chip is arranged on above the substrate; Metal level is arranged on the non-effective coverage face of chip; Plastic packaging material is sealed said chip.Here; The effective coverage face of chip is defined as the realization of chip and the surface that electric interconnection (for example carrying out electric interconnection through go between bonding or solder joint and outside) carried out in the outside; And with the another side of chip, that is, the surface of not carrying out electric interconnection with the outside is defined as non-effective coverage face.
According to chip-packaging structure of the present invention, it is characterized in that said metal level covers a part or non-effective coverage face whole of the non-effective coverage face of chip.
According to chip-packaging structure of the present invention, it is characterized in that said metal level is plated on the non-effective coverage face of chip through plating.
According to chip-packaging structure of the present invention, it is characterized in that, said chip-packaging structure also comprise the lead-in wire that the effective coverage face with chip is electrically connected with substrate and be arranged on said metal level and said substrate between nonconductive adhesive.
According to chip-packaging structure of the present invention, it is characterized in that said chip-packaging structure also comprises the solder joint that the effective coverage face with chip is electrically connected with substrate, said metal level is exposed to the outside of plastic packaging material.
According to chip-packaging structure of the present invention, through metal plating layer on the face of the non-effective coverage of chip, thereby compare with traditional chip-packaging structure, improved the heat dispersion of encapsulating structure.
Description of drawings
Through the description of exemplary embodiment of the present invention being carried out below in conjunction with accompanying drawing, above-mentioned and other purposes of the present invention and characteristics will become apparent, wherein:
Fig. 1 is the diagrammatic sketch that schematically shows the chip-packaging structure of existing employing lead-in wire bonding (wire bonding);
Fig. 2 is the diagrammatic sketch that schematically shows the chip-packaging structure of existing employing flip-chip (F1ip Chip);
Fig. 3 is the diagrammatic sketch that schematically shows the chip-packaging structure with metal level that adopts the lead-in wire bonding according to an exemplary embodiment of the present invention;
Fig. 4 is the diagrammatic sketch that schematically shows the PoP structure of the chip-packaging structure with metal level that adopts the lead-in wire bonding according to an exemplary embodiment of the present invention;
Fig. 5 is the diagrammatic sketch that schematically shows the chip-packaging structure with metal level that adopts flip-chip according to an exemplary embodiment of the present invention;
Fig. 6 is the diagrammatic sketch that schematically shows the PoP structure of the chip-packaging structure with metal level that adopts flip-chip according to an exemplary embodiment of the present invention.
Embodiment
Hereinafter, will describe exemplary embodiment of the present invention in detail with reference to accompanying drawing.Yet the present invention can implement with many different forms, and should not be limited to the exemplary embodiment of setting forth here.On the contrary, provide these exemplary embodiments to make that the disclosure will be thorough and complete, and can convey to those skilled in the art to the scope of exemplary embodiment fully.For the sake of clarity, possibly exaggerate the size and the relative size in layer and zone in the accompanying drawings.In addition, in the accompanying drawings, same or analogous label can be represented same or analogous element.
Fig. 1 is the diagrammatic sketch that schematically shows the chip-packaging structure of existing employing lead-in wire bonding (wire bonding).
With reference to Fig. 1; In the chip-packaging structure of existing employing lead-in wire bonding; Chip 1 is arranged on the substrate 2, and plastic packaging material 3 encapsulate chip 1 are avoided the influence of external environment condition to protect chip 1, and chip 1 is realized and outside being electrically connected through metal lead wire 7 and soldered ball 5 from its effective coverage face.
Fig. 2 is the diagrammatic sketch that schematically shows the chip-packaging structure of existing employing flip-chip (Flip Chip).
With reference to Fig. 2; In the chip-packaging structure of existing employing flip-chip; Chip 1 is arranged on the substrate 2, and plastic packaging material 3 encapsulate chip 1 are avoided the influence of external environment condition to protect chip 1, and chip 1 is realized and outside being electrically connected through solder joint 8 and soldered ball 5 from its effective coverage face.
Fig. 3 is the diagrammatic sketch that schematically shows the chip-packaging structure with metal level that adopts the lead-in wire bonding according to an exemplary embodiment of the present invention, and Fig. 4 is the diagrammatic sketch that schematically shows the PoP structure of the chip-packaging structure with metal level that adopts the lead-in wire bonding according to an exemplary embodiment of the present invention.
With reference to Fig. 3, can comprise according to the chip-packaging structure with metal level of the employing of exemplary embodiment of the present invention lead-in wire bonding: substrate 2; Chip 1 is arranged on above the substrate 2; Metal level 6 is arranged on the non-effective coverage face of chip 1; Plastic packaging material 3 is sealed said chip 1, avoids the influence of external environment condition to protect chip 1, and chip 1 is realized and outside being electrically connected through metal lead wire 7 and soldered ball 5 from its effective coverage face.Said chip-packaging structure also can comprise the nonconductive adhesive 4 that is arranged between said metal level 6 and the said substrate 2, so that said metal level 6 is combined with said substrate 2.Said metal level 6 can cover a part or non-effective coverage face whole of the non-effective coverage face of chip 1.Said metal level 6 can be plated on the non-effective coverage face of chip 1 through plating.
With reference to Fig. 4, can will pile up (for example, can pile up bilayer or multi-layer package structure more) through soldered ball according to the chip-packaging structure with metal level 6 of the employing of exemplary embodiment of the present invention lead-in wire bonding, to form the PoP structure.Shown in Fig. 4 is the structure that Flip-Chip Using part and the chip package with metal level 6 that adopts the lead-in wire bonding pile up; Yet, the invention is not restricted to this, for example; Can the chip package with metal level 6 of employing lead-in wire bonding double-deck or more multilayer be piled up, thereby form the PoP structure.In addition; Do not have the metal level that is used to dispel the heat in the Flip-Chip Using part on the chip package that adopts the lead-in wire bonding shown in Fig. 4 with metal level 6; Yet, the invention is not restricted to this, for example; Can comprise the metal level that is used to dispel the heat that is formed on the chip in the Flip-Chip Using part on the chip package that adopts the lead-in wire bonding, thereby improve the heat dispersion of chip-packaging structure with metal level 6.
Fig. 5 is the diagrammatic sketch that schematically shows the chip-packaging structure with metal level that adopts flip-chip according to an exemplary embodiment of the present invention; Fig. 6 is the diagrammatic sketch that schematically shows the PoP structure of the chip-packaging structure with metal level that adopts flip-chip according to an exemplary embodiment of the present invention.
With reference to Fig. 5, can comprise according to the chip-packaging structure with metal level of the employing flip-chip of exemplary embodiment of the present invention: substrate 2; Chip 1 is arranged on above the substrate 2; Metal level 6 is arranged on the non-effective coverage face of chip 1; Plastic packaging material 3 is sealed said chip 1, avoids the influence of external environment condition with protection chip 1.Here, when using 3 pairs of chips 1 of plastic packaging material to seal, can make metal level 6 be exposed to the outside, thereby compare with traditional encapsulating structure, chip-packaging structure according to the present invention has heat dispersion preferably.Said metal level 6 can cover a part or non-effective coverage face whole of the non-effective coverage face of chip.Said metal level 6 can be plated on the non-effective coverage face of chip 1 through plating.Also can comprise the effective coverage face that is arranged on chip 1 and the solder joint 8 between the substrate 2 according to the chip-packaging structure with metal level 6 of the employing flip-chip of exemplary embodiment of the present invention, thereby realize chips 1 and outside being electrically connected through solder joint 8 and soldered ball 5.
With reference to Fig. 6; When with double-deck or when more multilayer is piled up according to the chip package with metal level 6 of the employing flip-chip of exemplary embodiment of the present invention; Can wait them to pile up through soldered ball and nonconductive adhesive 9 (for example hot epoxy resin), to form the PoP structure.As shown in Figure 6, last packaging part also can comprise the metal level that is used to dispel the heat.In addition, can chip package with metal level 6 and the other forms of chip-packaging structure according to the employing flip-chip of exemplary embodiment of the present invention be piled up, to form the PoP structure.
In the packaging part, plastic packaging material has covered the metal level that is used to dispel the heat that is arranged on the chip on shown in Fig. 6, yet; The invention is not restricted to this; For example, the metal level that can be used in heat radiation exposes, and utilizes soldered ball and nonconductive adhesive 9 (for example hot epoxy resin) etc. to carry out multiple-level stack.
According to chip-packaging structure of the present invention, through metal plating layer on the face of the non-effective coverage of chip, thereby compare with traditional chip-packaging structure, improved the heat dispersion of encapsulating structure.
Though illustrated and described the example of exemplary embodiment of the present invention; But what those skilled in the art should understand that is; Exemplary embodiment of the present invention is not limited thereto; Do not breaking away under the situation of the spirit and scope of the present invention that limit like claim, can carry out various modifications exemplary embodiment of the present invention.
Claims (5)
1. chip-packaging structure, said chip-packaging structure comprises:
Substrate;
Chip is arranged on above the substrate;
Metal level is arranged on the non-effective coverage face of chip;
Plastic packaging material is sealed said chip.
2. chip-packaging structure according to claim 1 is characterized in that, said metal level covers a part or non-effective coverage face whole of the non-effective coverage face of chip.
3. chip-packaging structure according to claim 1 is characterized in that, said metal level is plated on the non-effective coverage face of chip through plating.
4. chip-packaging structure according to claim 1 is characterized in that, said chip-packaging structure also comprise the lead-in wire that the effective coverage face with chip is electrically connected with substrate and be arranged on said metal level and said substrate between nonconductive adhesive.
5. chip-packaging structure according to claim 1 is characterized in that, said chip-packaging structure also comprises the solder joint that the effective coverage face with chip is electrically connected with substrate, and said metal level is exposed to the outside of plastic packaging material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103400337A CN102376655A (en) | 2011-10-28 | 2011-10-28 | Chip packaging structure with metal layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103400337A CN102376655A (en) | 2011-10-28 | 2011-10-28 | Chip packaging structure with metal layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102376655A true CN102376655A (en) | 2012-03-14 |
Family
ID=45795037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103400337A Pending CN102376655A (en) | 2011-10-28 | 2011-10-28 | Chip packaging structure with metal layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102376655A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109916744A (en) * | 2019-04-18 | 2019-06-21 | 广东工业大学 | A kind of detection method and equipment of solder joint and substrate tensile strength |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075648A (en) * | 2006-05-17 | 2007-11-21 | 百鸣科技有限公司 | Method for radiating, packing and forming light-emitting diodes |
| CN101562138A (en) * | 2008-04-16 | 2009-10-21 | 矽品精密工业股份有限公司 | Method for producing semiconductor packaging part |
| CN101629707A (en) * | 2009-08-05 | 2010-01-20 | 深圳雷曼光电科技有限公司 | LED lamp and encapsulating method thereof |
| CN101752338A (en) * | 2008-12-11 | 2010-06-23 | 三星电子株式会社 | Ball grid array encapsulating structure and encapsulating process thereof |
| CN201655787U (en) * | 2010-04-06 | 2010-11-24 | 三星半导体(中国)研究开发有限公司 | Semiconductor encapsulation structure |
-
2011
- 2011-10-28 CN CN2011103400337A patent/CN102376655A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101075648A (en) * | 2006-05-17 | 2007-11-21 | 百鸣科技有限公司 | Method for radiating, packing and forming light-emitting diodes |
| CN101562138A (en) * | 2008-04-16 | 2009-10-21 | 矽品精密工业股份有限公司 | Method for producing semiconductor packaging part |
| CN101752338A (en) * | 2008-12-11 | 2010-06-23 | 三星电子株式会社 | Ball grid array encapsulating structure and encapsulating process thereof |
| CN101629707A (en) * | 2009-08-05 | 2010-01-20 | 深圳雷曼光电科技有限公司 | LED lamp and encapsulating method thereof |
| CN201655787U (en) * | 2010-04-06 | 2010-11-24 | 三星半导体(中国)研究开发有限公司 | Semiconductor encapsulation structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109916744A (en) * | 2019-04-18 | 2019-06-21 | 广东工业大学 | A kind of detection method and equipment of solder joint and substrate tensile strength |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI442541B (en) | Stackable multi-chip package system with support structure | |
| US8183687B2 (en) | Interposer for die stacking in semiconductor packages and the method of making the same | |
| US20090085185A1 (en) | Stack-type semiconductor package, method of forming the same and electronic system including the same | |
| KR101668444B1 (en) | Multi-chip package having frame interposer | |
| US20150028474A1 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| KR20140130920A (en) | Package on package device and method of fabricating the device | |
| KR20150054551A (en) | Semiconductor chip and semiconductor package comprising the same | |
| CN101436590A (en) | Package-on-package with improved joint reliability | |
| TW201227913A (en) | Three-dimensional system-in-package package-on-package structure | |
| US20160035698A1 (en) | Stack package | |
| US20080237833A1 (en) | Multi-chip semiconductor package structure | |
| KR20150059068A (en) | Semiconductor package | |
| US20070052082A1 (en) | Multi-chip package structure | |
| CN102693965A (en) | Package-on-package structure | |
| US9082634B2 (en) | Stack package and method for manufacturing the same | |
| US9087883B2 (en) | Method and apparatus for stacked semiconductor chips | |
| JP2007250916A (en) | Semiconductor device and manufacturing method therefor | |
| US20080237831A1 (en) | Multi-chip semiconductor package structure | |
| US11552051B2 (en) | Electronic device package | |
| CN102376655A (en) | Chip packaging structure with metal layer | |
| CN114843238A (en) | Packaging structure, electronic device and packaging method | |
| CN111128918B (en) | Chip packaging method and chip | |
| CN102543910A (en) | Chip packaging component and manufacturing method thereof | |
| CN103050454A (en) | Package on package structure | |
| CN108630626A (en) | Without substrate encapsulation structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120314 |