CN102376597A - Dual-damascene structure and manufacturing method thereof - Google Patents
Dual-damascene structure and manufacturing method thereof Download PDFInfo
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- CN102376597A CN102376597A CN201010261552XA CN201010261552A CN102376597A CN 102376597 A CN102376597 A CN 102376597A CN 201010261552X A CN201010261552X A CN 201010261552XA CN 201010261552 A CN201010261552 A CN 201010261552A CN 102376597 A CN102376597 A CN 102376597A
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Abstract
The invention discloses a dual-damascene structure and a manufacturing method thereof. The manufacturing method for the dual-damascene structure comprises the following steps: providing a semiconductor substrate, and forming a first low-dielectric constant dielectric layer on the semiconductor substrate and forming a trench and a through hole in the first low-dielectric constant dielectric layer; respectively forming metal materials on the first low-dielectric constant dielectric layer and in the trench and the through hole; removing the metal materials on the first low-dielectric constant dielectric layer by utilizing a chemical and mechanical lapping process, and forming a partially damaged first dielectric layer on the surface of the first low-dielectric constant dielectric layer by the chemical and mechanical lapping process; removing the damaged first dielectric layer; and forming a second low-dielectric constant dielectric layer on the remaining first low-dielectric constant dielectric layer. The dual-damascene structure disclosed by the invention can prevent the damaged first dielectric layer from generating adverse effects on the performances of subsequently formed metal interconnection lines and is beneficial to improving the reliability of semiconductor devices.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of dual-damascene structure and manufacturing approach thereof.
Background technology
At present, the manufacturing technology develop rapidly of semiconductor device, semiconductor device has had the deep-submicron structure, comprises the semiconductor element of enormous quantity in the integrated circuit.Along with further developing of fabricate technology, the high-performance between the semiconductor device, high density connect not only carries out in single interconnection layer, and will between multilayer, interconnect.Therefore, multilayer interconnect structure is provided usually, wherein a plurality of interconnection layers pile up mutually, and dielectric layer places therebetween, are used to connect semiconductor device.The multilayer interconnect structure that particularly utilizes dual damascene (dual-damascene) technology to form, it forms through hole (via) and groove (trench) in advance in dielectric layer, fill said through hole and groove with electric conducting material then.The boost device reliability because the restriction that dual-damascene structure can be avoided aliasing error and solve existing smithcraft, dual-damascene technics just are widely used in the semiconductor fabrication process.
As a rule, dielectric constant (k) value is lower than 3.0 dielectric film and is called patterns of low dielectric constant film by semiconductor manufacturing industry.In order to reduce the parasitic capacitance between the metal interconnecting wires, reduce the RC delay of signal and the interference between the metal interconnecting wires, generally adopt the dielectric layer of low-k (low k) material at present as dual-damascene structure.Detailed, please refer to Figure 1A～1D, it is the generalized section of each step corresponding construction of existing double mosaic structure manufacture method.
Shown in Figure 1A, at first, Semiconductor substrate 100 is provided, be formed with metal wiring layer 101 in the said Semiconductor substrate 100, the material of said metal wiring layer 101 can be in aluminium, silver, the copper one or several.
Shown in Figure 1B; Then; On said Semiconductor substrate 100, form low dielectric coefficient medium layer 110; And in said low dielectric coefficient medium layer 110, form groove (trench) 110b and through hole (via) 110a, and the position of said groove 110b is corresponding with the position of through hole 110a, and the cross-sectional width of said groove 110b is greater than the cross-sectional width of through hole 110a.About the more information of groove and through hole formation method, can be 200610026758.8 one Chinese patent application referring to application number.
Shown in Fig. 1 C, subsequently, form metal material 120 on low dielectric coefficient medium layer 110 and in said groove 110b and the through hole 110a, the material of said metal material 120 for example is a metallic copper.
Shown in Fig. 1 D, then, utilize chemical mechanical milling tech to remove the metal material 120 on the said low dielectric coefficient medium layer 110, to form dual-damascene structure.
Yet; In actual production, find; Because the density of said low dielectric coefficient medium layer 110 is lower, when utilizing chemical mechanical milling tech to remove the metal material on the low dielectric coefficient medium layer 110, the employed lapping liquid of said chemical mechanical milling tech (slurry) can react with the surface of said low dielectric coefficient medium layer 110; Make the low dielectric coefficient medium layer of segment thickness be damaged; Cause the dielectric constant of low dielectric coefficient medium layer to change, the performance of the metal interconnecting wires of follow-up formation is had a negative impact, and then influence the reliability of semiconductor device.
Summary of the invention
The present invention provides a kind of double mosaic structure manufacture method, changes with the dielectric constant that prevents low dielectric coefficient medium layer, improves the reliability of semiconductor device.
For solving the problems of the technologies described above; The present invention provides a kind of double mosaic structure manufacture method; Comprise: Semiconductor substrate is provided, is formed with first low dielectric coefficient medium layer on the said Semiconductor substrate and is formed at groove and the through hole in said first low dielectric coefficient medium layer; On said first low dielectric coefficient medium layer and in groove and the through hole, form metal material; Utilize chemical mechanical milling tech to remove the metal material on first low dielectric coefficient medium layer, this chemical mechanical milling tech forms first dielectric layer of part damage on first low dielectric coefficient medium layer surface; Remove first dielectric layer of said damage; On remaining first low dielectric coefficient medium layer, form second low dielectric coefficient medium layer.
Optional, in said double mosaic structure manufacture method, first dielectric layer of said damage utilizes wet-etching technology to remove.
Optional, in said double mosaic structure manufacture method, the material of said first low dielectric coefficient medium layer is a kind of or its combination in the carborundum of silica or nitrating of the silica of mixing fluorine, carbon dope.
Optional, in said double mosaic structure manufacture method, the employed etching liquid of said wet-etching technology is the hydrofluoric acid of dilution.
Optional, in said double mosaic structure manufacture method, the etch period of said wet-etching technology is 10 seconds～600 seconds.
Optional, in said double mosaic structure manufacture method, the thickness of said second low dielectric coefficient medium layer is more than or equal to the thickness of first dielectric layer of said damage.
Optional; In said double mosaic structure manufacture method, the thickness of first dielectric layer of said damage be
said second low dielectric coefficient medium layer thickness is
Optional, in said double mosaic structure manufacture method, remove after first dielectric layer of said damage, also comprise: unmarred first dielectric layer of removing segment thickness.
Optional, in said double mosaic structure manufacture method, the material of said second low dielectric coefficient medium layer is a kind of or its combination in the carborundum of silica or nitrating of the silica of mixing fluorine, carbon dope.
Optional, in said double mosaic structure manufacture method, said second low dielectric coefficient medium layer is to utilize the mode of chemical vapour deposition (CVD) to form.
Optional, in said double mosaic structure manufacture method, the material of said second low dielectric coefficient medium layer is an organic polymer.
Optional, in said double mosaic structure manufacture method, said second low dielectric coefficient medium layer utilizes the spin coating mode to form.
Optional, in said double mosaic structure manufacture method, also being formed with the barrier layer on the said Semiconductor substrate, said first low dielectric coefficient medium layer covers the surface on said barrier layer.
Optional; In said double mosaic structure manufacture method; The surface of said first low dielectric coefficient medium layer also is formed with protective layer, and said protective layer is removed utilizing chemical mechanical milling tech to remove in the step of the metal material on first low dielectric coefficient medium layer.
Accordingly, the present invention also provides a kind of dual-damascene structure, and said dual-damascene structure comprises: Semiconductor substrate; Be formed at first low dielectric coefficient medium layer on the said Semiconductor substrate, said first low dielectric coefficient medium layer does not damage; Be positioned at second low dielectric coefficient medium layer on said first low dielectric coefficient medium layer; The through hole and the groove that run through first low dielectric coefficient medium layer and second low dielectric coefficient medium layer; Be filled in the metal level in said through hole and the groove.
Owing to adopted above technical scheme, compared with prior art, the present invention has the following advantages:
After the metal material of the present invention on removing first low dielectric coefficient medium layer; Remove first dielectric layer of damage; And on remaining first low dielectric coefficient medium layer, form second low dielectric coefficient medium layer; With the dielectric constant value stabilization of the dielectric layer of guaranteeing dual-damascene structure, atraumatic first dielectric layer has a negative impact to the performance of metal interconnecting wires, helps improving the reliability of semiconductor device.
Description of drawings
Figure 1A to Fig. 1 D is the generalized section of each step corresponding construction of existing double mosaic structure manufacture method;
Fig. 2 is the flow chart of the double mosaic structure manufacture method that the embodiment of the invention provided;
Fig. 3 A to Fig. 3 F is the generalized section of each step corresponding construction of the double mosaic structure manufacture method that the embodiment of the invention provided.
Embodiment
According to background technology; When utilizing chemical mechanical milling tech to remove the metal material on the low dielectric coefficient medium layer; Can make the low dielectric coefficient medium layer of segment thickness be damaged, cause the dielectric constant of low dielectric coefficient medium layer to change, influence the reliability of semiconductor device.Therefore; The present invention provides a kind of dual-damascene structure and manufacturing approach thereof; After the metal material of said double mosaic structure manufacture method on removing first low dielectric coefficient medium layer; Remove first dielectric layer of damage, and on remaining first low dielectric coefficient medium layer, form second low dielectric coefficient medium layer, to guarantee the finally dielectric constant value stabilization of the dielectric layer of the dual-damascene structure of formation; Atraumatic first dielectric layer has a negative impact to the performance of the metal interconnecting wires of follow-up formation, helps improving the reliability of semiconductor device.
Please refer to Fig. 2, it is the flow chart of the double mosaic structure manufacture method that the embodiment of the invention provided, and in conjunction with this Fig. 2, this method may further comprise the steps:
Step S210 provides Semiconductor substrate, is formed with first low dielectric coefficient medium layer on the said Semiconductor substrate and is formed at groove and the through hole in said first low dielectric coefficient medium layer;
Step S220 forms metal material on first low dielectric coefficient medium layer and in groove and the through hole;
Step S230 utilizes chemical mechanical milling tech to remove the metal material on first low dielectric coefficient medium layer, and this chemical mechanical milling tech forms first dielectric layer of part damage on first low dielectric coefficient medium layer surface;
Step S240 removes first dielectric layer of said damage;
Step S250 forms second low dielectric coefficient medium layer on remaining first low dielectric coefficient medium layer.
To combine generalized section that dual-damascene structure of the present invention and manufacturing approach thereof are described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.
Shown in Fig. 3 A, and integrating step S210, at first, Semiconductor substrate 300 is provided.Said Semiconductor substrate 300 can be the substrate (part that comprises integrated circuit and other elements) of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes.
In said Semiconductor substrate 300, form metal wiring layer 301, the material of said metal wiring layer 301 can be in aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, tantalum, the copper one or several, and the material of said metal wiring layer 301 is preferably used copper.Because the present invention relates generally to the manufacture craft of dual-damascene structure, thus will not introduce the process that in Semiconductor substrate 300, forms metal wiring layer 301, but those skilled in the art are still this and know.
Shown in Fig. 3 B; And integrating step S210, then, on said Semiconductor substrate 300, form first low dielectric coefficient medium layer 310; And in first low dielectric coefficient medium layer 310, form groove 310b and through hole 310a; The position of said groove 310b is corresponding with the position of through hole 310a, and said groove 310b is communicated with through hole 310a, and the cross-sectional width of said groove 310b is greater than the cross-sectional width of through hole 310a.
In the present embodiment, in first low dielectric coefficient medium layer 310, define the through hole 310a that penetrates first low dielectric coefficient medium layer 310 fully earlier, utilize another photoresist layer to define groove 310b then.Certainly, in other embodiment of the present invention, also can define groove 310b on the top of first low dielectric coefficient medium layer 310 earlier, utilize another photoresist layer to define through hole 310a then.
Said first low dielectric coefficient medium layer 310 is selected advanced low-k materials for use, to reduce the parasitic capacitance of intraconnections, postpones thereby reduce RC, and alleviates the interference between the intraconnections, and then improve the speed of the operation of device.Said low dielectric coefficient medium layer 110 materials can be the silica (FSG) of mixing fluorine, the silica of carbon dope and the carborundum inorganic material such as (BLOK) of nitrating, or organic polymers such as poly aromatic alkene ether (flare), aromatic hydrocarbons (SILK) and xylenes plastics.In the present embodiment, it is the silica of the carbon dope of black diamond (black diamond) that the material of said first low dielectric coefficient medium layer 310 can adopt the trade mark of Material Used (Applied Materials) company, and it can form through modes such as chemical vapour deposition (CVD)s.
Optional; Before forming the step of first low dielectric coefficient medium layer 310 on the said Semiconductor substrate 300; On said Semiconductor substrate 300, form barrier layer 330 earlier; Said first low dielectric coefficient medium layer 310 covers the surface on said barrier layer 330, and said through hole 310a runs through said barrier layer 330.Said barrier layer 330 can be used for preventing metal diffusing in the metal line in first low dielectric coefficient medium layer 310, and barrier layer 330 also can prevent in follow-up etching process of carrying out simultaneously, and the metal wiring layers 301 in the Semiconductor substrate 300 are etched.The material on said barrier layer 330 can be a silicon nitride, and first low dielectric coefficient medium layer 310 of itself and follow-up formation has good adhesive force property.Certainly, the material on barrier layer 330 can also be other can barrier metal the material of diffusion, for example, the carborundum of silicon oxynitride or doping nitrogen etc.The thickness on said barrier layer 330 can it can form through modes such as chemical vapour deposition (CVD)s for
.
Optional, on said Semiconductor substrate 300, form after the step of first low dielectric coefficient medium layer 310, can also on said first low dielectric coefficient medium layer 310, form protective layer 340.Said protective layer 340 can be used to further protect hardness and the first less low dielectric coefficient medium layer 310 of dielectric constant, and the material of said protective layer 340 is silicon nitride or carborundum, and said protective layer 340 can form through modes such as chemical vapour deposition (CVD)s.
Shown in Fig. 3 C, and integrating step S220, metal material 320 formed on first low dielectric coefficient medium layer 310 and in groove 310b and the through hole 310a.The material of said metal material 320 for example is a metallic copper, can form said metal material 320 through the mode of physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Shown in Fig. 3 D; And integrating step S230; Then; Utilize chemical mechanical milling tech to remove the metal material on first low dielectric coefficient medium layer 310, in groove 310b and through hole 310a, to form metal level 321, the metal wiring layer 301 in said metal level 321 and the Semiconductor substrate 300 electrically connects.
Through present inventor's discovery that studies for a long period of time; In the process of carrying out chemical mechanical milling tech; Inevitably; Employed lapping liquid can react with the surface of low dielectric coefficient medium layer 310, make the low dielectric coefficient medium layer of segment thickness be damaged, and its dielectric constant can change.For narrating conveniently; Below first low dielectric coefficient medium layer of damaged partly is called first dielectric layer 312 of damage, intac first low dielectric coefficient medium layer partly is called unmarred first dielectric layer 311, in addition; In order to illustrate conveniently; Interface with unmarred first dielectric layer 311 and first dielectric layer 312 of damage in cutaway view is expressed as horizontal line, it will be understood by those of skill in the art that actual interface might not be the plane.
In the present embodiment, when utilizing chemical mechanical milling tech to remove the metal material on said first low dielectric coefficient medium layer 310, said protective layer 340 also is removed.
Shown in Fig. 3 E, and integrating step S240, committed step of the present invention is to remove first dielectric layer 312 of said damage.Preferably, utilize wet-etching technology to remove first dielectric layer 312 of said damage, said wet-etching technology can not cause any damage to advanced low-k materials.The hydrofluoric acid that the employed etching liquid style of said wet-etching technology is diluted in this way, the etch period of said wet-etching technology can be 10 seconds～600 seconds.
In the present embodiment, only remove first dielectric layer 312 of whole damages, do not remove unmarred first dielectric layer 311.Yet will be appreciated that; In other embodiments of the invention; When the step of first dielectric layer 312 of removing said damage, can also remove unmarred first dielectric layer of segment thickness, can be removed fully with first dielectric layer 312 of guaranteeing said damage.
Shown in Fig. 3 F, and integrating step S250, then, go up formation second low dielectric coefficient medium layer 350 at remaining first low dielectric coefficient medium layer 310 '.Because the embodiment of the invention has been removed by first dielectric layer 312 of lapping liquid damage; And on remaining first low dielectric coefficient medium layer 310 ', formed second low dielectric coefficient medium layer 350; Can guarantee the dielectric constant value stabilization of the dielectric layer of the final dual-damascene structure that forms; The performance of the metal interconnecting wires of 312 pairs of follow-up formation of atraumatic first dielectric layer has a negative impact, and can improve the reliability of semiconductor device.
Preferably, the thickness of said second low dielectric coefficient medium layer 350 equals the thickness of removed first low dielectric coefficient medium layer, the flush of the surface of promptly said second low dielectric coefficient medium layer 350 and metal level 321.Yet will be appreciated that the thickness of said second low dielectric coefficient medium layer 350 also can be slightly larger than the thickness of removed first low dielectric coefficient medium layer, to reduce technique controlling difficulty.In the present embodiment, the thickness of first dielectric layer 312 of said damage be
said second low dielectric coefficient medium layer 350 thickness is
Preferable, said second low dielectric coefficient medium layer 350 is organic polymers such as poly aromatic alkene ether (flare), aromatic hydrocarbons (SILK) and xylenes plastics.Spin coating mode capable of using forms said second low dielectric coefficient medium layer 350, utilizes the surface of second low dielectric coefficient medium layer 350 that the spin coating mode forms comparatively smooth.Certainly, the material of said second low dielectric coefficient medium layer 350 also can be the silica (FSG) of mixing fluorine, the silica of carbon dope and the carborundum inorganic material such as (BLOK) of nitrating, and the mode of its chemical vapour deposition (CVD) capable of using forms.
Continue with reference to figure 3F, and combine Fig. 3 A to Fig. 3 E, the dual-damascene structure based on above-mentioned double mosaic structure manufacture method forms comprises: Semiconductor substrate 300; Be formed at first low dielectric coefficient medium layer 310 ' on the said Semiconductor substrate 300, said first low dielectric coefficient medium layer 310 ' does not damage; Be positioned at second low dielectric coefficient medium layer 350 on said first low dielectric coefficient medium layer 310 '; The through hole 310a and the groove 310b that run through said first low dielectric coefficient medium layer 310 ' and second low dielectric coefficient medium layer 350; Be filled in the metal level 321 in said through hole 310a and the groove 310b.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (15)
1. double mosaic structure manufacture method comprises:
Semiconductor substrate is provided, is formed with first low dielectric coefficient medium layer on the said Semiconductor substrate and is formed at groove and the through hole in said first low dielectric coefficient medium layer;
On said first low dielectric coefficient medium layer and in said groove and the through hole, form metal material;
Utilize chemical mechanical milling tech to remove the metal material on first low dielectric coefficient medium layer, this chemical mechanical milling tech forms first dielectric layer of part damage on first low dielectric coefficient medium layer surface;
Remove first dielectric layer of said damage;
On remaining first low dielectric coefficient medium layer, form second low dielectric coefficient medium layer.
2. double mosaic structure manufacture method as claimed in claim 1 is characterized in that, first dielectric layer of said damage utilizes wet-etching technology to remove.
3. double mosaic structure manufacture method as claimed in claim 2 is characterized in that, the material of said first low dielectric coefficient medium layer is a kind of or its combination in the carborundum of silica or nitrating of the silica of mixing fluorine, carbon dope.
4. double mosaic structure manufacture method as claimed in claim 3 is characterized in that, the employed etching liquid of said wet-etching technology is the hydrofluoric acid of dilution.
5. double mosaic structure manufacture method as claimed in claim 4 is characterized in that, the etch period of said wet-etching technology is 10 seconds～600 seconds.
6. double mosaic structure manufacture method as claimed in claim 1 is characterized in that, the thickness of said second low dielectric coefficient medium layer is more than or equal to the thickness of first dielectric layer of said damage.
7. double mosaic structure manufacture method as claimed in claim 6; It is characterized in that, the thickness of first dielectric layer of said damage be
said second low dielectric coefficient medium layer thickness is
8. double mosaic structure manufacture method as claimed in claim 1 is characterized in that, removes after first dielectric layer of said damage, also comprises: unmarred first dielectric layer of removing segment thickness.
9. double mosaic structure manufacture method as claimed in claim 1 is characterized in that, the material of said second low dielectric coefficient medium layer is a kind of or its combination in the carborundum of silica or nitrating of the silica of mixing fluorine, carbon dope.
10. double mosaic structure manufacture method as claimed in claim 9 is characterized in that, said second low dielectric coefficient medium layer is to utilize the mode of chemical vapour deposition (CVD) to form.
11. double mosaic structure manufacture method as claimed in claim 1 is characterized in that, the material of said second low dielectric coefficient medium layer is an organic polymer.
12. double mosaic structure manufacture method as claimed in claim 11 is characterized in that, said second low dielectric coefficient medium layer utilizes the spin coating mode to form.
13. double mosaic structure manufacture method as claimed in claim 1 is characterized in that, also is formed with barrier layer, the surface of the said first low dielectric coefficient medium layer covering barrier layer on the said Semiconductor substrate.
14. double mosaic structure manufacture method as claimed in claim 1; It is characterized in that; The surface of said first low dielectric coefficient medium layer also is formed with protective layer, and said protective layer is removed utilizing chemical mechanical milling tech to remove in the step of the metal material on first low dielectric coefficient medium layer.
15. a dual-damascene structure is characterized in that, comprising:
Semiconductor substrate;
Be formed at first low dielectric coefficient medium layer on the said Semiconductor substrate, said first low dielectric coefficient medium layer does not damage;
Be positioned at second low dielectric coefficient medium layer on said first low dielectric coefficient medium layer;
The through hole and the groove that run through first low dielectric coefficient medium layer and second low dielectric coefficient medium layer;
Be filled in the metal level in said through hole and the groove.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515304A (en) * | 2012-06-19 | 2014-01-15 | 台湾积体电路制造股份有限公司 | Etch damage and esl free dual damascene metal interconnect |
| CN104835749A (en) * | 2014-02-11 | 2015-08-12 | 东琳精密股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| WO2022037243A1 (en) * | 2020-08-18 | 2022-02-24 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1421928A (en) * | 2001-09-27 | 2003-06-04 | 株式会社东芝 | Semiconductor device with embedded electric conducting layer and producing method thereof |
| CN101079408A (en) * | 2006-05-22 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Double-inlay structure and its making method |
| CN101369535A (en) * | 2007-08-17 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | Method for improving defect of insulation dielectric layer and forming dual damascene structure |
-
2010
- 2010-08-24 CN CN201010261552XA patent/CN102376597A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1421928A (en) * | 2001-09-27 | 2003-06-04 | 株式会社东芝 | Semiconductor device with embedded electric conducting layer and producing method thereof |
| CN101079408A (en) * | 2006-05-22 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Double-inlay structure and its making method |
| CN101369535A (en) * | 2007-08-17 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | Method for improving defect of insulation dielectric layer and forming dual damascene structure |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515304A (en) * | 2012-06-19 | 2014-01-15 | 台湾积体电路制造股份有限公司 | Etch damage and esl free dual damascene metal interconnect |
| US9318377B2 (en) | 2012-06-19 | 2016-04-19 | Taiwan Semiconductor Manufacutring Co., Ltd. | Etch damage and ESL free dual damascene metal interconnect |
| CN103515304B (en) * | 2012-06-19 | 2016-05-04 | 台湾积体电路制造股份有限公司 | Without the dual damascene metal interconnection part of etch damage and Department of Electronics's irrespective of size (ESL) |
| US9786549B2 (en) | 2012-06-19 | 2017-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch damage and ESL free dual damascene metal interconnect |
| US10312136B2 (en) | 2012-06-19 | 2019-06-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Etch damage and ESL free dual damascene metal interconnect |
| US11171041B2 (en) | 2012-06-19 | 2021-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch damage and ESL free dual damascene metal interconnect |
| US11955376B2 (en) | 2012-06-19 | 2024-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etch damage and ESL free dual damascene metal interconnect |
| CN104835749A (en) * | 2014-02-11 | 2015-08-12 | 东琳精密股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| WO2022037243A1 (en) * | 2020-08-18 | 2022-02-24 | 长鑫存储技术有限公司 | Semiconductor structure and method for forming same |
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