CN102375745A - Negated AND (NAND) gate flash starting device and using method thereof - Google Patents
Negated AND (NAND) gate flash starting device and using method thereof Download PDFInfo
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- CN102375745A CN102375745A CN2010102519306A CN201010251930A CN102375745A CN 102375745 A CN102375745 A CN 102375745A CN 2010102519306 A CN2010102519306 A CN 2010102519306A CN 201010251930 A CN201010251930 A CN 201010251930A CN 102375745 A CN102375745 A CN 102375745A
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- flash memory
- gate flash
- sheffer stroke
- stroke gate
- terminal
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Abstract
The invention provides a negated AND (NAND) gate flash starting device. The device comprises a central processing unit (CPU), and an NAND gate flash, a synchronous dynamic random access memory (SDRAM) and a pulse counting unit which are electrically connected with the CPU, wherein the NAND gate flash is used for prestoring a boot-loading program for starting a system; the pulse counting unit is used for initiating the NAND gate flash by generating a pulse signal to enable the NAND gate flash; and the CPU is used for reading the boot-loading program and transferring the boot-loading program to the SDRAM through the NAND gate flash so as to start the system. The invention also provides a using method for the NAND gate flash starting device. By the method, design cost can be reduced by using an NAND gate flash starting system.
Description
Technical field
The present invention relates to a kind of starter gear, relate in particular to a kind of Sheffer stroke gate flash memory starter gear and method of application based on embedded OS.
Background technology
Flash memory can be divided into rejection gate flash memory (NOR Flash) and Sheffer stroke gate flash memory (NAND Flash) on using at present.The NOR Flash Code Flash that generally is otherwise known as wherein; Because NOR Flash belongs to the non-voltile memory of linear addressing (Linearaddressing); Microprocessor can directly be carried out the program in the rejection gate flash memory; Do not need earlier with program read system synchronous DRAM (Synchronous Dynamic Random Access Memory, SDRAM) in, system start-up is convenient.But also there is the shortcoming that storage density is lower, price is comparatively expensive simultaneously in NOR Flash.By contrast, NAND Flash storage density is higher and price is lower, but because NAND Flash is similar to mechanical hard disk, belongs to block addressing (Block Addressing), and difficulty is bigger when being used for the back-up system startup.Therefore, most on the market embedded OS is difficult to make full use of the cost advantage of NAND Flash still with the media of NORFlash as the guidance system start at present.
Summary of the invention
In view of above situation, be necessary to provide a kind of NAND of utilization Flash to realize the Sheffer stroke gate flash memory starter gear of system start-up.
In addition, also be necessary to provide a kind of method of application of utilizing this Sheffer stroke gate flash memory starter gear to realize system start-up.
A kind of Sheffer stroke gate flash memory starter gear; It comprises a central processing unit and the Sheffer stroke gate flash memory, a synchronous dynamic RAM and the step-by-step counting unit that electrically connect with this central processing unit; One section bootstrap loader that is used for start-up system of said Sheffer stroke gate flash memory pre-stored; Said step-by-step counting unit is through producing this Sheffer stroke gate flash memory of pulse signal initialization; So that this Sheffer stroke gate flash memory enables, said central processing unit reads said bootstrap loader and this bootstrap loader is transferred to synchronous DRAM start-up system then through this Sheffer stroke gate flash memory.
A kind of method of application of Sheffer stroke gate flash memory starter gear, it may further comprise the steps: the said Sheffer stroke gate flash memory of initialization; Control Sheffer stroke gate flash memory reads bootstrap loader; Bootstrap loader is read in the synchronous dynamic RAM; Bootstrap loader in the operation synchronous DRAM, start-up system.
With respect to prior art; Said Sheffer stroke gate flash memory starter gear utilizes step-by-step counting unit initialization Sheffer stroke gate flash memory; So that this Sheffer stroke gate flash memory enables and read bootstrap loader, and then transfer in the synchronous DRAM this bootstrap loader and final start-up system through central processing unit.This Sheffer stroke gate flash memory starter gear can directly pass through Sheffer stroke gate flash memory start-up system, compares with using comparatively expensive rejection gate flash memory, and cost is cheaper.
Description of drawings
Fig. 1 is the functional block diagram of the Sheffer stroke gate flash memory starter gear of preferred embodiments of the present invention;
Fig. 2 is the Sheffer stroke gate flash memory shown in Figure 1 and the circuit diagram of step-by-step counting unit;
Fig. 3 is the rolling counters forward value shown in Figure 2 and the table of comparisons of Sheffer stroke gate flash memory pin state;
Fig. 4 is the working timing figure of Sheffer stroke gate flash memory starter gear shown in Figure 1;
Fig. 5 is the process flow diagram of Sheffer stroke gate flash memory starter gear method of application shown in Figure 1.
The main element symbol description
Sheffer stroke gate flash memory starter gear 100
Sheffer stroke gate flash memory 10
Order latch signal pin CLE
Address latch signal pin ALE
Chip enable pin
Data input and output pin I/O
Write enable
Read enable
Detect pin
Step-by-step counting unit 30
Clock terminal Clk
Counting terminal 0-7
Interrupt terminal S
Protection terminal Z
Counter 32
With door 34
First not gate 36
Second not gate 38
Chronotron 39
Synchronous DRAM 70
Embodiment
See also Fig. 1 and Fig. 2, preferred embodiments of the present invention provides a kind of Sheffer stroke gate flash memory starter gear 100, and it can be used for starting an embedded system device (like STB, figure does not show) commonly used.This Sheffer stroke gate flash memory starter gear 100 comprise a Sheffer stroke gate flash memory 10 (NAND Flash), a step-by-step counting unit 30, a central processing unit 50 (centralprocessing unit, CPU) and a synchronous dynamic RAM 70 (SDRAM).This NAND Flash 10, step-by-step counting unit 30 and SDRAM70 all electrically connect with CPU50.
This NAND Flash10 stored bootstrap loader (Pre-Bootloader), it is one section program of operation before the system kernel operation, but through this program initialization computer hardware, thinks that final calling system kernel prepares.The NAND? Flash10 includes a command latch signal pin CLE, an address latch signal pin ALE, a chip enable pin
data input and output pin I / O, a write enable pin
a read enable pin
and a detection pin
where command latch signal pin CLE and ALE address latch signal pin is active high; chip enable pin
is active low; write enable pin
is active low, with the in the data write NAND? Flash? 10; Read Enable pin
is active low, which is electrically connected to CPU50, CPU50 under control in order to read the Pre-Bootloader data; detection pin
is a control port, the electrical linked to a CPU50, the detect pin
high preparation (READY) signal low is busy (BUSY) signal, when the detect pin
The BUSY signal from the READY state to state, which means that NAND? Flash10 ready to execute the command then becomes READY status means ready to execute commands.
This step-by-step counting unit 30 is used for NAND Flash10 is carried out initialization, to drive this each pin enabled of NAND Flash10 or not enable.This step-by-step counting unit 30 comprises a counter 32, one and door 34,1 first not gate 36, one second not gate 38 and a chronotron 39.This counter 32 is one 8 digit counters, and it comprises that a clock terminal Clk, a plurality of counting terminal 0-7, interrupt a terminal S and a protection terminal Z.This clock terminal Clk and CPU50 electrically connect, to receive the clock signal of CPU50.Meanwhile, the clock terminal 39 through the delay Clk electrically connected to the NAND? Flash10 write enable pin
On a delay control write enable pin
enabled.These countings terminal 0-7 is through from 00000000 counting successively, with each pin enabled of control NAND Flash10/do not enable.Should have three input ends with door 34; Specifically; This counting terminal 0 and 1 is electrically connected at respectively and door 34 two input ends, and this counting terminal 2 is electrically connected at and another input end of 34 through first not gate 36, simultaneously; This counting terminal 2 electrically connects with the address latch signal pin ALE of NAND Flash10, should be electrically connected at the order latch signal pin CLE of NAND Flash10 with the output terminal of door 34; This counting terminal 3 is electrically connected at NAND Flash10 through second not gate 38 this counting terminal 4 of chip enable pin
all electrically connects with interruption terminal S and protection terminal Z; When this counting terminal 4 is output as 1; Counter 32 stops counting; Protect terminal Z to be changed to high resistant simultaneously; Thereby chip enable pin
that makes NAND Flash10 etc. also is changed to high resistant, in order to avoid influence the logic control of CPU50; This counting terminal 5 electrically connects with the data input and output pin I/O of NAND Flash10, and this counting terminal 6 and 7 is unsettled.
See also Fig. 3; When this counter 32 begins to count; When this counting terminal 3 is output as 0; Promptly count terminal 0-3 count value in 7 recurrence intervals of 0000-1110; The chip enable pin of this NAND Flash10
is 1, and this NAND Flash10 does not enable.When this counting terminal 3 is 1; Chip enable pin
is 0; This NAND Flash10 enables, and this counter 32 continues counting thereafter.When counting terminal 0-3 count value was 1101, the order latch signal pin CLE of NAND Flash10 enabled, when counting terminal 0-3 count value when 0011 changes to 1111, the address latch signal pin ALE of NAND Flash10 enables.When counter 32 continues counting, 4 set 1 of counting terminal, this hour counter 32 stops counting, and each pin of NAND Flash10 is changed to high resistant, and this promptly accomplishes NAND Flash10 initialization.
Please combine to consult Fig. 3 and Fig. 4; Counting terminal 0-3 at counter 32 count down at 0001 o'clock, and chip enable pin
low level enables.Its post command latch signal pin CLE enables; Write enable
and address latch signal pin ALE enables thereupon; After waiting for one section time-delay; Detect pin
and start, promptly transfer low level to and transfer high level again to from high level.After this be changed to low level whenever reading enable
; CPU50 promptly controls and reads enable
and read one group of Pre-Bootloader data from data input and output pin I/O, up to running through all Pre-Bootloader data.Last CPU50 reads these Pre-Bootloader data among the SDRAM70 through MOV, JUMP instruction, to prepare start-up system.
Please combine to consult Fig. 5, the method for using this Sheffer stroke gate flash memory starter gear 100 to start embedded system device may further comprise the steps:
S1: step-by-step counting unit 30 initialization NAND Flash 10;
S2: control pin
transfers low level to by high level and transfers high level again to;
S3: read enable
and be changed to low level and enable;
S4:CPU50 reads the dependent instruction that enable
reads the Pre-Bootloader data and carries out Pre-Bootloader through control;
The S5:SDRAM70 initialization;
S6:CPU50 transfers to the Pre-Bootloader data among the SDRAM70 through MO V instruction;
S7:CPU50 jumps to the entrance operation Bootloader of SDRAM70, start-up system.
Be appreciated that; The present invention is intended to initialization NAND Flash10; So this step-by-step counting unit 30 also can adopt other form to realize, as long as chip enable pin
order latch signal pin CLE and address latch signal pin ALE are enabled.
The present invention is through step-by-step counting unit 30 initialization NAND Flash10; So that NANDFlash10 reads the Pre-Bootloader data in the NAND Flash10 through the change that detects pin
and read enable
level under the control of CPU50; And these data are transferred to SDRAM70, with start-up system.This Sheffer stroke gate flash memory starter gear 100 can directly start from NAND Flash10, has avoided use NOR Flash, provides cost savings effectively.
Claims (11)
1. Sheffer stroke gate flash memory starter gear; It comprises a central processing unit and the Sheffer stroke gate flash memory and the synchronous dynamic RAM that electrically connect with this central processing unit; It is characterized in that: one section bootstrap loader that is used for start-up system of said Sheffer stroke gate flash memory pre-stored; Said Sheffer stroke gate flash memory starter gear also comprises a step-by-step counting unit; Said step-by-step counting unit and central processing unit electrically connect; Said step-by-step counting unit is through producing this Sheffer stroke gate flash memory of pulse signal initialization, so that this Sheffer stroke gate flash memory enables, said central processing unit reads said bootstrap loader and this bootstrap loader is transferred to synchronous DRAM start-up system then through this Sheffer stroke gate flash memory.
2. Sheffer stroke gate flash memory starter gear as claimed in claim 1; It is characterized in that: said Sheffer stroke gate flash memory comprises that reading enable and detects pin; When detecting pin and transferred to low level and transferred to high level again by high level, this central processing unit control is read enable and is read said bootstrap loader.
3. Sheffer stroke gate flash memory starter gear as claimed in claim 1; It is characterized in that: said step-by-step counting unit comprises a counter, one and door, one first not gate and one second not gate; Said and door comprises three input ends; Said counter comprises counting terminal 0-7, wherein counts terminal 0 and counting terminal 1 and is electrically connected at two input ends with door, and counting terminal 2 is electrically connected at another input end with door through first not gate; The counting terminal 3 and second not gate electrically connect, and counting terminal 5 electrically connects with the Sheffer stroke gate flash memory.
4. Sheffer stroke gate flash memory starter gear as claimed in claim 3 is characterized in that: said Sheffer stroke gate flash memory comprises an order latch signal pin, and said output terminal with door electrically connects with order latch signal pin.
5. Sheffer stroke gate flash memory starter gear as claimed in claim 4; It is characterized in that: said Sheffer stroke gate flash memory comprises an address latch signal pin, a chip enable pin and a data input and output pin; Said counting terminal 2 electrically connects with the address latch signal pin; Said counting terminal 3 electrically connects through second not gate and chip enable pin, and said counting terminal 5 electrically connects with the data input and output pin.
6. Sheffer stroke gate flash memory starter gear as claimed in claim 3; It is characterized in that: said counter comprises that also one interrupts a terminal and a protection terminal; Said interruption terminal is electrically connected at counting terminal 4 simultaneously with the protection terminal; When these counting terminal 4 set 1, this counter stops counting, and this protection terminal is changed to high resistant.
7. Sheffer stroke gate flash memory starter gear as claimed in claim 6; It is characterized in that: said Sheffer stroke gate flash memory comprises writes enable; Said step-by-step counting unit comprises a counter and a chronotron; Said counter comprises a clock terminal, and said clock terminal receives the time kind signal of central processing unit, this clock terminal through chronotron with write enable and electrically connect.
8. the method for application of a Sheffer stroke gate flash memory starter gear, it may further comprise the steps:
The said Sheffer stroke gate flash memory of initialization;
Control Sheffer stroke gate flash memory reads bootstrap loader;
Bootstrap loader is read in the synchronous dynamic RAM;
Bootstrap loader in the operation synchronous DRAM, start-up system.
9. the method for application of Sheffer stroke gate flash memory starter gear as claimed in claim 8: it is characterized in that: the control pin that also comprises a Sheffer stroke gate flash memory after the step of the said Sheffer stroke gate flash memory of said initialization transfers the step that low level transfers high level again to by high level.
10. the method for application of Sheffer stroke gate flash memory starter gear as claimed in claim 8: it is characterized in that: the control pin of said Sheffer stroke gate flash memory comprises that also the enable of reading of a Sheffer stroke gate flash memory is changed to low level step after transferring the step that low level transfers high level again to by high level.
11. the method for application of Sheffer stroke gate flash memory starter gear as claimed in claim 10: it is characterized in that: the said step that also comprises the said synchronous DRAM of an initialization before the step in the synchronous dynamic RAM that bootstrap loader is read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010251930.6A CN102375745B (en) | 2010-08-12 | 2010-08-12 | Negated AND (NAND) gate flash starting device and using method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010251930.6A CN102375745B (en) | 2010-08-12 | 2010-08-12 | Negated AND (NAND) gate flash starting device and using method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102375745A true CN102375745A (en) | 2012-03-14 |
| CN102375745B CN102375745B (en) | 2014-03-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010251930.6A Expired - Fee Related CN102375745B (en) | 2010-08-12 | 2010-08-12 | Negated AND (NAND) gate flash starting device and using method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543602A (en) * | 2001-08-06 | 2004-11-03 | System and method for booting from a non-volatile application and file storage device | |
| CN1591369A (en) * | 2003-08-27 | 2005-03-09 | 株式会社日立制作所 | Electronic apparatus and method for starting up system of such apparatus |
| US20050108500A1 (en) * | 2003-11-18 | 2005-05-19 | Junichi Kishida | Bootable NAND flash memory architecture |
| CN101118494A (en) * | 2006-08-01 | 2008-02-06 | 环达电脑(上海)有限公司 | System and method for starting up and operating system from external connected electronic card with built-in equipment |
-
2010
- 2010-08-12 CN CN201010251930.6A patent/CN102375745B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543602A (en) * | 2001-08-06 | 2004-11-03 | System and method for booting from a non-volatile application and file storage device | |
| CN1591369A (en) * | 2003-08-27 | 2005-03-09 | 株式会社日立制作所 | Electronic apparatus and method for starting up system of such apparatus |
| US20050108500A1 (en) * | 2003-11-18 | 2005-05-19 | Junichi Kishida | Bootable NAND flash memory architecture |
| CN101118494A (en) * | 2006-08-01 | 2008-02-06 | 环达电脑(上海)有限公司 | System and method for starting up and operating system from external connected electronic card with built-in equipment |
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| Publication number | Publication date |
|---|---|
| CN102375745B (en) | 2014-03-26 |
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Granted publication date: 20140326 Termination date: 20160812 |