CN102375745B - Negated AND (NAND) gate flash starting device and using method thereof - Google Patents
Negated AND (NAND) gate flash starting device and using method thereof Download PDFInfo
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- CN102375745B CN102375745B CN201010251930.6A CN201010251930A CN102375745B CN 102375745 B CN102375745 B CN 102375745B CN 201010251930 A CN201010251930 A CN 201010251930A CN 102375745 B CN102375745 B CN 102375745B
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- gate flash
- flash memory
- terminal
- sheffer stroke
- stroke gate
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Abstract
The invention provides a negated AND (NAND) gate flash starting device. The device comprises a central processing unit (CPU), and an NAND gate flash, a synchronous dynamic random access memory (SDRAM) and a pulse counting unit which are electrically connected with the CPU, wherein the NAND gate flash is used for prestoring a boot-loading program for starting a system; the pulse counting unit is used for initiating the NAND gate flash by generating a pulse signal to enable the NAND gate flash; and the CPU is used for reading the boot-loading program and transferring the boot-loading program to the SDRAM through the NAND gate flash so as to start the system. The invention also provides a using method for the NAND gate flash starting device. By the method, design cost can be reduced by using an NAND gate flash starting system.
Description
Technical field
The present invention relates to a kind of starter gear, relate in particular to a kind of Sheffer stroke gate flash memory starting device and using method based on embedded OS.
Background technology
Flash memory can be divided into rejection gate flash memory (NOR Flash) and Sheffer stroke gate flash memory (NAND Flash) in application at present.The NOR Flash Code Flash that is generally otherwise known as wherein, because NOR Flash belongs to the non-voltile memory of linear addressing (Linearaddressing), microprocessor can directly be carried out the program in rejection gate flash memory, do not need first program to be read synchronous DRAM (the Synchronous Dynamic Random Access Memory of system, SDRAM), in, system starts convenient.But also there is the shortcoming that storage density is lower, price is comparatively expensive simultaneously in NOR Flash.By contrast, NAND Flash storage density is higher and price is lower, but because NAND Flash is similar to mechanical hard disk, belongs to block addressing (Block Addressing), and while starting for back-up system, difficulty is larger.Therefore, at present most embedded OS is still usingd NORFlash as the medium of guidance system start on the market, is difficult to make full use of the cost advantage of NAND Flash.
Summary of the invention
In view of above situation, be necessary to provide a kind of NAND of utilization Flash to realize the Sheffer stroke gate flash memory starting device that system starts.
Separately, be also necessary to provide a kind of this Sheffer stroke gate flash memory starting device that utilizes to realize the using method that system starts.
A kind of Sheffer stroke gate flash memory starting device, it comprises a central processing unit and the Sheffer stroke gate flash memory being electrically connected with this central processing unit, one synchronous DRAM and a step-by-step counting unit, one section of described Sheffer stroke gate flash memory pre-stored is for starting the bootstrap loader of system, described step-by-step counting unit is by producing this Sheffer stroke gate flash memory of pulse signal initialization, so that this Sheffer stroke gate flash memory enables, described central processing unit is read described bootstrap loader and this bootstrap loader is transferred to synchronous DRAM by this Sheffer stroke gate flash memory and then starts system.
A using method for Sheffer stroke gate flash memory starting device, it comprises the following steps: Sheffer stroke gate flash memory described in initialization; Control Sheffer stroke gate flash memory and read bootstrap loader; Bootstrap loader is read in a synchronous DRAM; Bootstrap loader in operation synchronous DRAM, startup system.
With respect to prior art, described Sheffer stroke gate flash memory starting device utilizes step-by-step counting unit initialization Sheffer stroke gate flash memory, so that this Sheffer stroke gate flash memory enables and read bootstrap loader, and then by central processing unit, this bootstrap loader is transferred in synchronous DRAM and final startup system.This Sheffer stroke gate flash memory starting device can directly start system by Sheffer stroke gate flash memory, compares with using comparatively expensive rejection gate flash memory, and cost is cheaper.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of the Sheffer stroke gate flash memory starting device of better embodiment of the present invention;
Fig. 2 is the circuit diagram of the Sheffer stroke gate flash memory shown in Fig. 1 and step-by-step counting unit;
Fig. 3 is the table of comparisons of the rolling counters forward value shown in Fig. 2 and Sheffer stroke gate flash memory pin state;
Fig. 4 is the working timing figure of the Sheffer stroke gate flash memory starting device shown in Fig. 1;
Fig. 5 is the process flow diagram of the Sheffer stroke gate flash memory starting device using method shown in Fig. 1.
Main element symbol description
Sheffer stroke gate flash memory starting device 100
Sheffer stroke gate flash memory 10
Order latch signal pin CLE
Address latch signal pin ALE
Chip enable pin
Data input and output pin I/O
Write enable pin
Read enable pin
Detect pin
Step-by-step counting unit 30
Clock terminal Clk
Counting terminal 0-7
Interrupt terminal S
Protection terminal Z
With door 34
The first not gate 36
The second not gate 38
Chronotron 39
Synchronous DRAM 70
Embodiment
Refer to Fig. 1 and Fig. 2, better embodiment of the present invention provides a kind of Sheffer stroke gate flash memory starting device 100, and it can be used for starting a conventional embedded system device (as Set Top Box, figure does not show).This Sheffer stroke gate flash memory starting device 100 comprises a Sheffer stroke gate flash memory 10 (NAND Flash), a step-by-step counting unit 30, a central processing unit 50 (centralprocessing unit, CPU) and a synchronous DRAM 70 (SDRAM).This NAND Flash 10, step-by-step counting unit 30 and SDRAM70 are all electrically connected with CPU50.
Storage bootstrap loader (Pre-Bootloader) in this NAND Flash10, its one section of program for moving before system kernel operation, can initialization computer hardware by this program, thinks that final calling system kernel prepares.This NAND Flash10 comprises an order latch signal pin CLE, an address latch signal pin ALE, a chip enable pin
data input and output pin I/O, one writes enable pin
one reads enable pin
and one detect pin
wherein ordering latch signal pin CLE and address latch signal pin ALE is that high level is effective; Chip enable pin
for Low level effective; Write enable pin
for Low level effective, for data being write to NAND Flash 10; Read enable pin
for Low level effective, it is electrically connected at CPU50, under controlling at CPU50, reads Pre-Bootloader data; Detect pin
be a control port, it is electrically connected at CPU50, and this detects pin
during high level, for preparing (READY) signal, during low level, be busy (BUSY) signal, when detecting pin
signal from READY state, become BUSY state, represent that NAND Flash10 prepares fill order, and then become READY state representation and be ready to fill order.
This step-by-step counting unit 30 is for NAND Flash10 is carried out to initialization, to drive this each pin enabled of NAND Flash10 or not enable.This step-by-step counting unit 30 comprises a counter 32, one and door 34,1 first not gate 36, one second not gate 38 and a chronotron 39.This counter 32 is one 8 digit counters, and it comprises that a clock terminal Clk, a plurality of counting terminal 0-7, one interrupt terminal S and a protection terminal Z.This clock terminal Clk and CPU50 are electrically connected, to receive the clock signal of CPU50.This clock terminal Clk is electrically connected at the enable pin of writing of NAND Flash10 by chronotron 39 simultaneously
to control and to write enable pin after time delay
enable.These countings terminal 0-7 is by from 00000000 counting successively, to control each pin enabled of NAND Flash10/do not enable.Should there are three input ends with door 34, specifically, this counting terminal 0 and 1 is electrically connected at respectively two input ends with door 34, this counting terminal 2 is electrically connected at another input end with door 34 by the first not gate 36, simultaneously, this counting terminal 2 is electrically connected with the address latch signal pin ALE of NAND Flash10, should be electrically connected at the output terminal of door 34 the order latch signal pin CLE of NAND Flash10; This counting terminal 3 is electrically connected at the chip enable pin of NAND Flash10 by the second not gate 38
this counting terminal 4 is all electrically connected with protection terminal Z with interrupting terminal S, and when this counting terminal 4 is output as 1, counter 32 stops counting, protects terminal Z to be set to high resistant simultaneously, thereby makes the chip enable pin of NAND Flash10
deng also, be set to high resistant, in order to avoid affect the logic control of CPU50; This counting terminal 5 is electrically connected with the data input and output pin I/O of NAND Flash10, and this counting terminal 6 and 7 is unsettled.
Refer to Fig. 3, when this counter 32 starts to count, when this counting terminal 3 is output as 0, count terminal 0-3 count value within 7 recurrence intervals of 0000-1110, the chip enable pin of this NAND Flash10
be 1, this NAND Flash10 does not enable.When this counting terminal 3 is 1, chip enable pin
be 0, this NAND Flash10 enables, and this counter 32 continues counting thereafter.When counting terminal 0-3 count value is 1101, the order latch signal pin CLE of NAND Flash10 enables, and when counting terminal 0-3 count value changes to 1111 from 0011, the address latch signal pin ALE of NAND Flash10 enables.When counter 32 continues counting, 4 set 1 of counting terminal, this hour counter 32 stops counting, and each pin of NAND Flash10 is set to high resistant, and this complete NAND Flash10 initialization.
Incorporated by reference to consulting Fig. 3 and Fig. 4, at the counting terminal 0-3 of counter 32, count down at 0001 o'clock, chip enable pin
low level enables.Its post command latch signal pin CLE enables, and writes enable pin thereupon
aLE enables with address latch signal pin, waits for after one section of time delay, detects pin
start, from high level, transfer low level to and transfer again high level to.After this whenever reading enable pin
be set to low level, CPU50 controls and reads enable pin
from data input and output pin I/O, read one group of Pre-Bootloader data, until run through all Pre-Bootloader data.Last CPU50 reads these Pre-Bootloader data in SDRAM70 by MOV, JUMP instruction, to prepare startup system.
Incorporated by reference to consulting Fig. 5, the method for using this Sheffer stroke gate flash memory starting device 100 to start embedded system device comprises the following steps:
S1: step-by-step counting unit 30 initialization NAND Flash 10;
S2: control pin
by high level, transfer low level to and transfer again high level to;
S3: read enable pin
being set to low level enables;
S4:CPU50 reads enable pin by control
read Pre-Bootloader data and carry out the dependent instruction of Pre-Bootloader;
S5:SDRAM70 initialization;
S6:CPU50 transfers to Pre-Bootloader data in SDRAM70 by MO V instruction;
S7:CPU50 jumps to the entrance operation Bootloader of SDRAM70, startup system.
Be appreciated that the present invention is intended to initialization NAND Flash10, therefore this step-by-step counting unit 30 also can adopt other form to realize, as long as successively make chip enable pin within the step-by-step counting cycle
order latch signal pin CLE and address latch signal pin ALE enable.
The present invention is by step-by-step counting unit 30 initialization NAND Flash10, so that NANDFlash10 passes through to detect pin under the control of CPU50
with read enable pin
the Pre-Bootloader data in NAND Flash10 are read in the change of level, and these data are transferred to SDRAM70, with startup system.This Sheffer stroke gate flash memory starting device 100 can directly start from NAND Flash10, has avoided use NOR Flash, effectively provides cost savings.
Claims (6)
1. a Sheffer stroke gate flash memory starting device, it comprises a central processing unit and the Sheffer stroke gate flash memory and the synchronous DRAM that are electrically connected with this central processing unit, it is characterized in that: one section of described Sheffer stroke gate flash memory pre-stored is for starting the bootstrap loader of system, described Sheffer stroke gate flash memory starting device also comprises a step-by-step counting unit, described step-by-step counting unit and central processing unit are electrically connected, described step-by-step counting unit comprises a counter, one with door, one first not gate and one second not gate, described and door comprises three input ends, described counter comprises counting terminal 0-7, wherein count terminal 0 and counting terminal 1 and be electrically connected at two input ends with door, counting terminal 2 is electrically connected at another input end with door by the first not gate, counting terminal 3 and the second not gate are electrically connected, counting terminal 5 is electrically connected with Sheffer stroke gate flash memory, described step-by-step counting unit is by producing this Sheffer stroke gate flash memory of pulse signal initialization, so that this Sheffer stroke gate flash memory enables, described central processing unit is read described bootstrap loader and this bootstrap loader is transferred to synchronous DRAM by this Sheffer stroke gate flash memory and then starts system.
2. Sheffer stroke gate flash memory starting device as claimed in claim 1, it is characterized in that: described Sheffer stroke gate flash memory comprises that reading enable pin and detects pin, when detecting pin and transferred to low level and transferred to high level again by high level, this central processing unit is controlled and is read enable pin and read described bootstrap loader.
3. Sheffer stroke gate flash memory starting device as claimed in claim 1, is characterized in that: described Sheffer stroke gate flash memory comprises an order latch signal pin, and output terminal described and door is electrically connected with order latch signal pin.
4. Sheffer stroke gate flash memory starting device as claimed in claim 3, it is characterized in that: described Sheffer stroke gate flash memory comprises an address latch signal pin, a chip enable pin and a data input and output pin, described counting terminal 2 is electrically connected with address latch signal pin, described counting terminal 3 is electrically connected by the second not gate and chip enable pin, and described counting terminal 5 is electrically connected with data input and output pin.
5. Sheffer stroke gate flash memory starting device as claimed in claim 1; it is characterized in that: described counter also comprises an interruption terminal and a protection terminal; described interruption terminal is electrically connected at counting terminal 4 with protection terminal simultaneously; when this counting terminal 4 set 1; this counter stops counting, and this protection terminal is set to high resistant.
6. Sheffer stroke gate flash memory starting device as claimed in claim 5, it is characterized in that: described Sheffer stroke gate flash memory comprises writes enable pin, described step-by-step counting unit comprises a counter and a chronotron, described counter comprises a clock terminal, described clock terminal receives the clock signal of central processing unit, this clock terminal by chronotron with write enable pin and be electrically connected.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010251930.6A CN102375745B (en) | 2010-08-12 | 2010-08-12 | Negated AND (NAND) gate flash starting device and using method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010251930.6A CN102375745B (en) | 2010-08-12 | 2010-08-12 | Negated AND (NAND) gate flash starting device and using method thereof |
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| Publication Number | Publication Date |
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| CN102375745A CN102375745A (en) | 2012-03-14 |
| CN102375745B true CN102375745B (en) | 2014-03-26 |
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| CN201010251930.6A Expired - Fee Related CN102375745B (en) | 2010-08-12 | 2010-08-12 | Negated AND (NAND) gate flash starting device and using method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543602A (en) * | 2001-08-06 | 2004-11-03 | System and method for booting from a non-volatile application and file storage device | |
| CN1591369A (en) * | 2003-08-27 | 2005-03-09 | 株式会社日立制作所 | Electronic apparatus and method for starting up system of such apparatus |
| CN101118494A (en) * | 2006-08-01 | 2008-02-06 | 环达电脑(上海)有限公司 | System and method for starting up and operating system from external connected electronic card with built-in equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7257703B2 (en) * | 2003-11-18 | 2007-08-14 | Toshiba America Electronic Components, Inc. | Bootable NAND flash memory architecture |
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2010
- 2010-08-12 CN CN201010251930.6A patent/CN102375745B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1543602A (en) * | 2001-08-06 | 2004-11-03 | System and method for booting from a non-volatile application and file storage device | |
| CN1591369A (en) * | 2003-08-27 | 2005-03-09 | 株式会社日立制作所 | Electronic apparatus and method for starting up system of such apparatus |
| CN101118494A (en) * | 2006-08-01 | 2008-02-06 | 环达电脑(上海)有限公司 | System and method for starting up and operating system from external connected electronic card with built-in equipment |
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| CN102375745A (en) | 2012-03-14 |
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