Accompanying drawing explanation
Fig. 1 illustrates a kind of schematic diagram of supply unit of film liquid crystal display for one embodiment of the invention.
Fig. 2 is for the schematic diagram of two voltage-multiplying circuits is described.
Fig. 3 produces the schematic diagram of the sequential of two multiplication of voltages for explanation.
Fig. 4 is the schematic diagram for explanation voltage tripler.
Fig. 5 produces the schematic diagram of the sequential of three multiplication of voltages for explanation.
Fig. 6 is the schematic diagram for explanation negative electrical charge side Pu.
Fig. 7 produces the schematic diagram of the sequential of negative voltage for explanation.
[primary clustering symbol description]
100 supply units
102 printed circuit board (PCB)s
104 first voltage generation circuits
106 face glasss
108 positive charge side Pus
110 negative electrical charge side Pus
1082 two voltage-multiplying circuits
1084 voltage triplers
1042 power drives unit
1044 transistors
1046 inductance
1048 diodes
1050 electric capacity
1052 loads
1102 the 4th charging capacitors
1104 the 7th thin-film transistors
1106 the 8th thin-film transistors
1108 the 4th electric capacity of voltage regulation
10822 first charging capacitors
10824 the first film transistors
10826 second thin-film transistors
10828 first electric capacity of voltage regulation
10842 second charging capacitors
10844 the 3rd thin-film transistors
10846 the 4th thin-film transistors
10848 second electric capacity of voltage regulation
10850 the 3rd charging capacitors
10852 the 5th thin-film transistors
10854 the 6th thin-film transistors
10856 the 3rd electric capacity of voltage regulation
GND ground end
PS pulse width modulation is controlled signal
PWM pulse width modulation signal
VDDA the first voltage
VDDG2X bis-multiplication of voltages
VDDG3X tri-multiplication of voltages
VEEG negative voltage
VIN input voltage
Embodiment
For making object of the present invention, technical scheme and advantage clearer, below will, by specific embodiment and relevant drawings, the present invention be described in further detail.
Please refer to Fig. 1, Fig. 1 illustrates a kind of schematic diagram of supply unit 100 of film liquid crystal display for one embodiment of the invention.Supply unit 100 comprises a printed circuit board (PCB) 102, one first voltage generation circuit 104, a face glass 106, a positive charge side Pu 108 and negative electrical charge side Pu 110.The first voltage generation circuit 104 is to be formed on printed circuit board (PCB) 102, in order to produce one first voltage VDDA and a pulse width modulation signal PWM; Positive charge side Pu 108 is to be formed on face glass 106, in order to receive the first voltage VDDA and pulse width modulation signal PWM, and according to the first voltage VDDA and pulse width modulation signal PWM, exports two multiplication of voltage VDDG2X and three multiplication of voltage VDDG3X.Positive charge side Pu 108 comprises two voltage-multiplying circuits 1082 and voltage triplers 1084, and wherein two voltage-multiplying circuits 1082 are to export two multiplication of voltage VDDG2X and voltage tripler 1084 is to export three multiplication of voltage VDDG3X.But the present invention is not limited to positive charge side Pu 108 and only exports two multiplication of voltage VDDG2X and three multiplication of voltage VDDG3X.That is positive charge side Pu 108 is multiplication of voltages of exporting at least one the first voltage VDDA.Negative electrical charge side Pu 110 is to be formed on face glass 106, in order to received pulse width modulation signal PWM, and according to pulse width modulation signal PWM, exports a negative voltage VEEG.
As shown in Figure 1, the first voltage generation circuit 104 comprises a power drives unit 1042, a transistor 1044, an inductance 1046, diode 1048, an electric capacity 1050 and a load 1052.Power drives unit 1042 is to provide a pulse width modulation to control signal PS; Transistor 1044 has a first end, and one second end is controlled signal PS in order to received pulse width modulation, and one the 3rd end, is coupled to a ground end GND; Inductance 1046 has a first end, in order to receive an input voltage VIN, and one second end, is coupled to the first end of transistor 1044, in order to output pulse width modulation signal PWM; Diode 1048 has a first end, is coupled to the first end of transistor 1044, and one second end, in order to output-input voltage VIN; Electric capacity 1050 has a first end, is coupled to the second end of diode 1048, and one second end, is coupled to and holds GND; Load 1052 has a first end, is coupled to the second end of diode 1048, and one second end, is coupled to and holds GND.As shown in Figure 1, the first voltage VDDA is for according to pulse width modulation signal PWM and input voltage VIN, sees through under inductance 1046 energy storage and diode 1048 clamps resulting stable state direct voltage.In addition, the work period of pulse width modulation signal PWM is by pulse width modulation, to control signal PS to be controlled.
Please refer to Fig. 2 and Fig. 3, Fig. 2 is for the schematic diagram of two voltage-multiplying circuits 1082 is described, and Fig. 3 produces the schematic diagram of the sequential of two multiplication of voltage VDDG2X for explanation.As shown in Figure 2, two voltage-multiplying circuits 1082 are to receive the first voltage VDDA and pulse width modulation signal PWM, and export according to this two multiplication of voltage VDDG2X.Two voltage-multiplying circuits 1082 comprise one first charging capacitor 10822, a first film transistor 10824, one second thin-film transistor 10826 and one first electric capacity of voltage regulation 10828, and wherein the first charging capacitor 10822 and the first electric capacity of voltage regulation 10828 are the coupling capacitances for face glass 106.The first charging capacitor 10822 has a first end, in order to received pulse width modulation signal PWM, and one second end; The first film transistor 10824 has a first end, and in order to receive the first voltage VDDA, one second end, is coupled to the first end of the first film transistor 10824, and one the 3rd end, is coupled to the second end of the first charging capacitor 10822; The second thin-film transistor 10826 has a first end, is coupled to the second end of the first charging capacitor 10822, and one second end is coupled to the first end of the second thin-film transistor 10826, and one the 3rd end, in order to export two multiplication of voltage VDDG2X; The first electric capacity of voltage regulation 10828 has a first end, is coupled to the 3rd end of the second thin-film transistor 10826, and one second end, is coupled to and holds GND.
As shown in Figures 2 and 3, when pulse width modulation signal PWM is during for an electronegative potential (0V), the first film transistor 10824 opens and the second thin-film transistor 10826 cuts out.Now, the first voltage VDDA is to the first charging capacitor 10822 chargings, so the current potential of node A (the second end of the first charging capacitor 10822) is promoted to the first voltage VDDA.When pulse width modulation signal PWM is during for a high potential (VDDA), the first film transistor 10824 is closed and the second thin-film transistor 10826 is opened.Now, pulse width modulation signal PWM is to the first charging capacitor 10822 charging, so the current potential of node A is promoted to two multiplication of voltage VDDG2X again by the first voltage VDDA, and continues to maintain two multiplication of voltage VDDG2X.Because the second thin-film transistor 10826 is opened, so just exportable two multiplication of voltage VDDG2X of the 3rd end of the second thin-film transistor 10826.In addition, the first electric capacity of voltage regulation 10828 is the current potentials in order to stable node A.
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the schematic diagram for explanation voltage tripler 1084, and Fig. 5 produces the schematic diagram of the sequential of three multiplication of voltage VDDG3X for explanation.As shown in Figure 2, voltage tripler 1084 is to receive the first voltage VDDA and pulse width modulation signal PWM, and exports according to this three multiplication of voltage VDDG3X.Voltage tripler 1084 comprises one second charging capacitor 10842, one the 3rd thin-film transistor 10844, one the 4th thin-film transistor 10846, one second electric capacity of voltage regulation 10848, one the 3rd charging capacitor 10850, one the 5th thin-film transistor 10852, one the 6th thin-film transistor 10854 and one the 3rd electric capacity of voltage regulation 10856, and wherein the second charging capacitor 10842, the second electric capacity of voltage regulation 10848, the 3rd charging capacitor 10850 and the 3rd electric capacity of voltage regulation 10856 are the coupling capacitances for face glass 106.The second charging capacitor 10842 has a first end, in order to received pulse width modulation signal PWM, and one second end; The 3rd thin-film transistor 10844 has a first end, and in order to receive the first voltage VDDA, one second end, is coupled to the first end of the 3rd thin-film transistor 10844, and one the 3rd end, is coupled to the second end of the second charging capacitor 10842; The 4th thin-film transistor 10846 has a first end 48 and has a first end, is coupled to the 3rd end of the 4th thin-film transistor 10846, and one second end, is coupled to and holds GND; The 3rd charging capacitor 10850 has a first end, in order to received pulse width modulation signal PWM, and one second end; The 5th thin-film transistor 10852 has a first end, and in order to receive two multiplication of voltage VDDG2X, one second end, is coupled to the first end of the 5th thin-film transistor 10852, and one the 3rd end, is coupled to the second end of the 3rd charging capacitor 10850; The 6th thin-film transistor 10854 has a first end, is coupled to the second end of the 3rd charging capacitor 10850, and one second end is coupled to the first end of the 6th thin-film transistor 10854, and one the 3rd end, in order to export three multiplication of voltage VDDG3X; The 3rd electric capacity of voltage regulation 10856 has a first end, is coupled to the 3rd end of the 6th thin-film transistor 10854, and one second end, is coupled to and holds GND.
As shown in Figure 4 and Figure 5, when pulse width modulation signal PWM is during for electronegative potential (0V), the 3rd thin-film transistor 10844 and the 5th thin-film transistor 10852 are opened, and the 4th thin-film transistor 10846 and the 6th thin-film transistor 10854 are closed.Now, the first voltage VDDA is to the second charging capacitor 10842 chargings, so the current potential of Node B (the second end of the second charging capacitor 10842) is promoted to the first voltage VDDA.In addition, because the 4th thin-film transistor 10846 cuts out, so the current potential of the 3rd end of the 4th thin-film transistor 10846 is not yet raised.Therefore, although the 5th thin-film transistor 10852 unlatchings, because the current potential of the 3rd end of the 4th thin-film transistor 10846 is not yet raised, so the current potential of node C (the second end of the 3rd charging capacitor 10850) is not also raised.When pulse width modulation signal PWM is during for high potential (VDDA), the 4th thin-film transistor 10846 and the 6th thin-film transistor 10854 are opened, and the 3rd thin-film transistor 10844 and the 5th thin-film transistor 10852 are closed.Now, pulse width modulation signal PWM is to the second charging capacitor 10842 chargings, so the current potential of Node B is promoted to two multiplication of voltage VDDG2X again by the first voltage VDDA.Because the 4th thin-film transistor 10846 is opened, so the current potential of the 3rd end of the 4th thin-film transistor 10846 can be promoted to two multiplication of voltage VDDG2X.In addition, because the second electric capacity of voltage regulation 10848 is current potentials of stablizing the 3rd end of the 4th thin-film transistor 10846, so the sustainable two multiplication of voltage VDDG2X that maintain of the current potential of the 3rd end of the 4th thin-film transistor 10846.
As shown in Figure 4 and Figure 5, when pulse width modulation signal PWM is electronegative potential (0V) again, the 3rd thin-film transistor 10844 and the 5th thin-film transistor 10852 are opened, and the 4th thin-film transistor 10846 and the 6th thin-film transistor 10854 are closed.Now, two multiplication of voltage VDDG2X see through 10852 pairs of the 3rd charging capacitor 10850 chargings of the 5th thin-film transistor of opening, so the current potential of node C is promoted to two multiplication of voltage VDDG2X.When pulse width modulation signal PWM is high potential again, the 4th thin-film transistor 10846 and the 6th thin-film transistor 10854 are opened, and the 3rd thin-film transistor 10844 and the 5th thin-film transistor 10852 are closed.Now, pulse width modulation signal PWM is to the 3rd charging capacitor 10850 chargings, so the current potential of node C can be promoted to three multiplication of voltage VDDG3X again by two multiplication of voltage VDDG2X.Because the 6th thin-film transistor 10854 is opened, so the current potential of the 3rd end of the 6th thin-film transistor 10854 can be promoted to three multiplication of voltage VDDG3X, and export three multiplication of voltage VDDG3X.In addition, because the 3rd electric capacity of voltage regulation 10856 is current potentials of stablizing the 3rd end of the 6th thin-film transistor 10854, so the sustainable three multiplication of voltage VDDG3X that maintain of the current potential of the 3rd end of the 6th thin-film transistor 10854.
Please refer to Fig. 6 and Fig. 7, Fig. 6 is the schematic diagram for explanation negative electrical charge side Pu 110, and Fig. 7 produces the schematic diagram of the sequential of negative voltage VEEG for explanation.As shown in Figure 6, negative electrical charge side Pu comprises one the 4th charging capacitor 1102, one the 7th thin-film transistor 1104, one the 8th thin-film transistor 1106 and one the 4th electric capacity of voltage regulation 1108, and wherein the 4th charging capacitor 1102 and the 4th electric capacity of voltage regulation 1108 are the coupling capacitances for face glass 106.The 4th charging capacitor 1102 has a first end, in order to received pulse width modulation signal PWM, and one second end; The 7th thin-film transistor 1104 has a first end, is coupled to the second end of the 4th charging capacitor 1102, and one second end is coupled to the first end of the 7th thin-film transistor 1104, and one the 3rd end, is coupled to and holds GND; The 8th thin-film transistor 1106 has a first end, and in order to export negative voltage VEEG, one second end, is coupled to the first end of the 8th thin-film transistor 1106, and one the 3rd end, is coupled to the second end of the 4th charging capacitor 1102; The 4th electric capacity of voltage regulation 1108 has a first end, is coupled to the first end of the 8th thin-film transistor 1106, and one second end, is coupled to and holds GND.
As shown in Figure 6 and Figure 7, when pulse width modulation signal PWM is during for electronegative potential (0V), the 7th thin-film transistor 1104 cuts out and the 8th thin-film transistor 1106 is opened.Now, the current potential of the 4th charging capacitor 1102 is 0, and the current potential of node D (the second end of the 4th charging capacitor 1102) is also 0.When pulse width modulation signal PWM is during for high potential (VDDA), the 7th thin-film transistor 1104 opens and the 8th thin-film transistor 1106 cuts out.Now, pulse width modulation signal PWM is to the 4th charging capacitor 1102 chargings, and therefore, the voltage difference at the 4th charging capacitor 1102 two ends is the high potentials (VDDA) for pulse width modulation signal PWM, and the current potential of node D is still 0.When pulse width modulation signal PWM is during for electronegative potential (0V), the 7th thin-film transistor 1104 cuts out and the 8th thin-film transistor 1106 is opened.Now, the current potential of the first end of the 4th charging capacitor 1102 is to be 0V, but because will maintain the voltage difference (VDDA) at the 4th charging capacitor 1102 two ends, so the current potential of node D (the second end of the 4th charging capacitor 1102) can be by clamp down to negative voltage VEEG.Because the 8th thin-film transistor 1106 is opened, so the exportable negative voltage VEEG of the first end of the 8th thin-film transistor 1106.In addition, because the 4th electric capacity of voltage regulation 1108 is current potentials of stablizing the first end of the 8th thin-film transistor 1106, so the sustainable negative voltage VEEG that maintains of the current potential of the first end of the 8th thin-film transistor 1106.
In sum, the supply unit of film liquid crystal display provided by the present invention is to utilize the first voltage generation circuit, produces the first voltage and pulse width modulation signal.Then, positive charge side Pu can produce the multiplication of voltage of at least one the first voltage according to the first voltage and pulse width modulation signal, and negative electrical charge side Pu can, according to pulse width modulation signal, produce negative voltage.In addition, positive charge side Pu and negative electrical charge side Pu are to be integrated on face glass.So, the present invention not only can reduce the external module quantity of supply unit, and because positive charge side Pu and negative electrical charge side Pu are to be integrated on face glass, so the cost of supply unit is lower and need to be compared with the printed circuit board (PCB) of small size.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.