CN102361034B - Vertical selection tube and memory cell formed by vertical selection tube - Google Patents
Vertical selection tube and memory cell formed by vertical selection tube Download PDFInfo
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- CN102361034B CN102361034B CN 201110298199 CN201110298199A CN102361034B CN 102361034 B CN102361034 B CN 102361034B CN 201110298199 CN201110298199 CN 201110298199 CN 201110298199 A CN201110298199 A CN 201110298199A CN 102361034 B CN102361034 B CN 102361034B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 116
- 239000000463 material Substances 0.000 claims description 22
- 230000008859 change Effects 0.000 claims description 20
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910018110 Se—Te Inorganic materials 0.000 claims description 3
- -1 chalcogenide compound Chemical class 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a vertical selection tube. The vertical selection tube comprises a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer, wherein the four layers are formed between an upper electrode and a lower electrode as well as are vertically stacked successively. The first semiconductor layer and the third semiconductor layer are a first type doping; the second semiconductor layer and the fourth semiconductor layer are a second type doping; a gate stack is formed at one side of the third semiconductor layer and the doping density of the third semiconductor layer is lower than doping densities of the second semiconductor layer and the fourth semiconductor layer, so that the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer and the gate stack form a vertical MOS transistor as well as the first semiconductor layer and the second semiconductor layer form a vertical diode. According to the invention, a memory cell structure is formed by the selection tube and a resistance-variable unit or a phase transition unit through series connection, so that problems of crosstalk and electric leakage between adjacent units during memory array operation can be effectively improved; and the vertical selection tube and the memory cell provided in the invention is especially suitable for a high density memory array with a three dimensional stack.
Description
Technical field
The present invention relates to the semiconductor design field, be specifically related to memory technology, particularly a kind of vertical selection pipe and by its memory cell that forms.
Background technology
Resistance-variable storing device (RRAM) and phase transition storage (PCM) be as a kind of novel non-volatile memory technology, owing to its storage density is high, low in energy consumption, read or write speed is fast, data hold time is long, many-valued realization, cellar area, receive much concern with the superior function such as CMOS process compatible.Wherein, can realize the research focus that three-dimensional integrated resistance-variable storing device and phase transition storage become high-density storage.But the multiple-level stack structure of three-dimensional storage causes occurring between the memory cell, between layers crosstalking, leakage current and technique makes the problems such as difficulty.
Existing memory cell mainly comprises 1T1R (One Transistor One Resistor) structure and 1D1R (One Diode One Resistor) structure.A 1T1R structure i.e. MOS transistor is connected with a variable resistor, and transistor plays a part to select and isolation.But transistor belongs to active device, need to finish in front-end process, and the minimum unit area restricts by transistor, is unfavorable for that the density three-dimensional of memory cell is stacking.A 1D1R structure i.e. diode is connected with a variable resistor, by the rectification characteristic realization of the diode selection to resistance.The high forward current density of diode, high switch current ratio and processing compatibility are important choice criteria.Diode electrically current density and the commutating ratio of based single crystal Si material are higher, but technological temperature is higher, and are difficult for making at metal electrode; Though the diode processing compatibility based on oxide is good, forward current density is unsatisfactory.
Therefore, need a kind of selector that has high switch current ratio, is easy to make to become the key of three-dimensional storage.
Summary of the invention
Purpose of the present invention is intended to one of solve the problems of the technologies described above at least, a kind of vertical selection pipe is provided and by the memory cell that it consists of, is applicable to the three-dimensional integrated of resistance-variable storing device and phase transition storage.
For achieving the above object, one aspect of the present invention provides a kind of vertical selection pipe, comprising: top electrode; Bottom electrode; And be formed on semiconductor body between described top electrode and the bottom electrode, wherein, described semiconductor body comprises successively the first semiconductor layer of vertical stacking, the second semiconductor layer, the 3rd semiconductor layer and the 4th semiconductor layer, wherein, described the first semiconductor layer and described the 3rd semiconductor layer are that the first kind is mixed, described the second semiconductor layer and described the 4th semiconductor layer are that Second Type mixes, be formed with grid in a side of described the 3rd semiconductor layer stacking, and the doping content of described the 3rd semiconductor layer is lower than the doping content of described the second semiconductor layer and the 4th semiconductor layer, so that described the second semiconductor layer, the 3rd semiconductor layer, the 4th semiconductor layer and the vertical MOS transistor of the stacking formation of described grid, described the first semiconductor layer forms vertical diode with the second semiconductor layer.
Wherein, the described first kind is doped to the P type or N-type is mixed, and Second Type is doped to N-type or the P type opposite with described first kind doping and mixes.
Wherein, the material of described semiconductor body is the polycrystalline semiconductor material that N-type or P type mix, the polysilicon or the polycrystalline germanium that for example mix.With respect to the monocrystal material that needs the high-temperature technology preparation, polycrystalline material can prepare at a lower temperature by methods such as extensions, therefore adopt the selection Guan Buhui of polycrystalline material preparation to affect its resistive element or other performance of devices.
Wherein, the thickness range of each layer is 10-200nm in the described semiconductor body, and the thickness of described the second semiconductor layer and the 3rd semiconductor layer is greater than the thickness of described the first semiconductor layer and the 4th semiconductor layer.The PNPN of this grid-control selects pipe can be approximately that two parasitic bipolar transistor interact and forms latch-up when causing work, therefore two-layer thickness in the middle of increasing, be equivalent to increase the base thickness of two bipolar tube, thereby reduce the multiplication factor of bipolar tube, suppress latch-up.
Wherein, the course of work of described vertical selection pipe is: to the stacking voltage that applies of described grid, described MOS transistor is opened, simultaneously to described upper and lower electrode application voltage, make described diode forward conducting and form path with described metal-oxide-semiconductor, to realize selecting pipe to open; To the stacking voltage that applies of described grid, described metal-oxide-semiconductor is turn-offed, simultaneously to described upper and lower electrode application voltage, described diode is disconnected, to realize selecting pipe to turn-off.Because described selection pipe is equivalent to the PN junction diode of two anti-partially PN junction diodes and a positively biased and is in series when turn-offing, reverse leakage reduces greatly.
The present invention provides a kind of memory unit on the other hand, comprises resistive element or phase change cells; Aforesaid selection pipe, and described selection pipe is connected mutually with described resistive element or phase change cells.
Wherein, described resistive element or phase change cells are to be formed on the top electrode of described vertical selection pipe or the film storage medium of lower electrode surface.
Wherein, the material of described resistive element comprises Ni
xO
y, Nb
xO
y, Ti
xO
y, Hf
xO
y, Mg
xO
y, Co
xO
y, Cr
xO
y, V
xO
y, Zn
xO
y, Al
xO
y, Zr
xO
y, Al
xN
yDeng, wherein, the scope of x, y is 0-1.
Wherein, the material of described phase change cells comprises the chalcogenide compound of Ge-Se-Te.
The course of work of described memory cell is: when described selection pipe was opened, described resistive element or phase change cells were strobed; When described selection pipe turn-offed, described resistive element or phase change cells were not selected.
Vertically select pipe and this selection pipe formed memory cell structure of connecting with resistive element or phase change cells by grid-control PNPN provided by the invention, crosstalking and the electric leakage problem between the adjacent cells when effectively improving the storage array operation is specially adapted to three-dimensional stacked high density storage array.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment in conjunction with following accompanying drawing, wherein:
Fig. 1 is the structural representation of the vertical selection pipe of the embodiment of the invention;
Fig. 2 is the structural representation of the memory cell of the embodiment of the invention;
Fig. 3 is the principle schematic of vertical selection pipe of the present invention when opening, can be with schematic diagram and equivalent circuit diagram;
Fig. 4 is the principle schematic of vertical selection pipe of the present invention when turn-offing, can be with schematic diagram and equivalent circuit diagram.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
Fig. 1 is the structural representation of the vertical selection pipe of the embodiment of the invention.As shown in Figure 1, vertically select pipe to comprise top electrode 1, bottom electrode 2 and be formed on semiconductor body 3 between the described upper and lower electrode.Semiconductor body 3 comprises from top to bottom successively the first semiconductor layer of vertical stacking, the second semiconductor layer, the 3rd semiconductor layer and the 4th semiconductor layer, wherein, the first semiconductor layer and the 3rd semiconductor layer are that the P type mixes, the second semiconductor layer and the 4th semiconductor layer are that N-type is mixed, it is stacking that the side of the 3rd layer of p type semiconductor layer is formed with grid, stacking gate oxide 4 and the grid 5 of comprising of described grid, the doping content of the 3rd layer of p type semiconductor layer is lower than the second layer and the 4th layer of n type semiconductor layer, be equivalent between the second layer and the 4th layer of n type semiconductor layer, form the structure of the raceway groove of similar MOS transistor, thereby make the second semiconductor layer, the 3rd semiconductor layer, the structure of the similar vertical MOS transistor of the 4th semiconductor layer N-P-N and the stacking formation of described grid, ground floor p type semiconductor layer and second layer n type semiconductor layer form the structure of similar vertical diode, whole vertical selection pipe is equivalent to be formed on, a diode and the MOS transistor of mutual series connection between the bottom electrode select pipe by upper, bottom electrode is electrically connected with other devices.Wherein, the polycrystalline semiconductor material of the material of tagma four-level semiconductor layer for mixing, the polysilicon that for example mixes or the polycrystalline germanium of doping.With respect to the monocrystal material that needs the high-temperature technology preparation, polycrystalline material can prepare at a lower temperature by methods such as extensions, therefore adopt the selection Guan Buhui of polycrystalline material preparation to affect its resistive element or other performance of devices.The thickness range of each layer is 10-200nm.Preferably, the thickness of middle two-layer semiconductor region needs greater than the superiors and undermost semiconductor.The PNPN of this grid-control selects pipe can be approximately that two parasitic bipolar transistor interact and forms latch-up when causing work, therefore two-layer thickness in the middle of increasing, be equivalent to increase the base thickness of two bipolar tube, thereby reduce the multiplication factor of bipolar tube, suppress latch-up.
Be pointed out that, the embodiment of the invention is mixed take the first semiconductor layer and the 3rd semiconductor layer as the P type, the second semiconductor layer and the 4th semiconductor layer are described as N-type is doped to example, in practice, equally can realize the present invention as N-type doping, the second semiconductor layer and the 4th semiconductor layer as the P type mixes take the first semiconductor layer and the 3rd semiconductor layer, not repeat them here.
Fig. 2 is the structural representation of the memory cell of the embodiment of the invention, and as shown in Figure 2, this memory cell comprises resistive element or the phase change cells 7 of vertical selection pipe 6 and series connection with it.In the present embodiment, as the electrode that is connected with resistive element or phase change cells, bottom electrode 2 is as common electrode with the top electrode 1 of selecting pipe 6.Phase change cells or resistive element preferably can be formed in the film storage medium on top electrode 1 surface.Wherein, the material of resistive element comprises Ni
xO
y, Nb
xO
y, Ti
xO
y, Hf
xO
y, Mg
xO
y, Co
xO
y, Cr
xO
y, V
xO
y, Zn
xO
y, Al
xO
y, Zr
xO
y, Al
xN
yCompound-material or other polymeric materials such as (scope of x, y are between 0-1), especially wherein binary metal oxide or nitride scarcely need high temperature in preparation, and film forming thickness easy to control, therefore be the preferred material of the group change unit of the embodiment of the invention.The material of phase change cells comprises the chalcogenide compound of Ge-Se-Te etc.Part shown in dotted line circle among the figure is a memory cell 8.Upper and lower side in this memory cell is connected with respectively common electrode 9, and wherein the bottom electrode 2 of vertical selection pipe 6 can be used as lower common electrode wherein.The material of electrode can be for polysilicon or other electrode materials that mixes, such as metal materials such as TiN.Two common electrodes up and down are orthogonal, for a plurality of memory cell share, form the storage array of intersection dot matrix.
Fig. 3 is the principle schematic of vertical selection pipe of the present invention when opening, can be with schematic diagram and equivalent circuit diagram.When grid applies suitable positive voltage+VG, portions of electronics about near the gate interface place of the 3rd floor p type semiconductor layer electronics and this floor in the two semiconductor layer N districts can attract move to gate interface owing to grid voltage, form gradually the electron channel 10 of transoid, it is the N-zone, as shown in phantom in FIG., the metal-oxide-semiconductor that then is positioned at the bottom is opened.Respectively apply suitable positive bias-voltage at the upper/lower electrode of selecting pipe this moment, for example top electrode applies+V1 voltage, bottom electrode apply earthed voltage or-V2 voltage, the PN diode forward conducting on top, then form top-down electric field in the tagma of selecting pipe, the electrons in tagma is under the effect of this electric field, and flowing of orientation namely forms the gating firing current Jon that flows from the top down from bottom to top.Along the principle that also reflects this unlatching in the energy band diagram of A-A ' direction: after applying positive grid voltage, transoid becomes the N-district near the gate interface of the 3rd floor p type semiconductor layer, and Ec and top of valence band Ev are downward at the bottom of the conduction band; Upper/lower electrode apply the V1+V2 that voltage forms voltage and, so that downward in various degree bending all appears in be with of upper strata P type and N-type tagma, at this moment, the potential barrier reduction that electronics need to be crossed, the electronics of formation from bottom N district to top layer P district is mobile.Selection pipe during unlatching can equivalence be the metal-oxide-semiconductor of a unlatching of diode series connection of a forward conduction, shown in equivalent circuit diagram.Select the resistance of pipe very little after opening, so also only be a minimum part to the alive dividing potential drop of upper/lower electrode, the voltages of the overwhelming majority will drop on resistive element or the phase change cells, thereby realize that this selection manages the gating of the memory cell at place.
Fig. 4 be when selecting pipe to turn-off principle schematic, can be with schematic diagram and equivalent circuit diagram.When grid applies earthed voltage or when floating empty, gate interface does not form the electron channel of transoid in the 3rd layer of p type semiconductor layer, and the metal-oxide-semiconductor that then is positioned at the bottom is not opened.Respectively apply suitable reversed bias voltage at the upper/lower electrode of selecting pipe this moment, for example top electrode applies-V3 voltage, bottom electrode apply earthed voltage or+V4 voltage, the PN diode that the two-layer P-N semiconductor layer of the PN diode that the two-layer P-N semiconductor layer in top forms and bottom forms is all partially anti-, form anti-partially depletion region 11, minimum pull-down current J is only arranged
OffFlow through.At this moment, although the diode that middle two-layer N-P semiconductor layer forms is positively biased at this moment, because the anti-inclined to one side diode of respectively connecting up and down, whole selection pipe still turn-offs.That flow through the selection pipe this moment is reverse leakage current J
Off, less than general back biased diode.Along also finding out in the energy band diagram of B-B ' direction, grid is making alive not, upper/lower electrode apply the V3+V4 that voltage forms voltage and, so that being with of lower floor's n type semiconductor layer is bent downwardly, being with of top layer n type semiconductor layer slightly is bent upwards, and at this moment, the potential barrier that electronics, hole need to be crossed increases, be difficult to from up to down flow, shown in dotted line direction in the energy band diagram.Selection pipe during shutoff can equivalence be the diode that is in series three " end to end ", shown in equivalent circuit diagram.Have no progeny and select the resistance of pipe very large in the pass, leakage current is very little, very large to the alive dividing potential drop of upper/lower electrode institute, thereby realize the shutoff of the memory cell at this selection pipe place, and namely the memory cell at this selection pipe place is not chosen.
Vertically select pipe and this selection pipe formed memory cell structure of connecting with resistive element or phase change cells by grid-control PNPN provided by the invention, the selector that realization has high switch current ratio, is easy to make, crosstalking and the electric leakage problem between the adjacent cells when effectively improving the storage array operation is specially adapted to three-dimensional stacked high density storage array.
Although illustrated and described embodiments of the invention, those having ordinary skill in the art will appreciate that: in the situation that do not break away from principle of the present invention and aim can be carried out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is limited by claim and equivalent thereof.
Claims (11)
1. the vertical pipe of selecting is characterized in that, comprising:
Top electrode;
Bottom electrode; And
Be formed on the semiconductor body between described top electrode and the bottom electrode, wherein, described semiconductor body comprises successively the first semiconductor layer of vertical stacking, the second semiconductor layer, the 3rd semiconductor layer and the 4th semiconductor layer, wherein, described the first semiconductor layer and described the 3rd semiconductor layer are that the first kind is mixed, described the second semiconductor layer and described the 4th semiconductor layer are that Second Type mixes, be formed with grid in a side of described the 3rd semiconductor layer stacking, and the doping content of described the 3rd semiconductor layer is lower than the doping content of described the second semiconductor layer and the 4th semiconductor layer, so that described the second semiconductor layer, the 3rd semiconductor layer, the 4th semiconductor layer and the vertical MOS transistor of the stacking formation of described grid, described the first semiconductor layer forms vertical diode with the second semiconductor layer.
2. vertical selection pipe as claimed in claim 1 is characterized in that, the described first kind is doped to the P type or N-type is mixed, and Second Type is doped to N-type or the P type opposite with described first kind doping and mixes.
3. vertical selection pipe as claimed in claim 1 is characterized in that, polysilicon or the polycrystalline germanium of the material of described semiconductor body for mixing.
4. vertical selection pipe as claimed in claim 1 is characterized in that, the thickness range of each layer is 10-200nm in the described semiconductor body.
5. such as each described vertical selection pipe of claim 1-4, it is characterized in that: the thickness of described the second semiconductor layer and the 3rd semiconductor layer is greater than the thickness of described the first semiconductor layer and the 4th semiconductor layer.
6. vertical selection pipe as claimed in claim 5 is characterized in that:
To the stacking voltage that applies of described grid, described MOS transistor is opened, simultaneously to described upper and lower electrode application voltage, make described diode forward conducting and form path with described metal-oxide-semiconductor, to realize selecting pipe to open;
To the stacking voltage that applies of described grid, described metal-oxide-semiconductor is turn-offed, simultaneously to described upper and lower electrode application voltage, described diode is disconnected, to realize selecting pipe to turn-off.
7. memory cell comprises:
Resistive element or phase change cells;
Select pipe, described each described vertical selection pipe of selection Guan Weiru claim 1-6, and described selection pipe is connected mutually with described resistive element or phase change cells.
8. the memory cell of stating such as claim 7 is characterized in that, described resistive element or phase change cells are to be formed on the top electrode of described vertical selection tubular construction or the film storage medium of lower electrode surface.
9. memory cell as claimed in claim 7 is characterized in that, the material of described resistive element comprises Ni
xO
y, Nb
xO
y, Ti
xO
y, Hf
xO
y, Mg
xO
y, Co
xO
y, Cr
xO
y, V
xO
y, Zn
xO
y, Al
xO
y, Zr
xO
y, Al
xN
y, wherein, the scope of x, y is 0-1.
10. memory cell as claimed in claim 7 is characterized in that, the material of described phase change cells comprises the chalcogenide compound of Ge-Se-Te.
11. memory cell as claimed in claim 7 is characterized in that:
When described selection pipe was opened, described resistive element or phase change cells were selected;
When described selection pipe turn-offed, described resistive element or phase change cells were not selected.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110298199 CN102361034B (en) | 2011-09-29 | 2011-09-29 | Vertical selection tube and memory cell formed by vertical selection tube |
| US13/520,166 US8748934B2 (en) | 2011-09-29 | 2012-03-12 | Vertical selection transistor, memory cell, and three-dimensional memory array structure and method for fabricating the same |
| PCT/CN2012/072213 WO2013044612A1 (en) | 2011-09-29 | 2012-03-12 | Vertical selection transistor, memory cell, and three-dimensional memory array structure and method for fabricating the same |
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|---|---|---|---|
| CN 201110298199 CN102361034B (en) | 2011-09-29 | 2011-09-29 | Vertical selection tube and memory cell formed by vertical selection tube |
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| CN102361034A CN102361034A (en) | 2012-02-22 |
| CN102361034B true CN102361034B (en) | 2013-03-06 |
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| WO2013044612A1 (en) * | 2011-09-29 | 2013-04-04 | Tsinghua University | Vertical selection transistor, memory cell, and three-dimensional memory array structure and method for fabricating the same |
| KR102295524B1 (en) * | 2017-03-27 | 2021-08-30 | 삼성전자 주식회사 | Memory device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331724B1 (en) * | 1995-11-17 | 2001-12-18 | Nippon Precision Circuits, Inc. | Single transistor E2prom memory device with controlled erasing |
| CN101393945A (en) * | 2007-09-19 | 2009-03-25 | 中国科学院半导体研究所 | Full silicon waveguide type photoelectric converter and manufacturing method thereof |
| CN101834210A (en) * | 2010-04-28 | 2010-09-15 | 复旦大学 | PNPN (Positive-Negative-Positive-Negative) field effect transistor of sinking channel and preparation method thereof |
| CN102097477A (en) * | 2010-12-15 | 2011-06-15 | 复旦大学 | MIS (metal-insulator-semiconductor) and MIM (metal-insulator-metal) device provided with gate |
-
2011
- 2011-09-29 CN CN 201110298199 patent/CN102361034B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6331724B1 (en) * | 1995-11-17 | 2001-12-18 | Nippon Precision Circuits, Inc. | Single transistor E2prom memory device with controlled erasing |
| CN101393945A (en) * | 2007-09-19 | 2009-03-25 | 中国科学院半导体研究所 | Full silicon waveguide type photoelectric converter and manufacturing method thereof |
| CN101834210A (en) * | 2010-04-28 | 2010-09-15 | 复旦大学 | PNPN (Positive-Negative-Positive-Negative) field effect transistor of sinking channel and preparation method thereof |
| CN102097477A (en) * | 2010-12-15 | 2011-06-15 | 复旦大学 | MIS (metal-insulator-semiconductor) and MIM (metal-insulator-metal) device provided with gate |
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Effective date of registration: 20190709 Address after: 361022 Unit 0206, Unit 109, 62 Chengyi North Street, Xiamen Software Park Phase III, Fujian Province Patentee after: Xiamen Semiconductor Industry Technology Research and Development Co., Ltd. Address before: 100084 Haidian District 100084-82 mailbox in Beijing Patentee before: Tsinghua University |