CN102355262A - Control method for mixing digital-to-analogue converter (DAC) switching circuit - Google Patents

Abstract

The invention discloses a control method for a mixing digital-to-analogue converter (DAC) switching circuit. The control method comprises that: a DAC switching circuit is constructed, wherein the DAC switching circuit comprises a unit decoding circuit, a mode selection circuit and a switch array; the unit decoding circuit decodes an input digital signal and outputs the signal to the mode selection circuit; the mode selection circuit selects an output mode of the switch array according to a mode control signal, converts the signal input by the unit decoding unit into a switching selection signal according to the output mode and outputs the switching selection signal to the switch array; and the switch array generates analogue output according to the switching selection signal. By the control method, the shortcomings that the output noises of a conventional high-performance DAC are relatively more dependent on input control switching signals and that an output signal frequency range is limited are overcome, the static linearity of the DAC is improved, the dynamic range of the static linearity is widened, the function of multimode up-conversion is realized at the same time, and the DAC is endowed with the function of a mixer.

Description

A kind of control method of mixer/dac on-off circuit

Technical field

The present invention relates to a kind of control method of mixer/dac on-off circuit.

Background technology

In the design of electronic circuit, noise problem increasingly becomes the bottleneck of design, it can with dynamic range increase and signal energy step-down and be on the rise.In mixed-signal applications, being continually changing for data signal is to influence the main noise source of analog signal normal work.In digital analog converter DAC, the switch of control analog signal output is by Digital Signals.The data signal being continually changing will produce noise in simulation output part.It is these impossible completely isolated noises in actual achievable system, because they be coupled to by the control unit of analog signal it is therein, also because the intrinsic power consumption of digital circuit, the temporal correlation and its resistance drop and Charge injection effect of load, these will cause reference signal, supply voltage, bias voltage, clock phase, the change of transition region phase and body effect, and produce noise in output.Because inevitable parasitic problems and non-ideal circuitry will cause to load the modulation problems that signal is coupled to the dependence and clutter of data in change, so data signal will add noise to analog signal in this manner.

Except noise problem, commonly used in some traditional electronic equipments is such a system, and data signal is transformed into after analog signal, then carry out analog signal move process.As in traditional mobile phone, generally convert digital signals into analog signal with a DAC chip and send out, but need a mixer chip to be gone in the frequency of the frequency translation of baseband signal to suitable transmitting before transmission.So it is probably poorly efficient to complete such a function using two or more chips.

The process that DAC converts digital signals into analog signal is to keep the value of digital input signals to realize by the clock cycle in each conversion.And such a holding process is realized by switch, what switch function and input signal were completed is the process of convolution in time domain, and in frequency domain switching signal complete be filtering modulation to input signal process.

Although traditional Double deference construction of switch has the ability to eliminate the nonlinear problem caused by undesirable switch, for those it is related to input data it is non-linear for have little effect.The frequency of the signal of output can be only positioned at the first Nyquist scope simultaneously, and upconversion function can not be realized to output signal.

The content of the invention

The technology of the present invention solves problem：Overcoming the deficiencies in the prior art, there is provided a kind of control method of mixer/dac on-off circuit.Solve traditional high-performance DAC output noises using the present invention has the shortcomings that compared with strong dependency to input controlling switch signal, solve the limited deficiency of its output signal frequency scope, not only increase DAC static linear degree and its dynamic range, the function of various modes up-conversion is realized simultaneously, makes DAC while being provided with the function of frequency mixer.

The present invention technical solution be：

A kind of control method of mixer/dac on-off circuit, the frequency conversion during the data signal of achievable input is turned over to analog signal is exported, and is controlled by following steps：

(1) DAC switch single channel is built, the DAC switches single channel includes：Unit decoding circuit, mode selection circuit and switch arrays, the input and the data signal D of input of the unit decoding circuit, and the clock signal clk of input are connected；The input of the mode selection circuit and 8 tunnel output signal V1~V8 of unit decoding circuit, and mode control signal E1~E3 are connected；The switch arrays are made up of 8 metal-oxide-semiconductor S1~S8, S1~S8 source electrode is connected with current source, S1~S8 grid is connected with switch selection signal G1~G8 by sequence number is corresponding respectively, wherein, S1, S3, S5, S7 are one group, it is another group that S1, S3, S5, S7 drain electrode, which are connected to form output end Ip, S2, S4, S6, S8, and S2, S4, S6, S8 drain electrode are connected to form output end In；

(2) when unit decoding circuit has data signal D inputs, enter row decoding to the clk_S90 of D, clk and clk after 90 ° of phase shifts to cause within clock signal clk every 1/4 cycle, 1 road useful signal output and 7 road invalid signals outputs are produced, and output signal V1~V8 of generation is output to mode selection circuit；

(3) mode selection circuit is when receiving V1~V8 of input, while selecting the switch selection signal for determining switch arrays output mode according to the mode control signal of input E1~E3；The switch arrays output mode includes：Normal mode, back to zero pattern, two-way bipolarity level mode, four phase bipolarity level moulds Formula and the polarity level mode of four phase three；

If output mode is normal mode, in a cycle, switch selection signal only makes one group of switch in the conduction state all the time；

If output mode is back to zero pattern, in one cycle, switch selection signal makes one group of switch in the conduction state in preceding half period, two groups of switches is in closed mode in second half of the cycle；

If output mode is two-way bipolarity level mode, in one cycle, switch selection signal makes one group of switch in the conduction state in preceding half period, makes another group of switch in the conduction state in second half of the cycle；

If the phase bipolarity level mode of output mode signal behavior four, in one cycle, switch selection signal makes one group of switch in the conduction state in the 1/4th cycle and the 3/4th cycle, makes another group of switch in the conduction state in the 2/4th cycle and the 4/4th cycle；

If the polarity level mode of four phase of output mode signal behavior three, then in one cycle, switch selection signal makes two groups of switches successively in the conduction state respectively in the 1/4th cycle and the 3/4th cycle, two groups of switches is in closed mode in the 2/4th cycle and the 4/4th cycle；

(4) switch arrays receive the switch selection signal G1~G8 exported by mode selection circuit, and according to switch selection signal G1~G8 generations analog output signal corresponding with input data signal D；Switch arrays are according to switch selection signal G1~G8 output rule：

When any one in G1, G3, G5, G7 is effective, then corresponding metal-oxide-semiconductor will be turned in S1, S3, S5, S7, and S2, S4, S6, S8 are turned off, and Ip exports corresponding analog quantity, and In is without output；

When any one in G2, G4, G5, G8 is effective, then corresponding metal-oxide-semiconductor will be turned in S2, S4, S6, S8, and S1, S3, S5, S7 are turned off, and In exports corresponding analog quantity, and Ip is without output.

The present invention has the following advantages that compared with prior art：

1st, the technology solves the shortcoming that the output noise of traditional double difference switch-dividing presence is relied on input signal, pass through the conducting state of metal-oxide-semiconductor in switch selection signal selecting switch array, realized by the output of different switches by noise to the conversion of fixed frequency burr, improve the static linear degree and dynamic range of output.

2nd, the problem of present invention solves limited four switching techniques variable mode of the prior art and not enough frequency conversion frequency band, can be achieved the frequency conversion output of five kinds of patterns, the analog signal of output is covered first to the 5th all intervals of Nyquist.

3rd, the present invention realizes to input conversion of the data signal to analog signal and the mixing function to analog signal by the combination of unit decoding circuit, mode selection circuit and switch arrays, reduces the design difficulty of baseband transmitter.

Brief description of the drawings

Fig. 1 is circuit diagram of the present invention；

Fig. 2 is unit decoding circuit structure figure；

Fig. 3 is mode selection circuit structure chart；

Fig. 4 is different output mode oscillograms；

Fig. 5 is different output mode switch function spectrograms；

Fig. 6 is flow chart of the present invention.

Embodiment

Just the present invention is described further with reference to accompanying drawing below.

It is as follows, it is the english abbreviation explanation of the present invention：

DAC：Digital to Analog Converter, digital-to-analog converter

RZ：Return to zero, back to zero

BPBL：Biphase Bipolar Level, two-way bipolar level

QPBL：Quad-phase Bipolar level, four mutually bipolar level

QPTL：Quad-phase triple level, the pole level of four phase three

Nyquist：Nyquist

It is flow chart of the present invention such as Fig. 6.The first step：Build DAC switch single channel；Second step：Unit decoding circuit is decoded；3rd step：The carry out model selection of mode selection circuit；4th step：Switch arrays are exported.Just it is introduced respectively below.

(1) DAC switch single channel is built

As shown in figure 1, being circuit diagram of the present invention.Circuit includes：Unit decoding circuit, mode selection circuit and switch arrays.

Unit decoding circuit input and the data signal D of input, and the clock signal clk of input are connected, and output end is used to export decoding output signal V1~V8.The input of mode selection circuit is connected with the output end of unit decoding circuit, receives decoding output signal V1~V8, meanwhile, mode selection circuit also there are three tunnels to be used for reception pattern control signal E1~E3 input.The output end of mode selection circuit is used for 8 way switch selection signal G1~G8 of output control switch array.Switch arrays are made up of 8 metal-oxide-semiconductor S1~S8, and same G1~G8's S1~S8 grid is connected on demand respectively.

(2) unit decoding circuit interpretation method

The input signal of unit decoding circuit is data signal D and clock signal clk, producing 8 road decoding output signal V1~V8 by decoding was used within every 1/4 cycle, 1 metal-oxide-semiconductor conducting of selection, 7 metal-oxide-semiconductors are closed, it is that the design method of this element decoding circuit is as follows even if 1 road useful signal and 7 road invalid signals will be included in the V1~V8 exported every time：

If 1 road useful signal is defined as logical zero, invalid signals are defined as logical one, and 90 ° of phase shifts are carried out to the clock signal clk of input, so that it is D, clk and clk_90 to constitute three tunnels decoding input signal.

When it is 1,1,0 that D, clk, clk_S90, which divide, if selection allows V1 effectively, V2~V8 is invalid, the Karnaugh map according to table 1, and we select to enclose " 0 ", therefore

So

When D, clk, clk_S90 are respectively 010,111,011,101,001,100,000, V2~V8 is allowed to sequentially turn on, application Kano primitive is managed successively, is proposed decoding circuit module.

Table 1

As shown in Fig. 2 being a kind of way of realization of unit decoding circuit, the decoding relation of realization is as follows：

(3) mode selecting method of mode selection circuit

Mode selection circuit determines the output mode of switch arrays under mode control signal E1~E3 control, and decoding output signal V1~V8 of input is selected to G1~G8 output.The present invention receives mode control signal E1~E3 of input using three or eight decoders, the PMOS t1-t14 in mode selection circuit as shown in Figure 3 is controlled using five output signals of three or eight decoders, MUX in Fig. 3 is alternative data selector, V1~V8 and PMOS t1-t14 annexation such as Fig. 3.

As E1E2E3=000, D1=0, other four output signals are 1.Therefore switch t1-t8 conductings, other switch cut-offs, it is output as normal mode.

In a cycle of normal mode, switch selection signal only makes one group of switch in the conduction state all the time.The switch function P of normal mode_ZRH(t) it is as follows：

$P_{\mathrm{ZRH}}\left(t\right)=\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=\left\{\begin{array}{c}\mathrm{1,0}<t<T_R\\ 0,t<0\mathrm{ort}>T_R\end{array}\right.,$

$P_{\mathrm{ZRH}}\left(t\right)=\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=u\left(t\right)-u(t-T_R),$

Wherein, T_RFor the clock cycle,

P_ZRH(t) Laplace transform is as follows：

$L\left\{\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)\right\}=L\{u\left(t\right)-u(t-T_R)\}=\frac{1}{s}-\frac{1}{s}{e}^{-s{T}_R}=\frac{1-e^{-s{T}_R}}{s},$

Fourier transformation is as follows：

$F\left\{\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)\right\}=T_R\frac{e^{\mathrm{jw}\frac{T_R}{2}}-e^{-\mathrm{jw}\frac{T_R}{2}}}{2\mathrm{jw}\frac{T_R}{2}}{e}^{-\mathrm{jw}\frac{T_R}{2}}=T_R\frac{\sin \left(w\frac{T_R}{2}\right)}{w\frac{T_R}{2}}{e}^{-\mathrm{jw}\frac{T_R}{2}}$

$=T_R\mathrm{Sa}\left(w\frac{T_R}{2}\right)e^{-\mathrm{jw}\frac{T_R}{2}}=P_{\mathrm{ZRH}}\left(w\right)$

According to the property of sampling function, work as w=nw_R, (n ∈ z, n ≠ 0), sampling function have a zero point, and whole function amplitude envelops with -20dB/Decade or -6dB/Octant reduced rate.Nyquist frequency is W_R/2。

As E1E2E3=001, D2=0, other four output signals are 1.Therefore switch t1-t4, t10 and t11 conducting, export BPBL patterns.

In a cycle of BPBL patterns, switch selection signal makes one group of switch in the conduction state in preceding half period, makes another group of switch in the conduction state in second half of the cycle

Switch function P_BPBL(t) it is as follows：

Its Fourier transformation is

$F\left\{P_{\mathrm{BPBL}}\left(t\right)\right\}=\frac{1-2e^{-s{T}_R/2}+e^{-s{T}_R}}{s}{|}_{s=\mathrm{jw}}=\frac{1-2e^{-\mathrm{jw}{T}_R/2}+e^{-\mathrm{jw}{T}_R}}{\mathrm{jw}}$ , then

$=\frac{{(1-e^{-\mathrm{jw}{T}_R/2})}^2}{\mathrm{jw}}=T_R\frac{{\sin }^2(w{T}_R/4)}{w{T}_R/4}{e}^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}$

$F\left\{P_{\mathrm{BPBL}}\left(t\right)\right\}=P_{\mathrm{BPBL}}\left(w\right)=T_R\mathrm{Sa}\left(\mathrm{\&pi;}\frac{w}{2w_R}\right)\sin \left(\mathrm{\&pi;}\frac{w}{2w_R}\right)e^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}$

The amplitude spectrum of switch function completely inhibit direct current signal under this pattern, larger to inhibit the interval frequency spectrum of the first Nyquist, it is of a relatively high enhance second and the 3rd Nyquist spectral amplitude, particularly second Nyquist zone has obtained comparatively flat enhancing.

As E1E2E3=010, D3=0, other four output signals are 1.Therefore switch t1, t2, t5, t6, t9 and t11 conducting, export QPBL patterns.

In a cycle of QPBL patterns, switch selection signal makes one group of switch in the conduction state in the 1/4th cycle and the 3/4th cycle, makes another group of switch in the conduction state in the 2/4th cycle and the 4/4th cycle.

Switch function P_QPBL(t) r is as follows：

$P_{\mathrm{QPBL}}\left(t\right)=u\left(t\right)-2u(t-\frac{T_R}{4})+2u(t-\frac{T_R}{2})-2u(t-\frac{3T_R}{4})+u(t-T_R)$

Fourier transformation is

$F\left\{P_{\mathrm{QPBL}}\left(t\right)\right\}=\frac{1+2e^{-s{T}_R/2}-2e^{-s{T}_R/4}-2e^{-3s{T}_R/4}+e^{-s{T}_R}}{s}){|}_{s=\mathrm{jw}}$

$=\frac{{(e^{s{T}_R/8}-e^{-s{T}_R/8})}^2(e^{s{T}_R/4}+e^{-s{T}_R/4})}{s}{e}^{-s{T}_R/2}{|}_{s=\mathrm{jw}}$

$F\left\{P_{\mathrm{QPBL}}\left(t\right)\right\}=T_R\frac{\sin (w{T}_R/8)}{w{T}_R/8}\sin (w{T}_R/8)\cos (w{T}_R/4)e^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}$

$=T_R\mathrm{Sa}\left(\mathrm{\&pi;}\frac{w}{4w_R}\right)\sin \left(\mathrm{\&pi;}\frac{w}{4w_R}\right)\cos \left(\mathrm{\&pi;}\frac{w}{2w_R}\right)e^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}$

The main frequency spectrum for enhancing the four, the 5th Nyquist zones under this pattern.

As E1E2E3=011, D4=0, other four output signals are 1.Therefore switch t1-t8, t13, t14 conducting, export RZ patterns.

In a cycle of RZ patterns, switch selection signal makes one group of switch in the conduction state in preceding half period, two groups of switches is in closed mode in second half of the cycle.

The switch function P of RZ patterns_RZ(t) it is as follows：

$P_{\mathrm{RZ}}\left(t\right)=\underset{(0,T_R/2)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=\left\{\begin{array}{c}\mathrm{1,0}<t<T_R/2\\ 0,t<0\mathrm{ort}>T_R/2\end{array}\right.,$ Therefore

$P_{\mathrm{RZ}}\left(t\right)=\underset{(0,T_R/2)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=u\left(t\right)-u(t-T_R/2),$ Fourier transformation is

$F\left\{\underset{(0,T_R/2)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)\right\}=\frac{T_R}{2}\frac{e^{\mathrm{jw}\frac{T_R}{4}}-e^{-\mathrm{jw}\frac{T_R}{4}}}{2\mathrm{jw}\frac{T_R}{4}}{e}^{-\mathrm{jw}\frac{T_R}{4}}$

$=\frac{T_R}{2}\mathrm{Sa}\left(w\frac{T_R}{4}\right)e^{-\mathrm{jw}\frac{T_R}{4}}=P_{\mathrm{RZ}}\left(w\right)$

The Frequency spectrum ratio zeroth order of back to zero pattern keeps the spectral bandwidth of pattern to add 1 times, while amplitude is reduced to half, therefore the former is suppressed relative to the first Nyquist spectral of the latter, and the frequency spectrum of the 2nd the 3rd Nyquist is strengthened.

As E1E2E3=100, D5=0, other four output signals are 1.Therefore switch t1-t4, t7, t8, t10, t12, t14 conducting, export QPTL patterns.

In a cycle of QPTL patterns, switch selection signal makes two groups of switches successively in the conduction state respectively in the 1/4th cycle and the 3/4th cycle, two groups of switches is in closed mode in the 2/4th cycle and the 4/4th cycle.

The switch function P of QPTL patterns_QPTL(t) it is as follows：

$P_{\mathrm{QPTL}}\left(t\right)=\underset{(0,T_R/4)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)-\underset{(0,T_R/4)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=u\left(t\right)-u(t-\frac{T_R}{4})-u(t-\frac{T_R}{2})+u(t-\frac{3T_R}{4})$

Fourier transformation is

$F\left\{P_{\mathrm{QPTL}}\left(t\right)\right\}=\frac{1-e^{-s{T}_R/2}-e^{-s{T}_R/4}+e^{-3s{T}_R/4}}{s}){|}_{s=\mathrm{jw}}$

$=\frac{(e^{s{T}_R/8}-e^{-s{T}_R/8})(e^{s{T}_R/4}-e^{-s{T}_R/4})}{s}{e}^{-3s{T}_R/8}{|}_{s=\mathrm{jw}}$

$F\left\{P_{\mathrm{QPTL}}\left(t\right)\right\}=\frac{T_R}{2}\frac{\sin (w{T}_R/8)}{w{T}_R/8}\sin (w{T}_R/4)e^{\mathrm{j\&pi;}/2-j3w{T}_R/8}$

$=\frac{T_R}{2}\mathrm{Sa}\left(\mathrm{\&pi;}\frac{w}{4w_R}\right)\sin \left(\mathrm{\&pi;}\frac{w}{2w_R}\right)e^{\mathrm{j\&pi;}/2-j3w{T}_R/8}$

The amplitude spectrum of this pattern than two-way bipolar amplitude spectrum preferably enhance second and the 3rd Nyquist area amplitude spectrum.

(4) output control of the switch arrays under switch selection signal

As described above, switch arrays are made up of 8 metal-oxide-semiconductor S1~S8.In S1~S8, S1~S8 Source electrode be connected with current source, S1~S8 grid is connected with switch selection signal G1~G8 by sequence number is corresponding respectively, wherein, S1, S3, S5, S7 are one group, S1, S3, S5, S7 drain electrode are connected to form output end Ip, S2, S4, S6, S8 are another group, and S2, S4, S6, S8 drain electrode are connected to form output end In.

Output rule in the case where switch selection signal G1~G8 is controlled is：

Imitated output quantity is standardized as 1 by we, without being output as 0

When any one in G1, G3, G5, G7 is effective, then corresponding metal-oxide-semiconductor will be turned in S1, S3, S5, S7, and S2, S4, S6, S8 are turned off, and Ip exports corresponding analog quantity, and In is+1 without output, then difference output；

When any one in G2, G4, G5, G8 is effective, then corresponding metal-oxide-semiconductor will be turned in S2, S4, S6, S8, and S1, S3, S5, S7 are turned off, and In exports corresponding analog quantity, and Ip is -1 without output, then difference output.

With reference to foregoing circuit, table 2 below gives the output relations of D, clk, clk_90, V1~V8 in each mode：

D clk clk_S90	110	111	101	100	010	011	001	000
									V1	0	1	1	1	1	1	1	1
V2	1	1	1	1	0	1	1	1
									V3	1	0	1	1	1	1	1	1
V4	1	1	1	1	1	0	1	1
									V5	1	1	0	1	1	1	1	1
V6	1	1	1	1	1	1	0	1
									V7	1	1	1	0	1	1	1	1
V8	1	1	1	1	1	1	1	0
									Normal output	+1	+1	+1	+1	-1	-1	-1	-1
QPBL output	+1	-1	+1	-1	-1	+1	-1	+1
									BPBL output	+1	+1	-1	-1	-1	-1	+1	+1
QPTL output	+1	0	-1	0	-1	0	+1	0
									RZ output	+1	+1	0	0	-1	-1	0	0

Table 2

Fig. 4 gives the oscillogram under each output mode under different D, clk, clk_90.It is can be seen that with reference to table 2 and Fig. 4 when input data is not changing in two continuous clock cycles, decoding circuit will be The data of change are introduced on switch, but output state can't be changed.When data are changing two continuous clock cycle, the change of control data causes the change of output state on switch.It can be seen that, no matter whether input data changes, signal clock ceaselessly complementary change and the not change with input data mode change on switch, burr so associated with the data is just converted into the burr of the clutter of a fixed frequency, he is 4 times of clock frequency, it is a high frequency spurs, he is easily filtered out away from conventional available signal frequency band.

Fig. 5 is given under all output modes, spectrogram of the switch function under frequency domain.It can be seen that full cycle zeroth order keeps rectangular pulse to be that the frequency spectrum exported under normal patterns is most strong in+1Nyquist areas, here it is the base band Nyquist areas that routine DAC is worked.The spectral amplitude in other Nyquist areas is by greater attenuation.Relative+1Nyquist the spectrums with Normal patterns of+1 area Nyquist spectral amplitude are inhibited under RZ patterns, and the spectral amplitude in+2 ,+3Nyquist areas is relative with being strengthened under Normal patterns.BPBL amplitude spectrum completely inhibit direct current signal, significantly inhibits the spectrum amplitude in+1Nyquist areas and relatively highly enhances the spectral amplitude in+2 ,+3Nyquist areas, the spectrum in particularly+2nd area has obtained comparatively strengthening uniform flat.This realization is just properly termed as Direct conversion for DAC.Spectrum of the QPTL spectrum than BPBL preferably (i.e. evenly flatly) strengthens+2, spectral amplitude in+3Nyquist areas.It is thus a kind of preferably up-conversion characteristic.QPBL mainly enhances the spectral amplitude in+4 ,+5Nyquist areas, it is thus possible to realize the up-conversion characteristic of higher carrier wave.

Unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.

Claims (1)

1. a kind of control method of mixer/dac on-off circuit, the frequency conversion during the data signal of achievable input is turned over to analog signal is exported, it is characterised in that be controlled by following steps：

(1) DAC switch single channel is built, the DAC switches single channel includes：Unit decoding circuit, mode selection circuit and switch arrays, the input and the data signal D of input of the unit decoding circuit, and the clock signal clk of input are connected；The input of the mode selection circuit and 8 tunnel output signal V1~V8 of unit decoding circuit, and mode control signal E1~E3 are connected；The switch arrays are made up of 8 metal-oxide-semiconductor S1~S8, S1~S8 source electrode is connected with current source, S1~S8 grid is connected with switch selection signal G1~G8 by sequence number is corresponding respectively, wherein, S1, S3, S5, S7 are one group, it is another group that S1, S3, S5, S7 drain electrode, which are connected to form output end Ip, S2, S4, S6, S8, and S2, S4, S6, S8 drain electrode are connected to form output end In；

(2) when unit decoding circuit has data signal D inputs, enter row decoding to the clk_S90 of D, clk and clk after 90 ° of phase shifts to cause within clock signal clk every 1/4 cycle, 1 road useful signal output and 7 road invalid signals outputs are produced, and output signal V1~V8 of generation is output to mode selection circuit；

(3) mode selection circuit is when receiving V1~V8 of input, while selecting the switch selection signal for determining switch arrays output mode according to the mode control signal of input E1~E3；The switch arrays output mode includes：Normal mode, back to zero pattern, two-way bipolarity level mode, four phase bipolarity level modes and the polarity level mode of four phase three；

If output mode is normal mode, in a cycle, switch selection signal only makes one group of switch in the conduction state all the time；

If output mode is back to zero pattern, in one cycle, switch selection signal makes one group of switch in the conduction state in preceding half period, two groups of switches is in closed mode in second half of the cycle；

If output mode is two-way bipolarity level mode, in one cycle, switch selection signal makes one group of switch in the conduction state in preceding half period, makes another group of switch in the conduction state in second half of the cycle；

If the phase bipolarity level mode of output mode signal behavior four, in one cycle, switch selection signal makes one group of switch in the conduction state in the 1/4th cycle and the 3/4th cycle, in the 2/4th cycle and the 4/4th Cycle makes another group of switch in the conduction state；

If the polarity level mode of four phase of output mode signal behavior three, then in one cycle, switch selection signal makes two groups of switches successively in the conduction state respectively in the 1/4th cycle and the 3/4th cycle, two groups of switches is in closed mode in the 2/4th cycle and the 4/4th cycle；

(4) switch arrays receive the switch selection signal G1~G8 exported by mode selection circuit, and according to switch selection signal G1~G8 generations analog output signal corresponding with input data signal D；Switch arrays are according to switch selection signal G1~G8 output rule：

When any one in G1, G3, G5, G7 is effective, then corresponding metal-oxide-semiconductor will be turned in S1, S3, S5, S7, and S2, S4, S6, S8 are turned off, and Ip exports corresponding analog quantity, and In is without output；

When any one in G2, G4, G5, G8 is effective, then corresponding metal-oxide-semiconductor will be turned in S2, S4, S6, S8, and S1, S3, S5, S7 are turned off, and In exports corresponding analog quantity, and Ip is without output.

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