CN102355262B - Control method for mixing digital-to-analogue converter (DAC) switching circuit - Google Patents

Abstract

The invention discloses a control method for a mixing digital-to-analogue converter (DAC) switching circuit. The control method comprises that: a DAC switching circuit is constructed, wherein the DAC switching circuit comprises a unit decoding circuit, a mode selection circuit and a switch array; the unit decoding circuit decodes an input digital signal and outputs the signal to the mode selection circuit; the mode selection circuit selects an output mode of the switch array according to a mode control signal, converts the signal input by the unit decoding unit into a switching selection signal according to the output mode and outputs the switching selection signal to the switch array; and the switch array generates analogue output according to the switching selection signal. By the control method, the shortcomings that the output noises of a conventional high-performance DAC are relatively more dependent on input control switching signals and that an output signal frequency range is limited are overcome, the static linearity of the DAC is improved, the dynamic range of the static linearity is widened, the function of multimode up-conversion is realized at the same time, and the DAC is endowed with the function of a mixer.

Description

A kind of control method of mixer/dac switching circuit

Technical field

The present invention relates to a kind of control method of mixer/dac switching circuit.

Background technology

In the design of electronic circuit, noise problem more and more becomes the bottleneck of design, and it can be on the rise along with the step-down of the increase of dynamic range and the energy of signal.In mixed-signal applications, the continuous variation of digital signal is the main noise source that affects the normal work of analog signal.In digital to analog converter DAC, the switch of control simulation signal output is by Digital Signals.The digital signal constantly changing will produce noise at simulation output.In the attainable system of reality, can not isolate these noises completely, because they are to be coupled to wherein by the control unit of analog signal, also because of the intrinsic power consumption of digital circuit, temporal correlation and resistance drop and the charge injection effect of load, these will cause variation and the body effect of reference signal, supply voltage, bias voltage, clock phase, transition region phase place, and produce noise in output.Digital signal because will causing the dependence of load variations to data and clutter, inevitable parasitic problem and non-ideal circuitry is coupled to the modulation problems of signal, so will add noise to analog signal in this manner.

Except noise problem, in some traditional electronic equipments conventionally application be such system, after digital signal is transformed into analog signal, then carry out the process of moving of analog signal.In traditional mobile phone, conventionally convert digital signal to analog signal with a DAC chip and send out, but before transmitting, need a mixer chip that the frequency translation of baseband signal is gone on the frequency that is applicable to launching.So using two or more chips to complete such function may be poor efficiency.

The process that DAC converts digital signal to analog signal is to keep the value of digital input signals to realize by the clock cycle in each conversion.And such keep-process is to be realized by switch, what in time domain, switch function and input signal completed is the process of convolution, is the process of the filtering modulation to input signal and in frequency domain, switching signal completes.

Although traditional two differential switch structures have the ability to eliminate due to the caused nonlinear problem of undesirable switch, for those to input relevant non-linear of data have little effect.The frequency of signal of output can only be positioned at the first Nyquist scope simultaneously, cannot realize upconversion function to output signal.

Summary of the invention

Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of control method of mixer/dac switching circuit is provided.Employing the invention solves traditional high-performance DAC output noise input control switching signal is had to the shortcoming compared with strong dependency, solve the range limited deficiency of its output signal frequency, the static linearity and the dynamic range thereof of DAC are not only improved, realize the function of various modes up-conversion simultaneously, made DAC there is the function of frequency mixer simultaneously.

Technical solution of the present invention is:

A control method for mixer/dac switching circuit, the digital signal that can realize input turns over the frequency conversion output in process to analog signal, controls by following steps:

(1) build DAC switching circuit, described DAC switching circuit comprises: cell decode circuit, mode selection circuit and switch arrays, and the input of described cell decode circuit and the digital signal D of input, and the clock signal clk of input is connected; 8 tunnel output signal V1～V8 of the input of described mode selection circuit and cell decode circuit, and mode control signal E1～E3 is connected; Described switch arrays are made up of 8 metal-oxide-semiconductor S1～S8, the source electrode of S1～S8 is all connected with current source, the grid of S1～S8 selects signal G1～G8 to be connected by sequence number is corresponding with switch respectively, wherein, S1, S3, S5, S7 are one group, the drain electrode of S1, S3, S5, S7 is connected to form output Ip, and S2, S4, S6, S8 are another group, and the drain electrode of S2, S4, S6, S8 is connected to form output In;

(2) in the time that cell decode circuit has digital signal D input, D, clk and the clk_S90 of clk after 90 ° of phase shifts are carried out to decoding to be made within every 1/4 cycle of clock signal clk, produce 1 road useful signal output and 7 road invalid signals outputs, and the output signal V1～V8 of generation is outputed to mode selection circuit;

(3) mode selection circuit, in the time receiving the V1～V8 of input, selects the switch for determining switch arrays output mode to select signal according to the mode control signal E1 of input～E3 simultaneously; Described switch arrays output mode comprises: normal mode, back to zero pattern, two-phase bipolarity level mode, four phase bipolarity level modes and four, three polarity level modes mutually;

If output mode is normal mode,, in one-period, switch selects signal only to make one group of switch all the time in conducting state;

If output mode is back to zero pattern, in one-period, switch select signal make one group of switch in front half period in conducting state, make two groups of switches in rear half period all in closed condition;

If output mode is two-phase bipolarity level mode,, in one-period, switch selects signal to make one group of switch in conducting state in front half period, makes another group switch in conducting state in rear half period;

If output mode is four phase bipolarity level modes,, in one-period, switch selects signal to make one group of switch in conducting state in the 1/4th cycle and the 3/4th cycle, makes another group switch in conducting state in the 2/4th cycle and the 4/4th cycle;

If output mode is four phase three polarity level modes, in one-period, switch selects signal to make respectively two groups of switches successively in conducting state in the 1/4th cycle and the 3/4th cycle, makes two groups of switches all in closed condition in the 2/4th cycle and the 4/4th cycle;

(4) switch arrays receive the switch of being exported by mode selection circuit and select signal G1～G8, and select signal G1～G8 to produce the analog output signal corresponding with supplied with digital signal D according to switch; Switch arrays select the output rule of signal G1～G8 to be according to switch:

In the time that in G1, G3, G5, G7, any one is effective, in S1, S3, S5, S7, corresponding metal-oxide-semiconductor is by conducting, and S2, S4, S6, S8 all end, and Ip exports corresponding analog quantity, In no-output;

In the time that in G2, G4, G5, G8, any one is effective, in S2, S4, S6, S8, corresponding metal-oxide-semiconductor is by conducting, and S1, S3, S5, S7 all end, and In exports corresponding analog quantity, Ip no-output.

The present invention compared with prior art tool has the following advantages:

1, this technology has solved the shortcoming that output noise that traditional double differential switch exists relies on input signal, select the conducting state of metal-oxide-semiconductor in signal selecting switch array by switch, realize the conversion to fixed frequency burr by noise by the output of different switches, improved the static linearity and the dynamic range of output.

2, the invention solves the problem of the limited and frequency conversion frequency band deficiency of four switching technique variable mode of the prior art, can realize the frequency conversion output of five kinds of patterns, make the analog signal of output contain the first to the 5th all intervals of Nyquist.

3, the present invention is by the combination of cell decode circuit, mode selection circuit and switch arrays, realized supplied with digital signal to the conversion of analog signal and the mixing function to analog signal, reduced the design difficulty of baseband transmitter.

Brief description of the drawings

Fig. 1 is circuit diagram of the present invention;

Fig. 2 is cell decode circuit structure diagram;

Fig. 3 is mode selection circuit structure chart;

Fig. 4 is different output mode oscillograms;

Fig. 5 is different output mode switch function spectrograms;

Fig. 6 is flow chart of the present invention.

Embodiment

Just by reference to the accompanying drawings the present invention is described further below.

As follows, be english abbreviation explanation of the present invention:

DAC:Digital to Analog Converter, digital-to-analog converter

RZ:Return to zero, back to zero

BPBL:Biphase Bipolar Level, two-way bipolar level

QPBL:Quad-phase Bipolar level, four mutually bipolar level

QPTL:Quad-phase triple level, four phase three utmost point level

Nyquist: Nyquist

As Fig. 6, it is flow chart of the present invention.The first step: build DAC switching circuit; Second step: cell decode circuit decode; The 3rd step: mode selection circuit carry out model selection; The 4th step: switch arrays output.Just be introduced respectively below.

(1) build DAC switching circuit

As shown in Figure 1, be circuit diagram of the present invention.Circuit comprises: cell decode circuit, mode selection circuit and switch arrays.

The digital signal D of cell decode circuit input end and input, and the clock signal clk of input is connected, output is used for exporting decoding output signal V1～V8.The input of mode selection circuit is connected with the output of cell decode circuit, receives decoding output signal V1～V8, and meanwhile, mode selection circuit also has the input of three tunnels for receiving mode control signal E1～E3.The output of mode selection circuit is selected signal G1～G8 for 8 way switch of output control switch array.Switch arrays are made up of 8 metal-oxide-semiconductor S1～S8, and same G1～G8 is connected on demand respectively for the grid of S1～S8.

(2) cell decode circuit decode method

The input signal of cell decode circuit is digital signal D and clock signal clk, produce 8 road decoding output signal V1～V8 within every 1/4 cycle through decoding, select 1 metal-oxide-semiconductor conducting, 7 metal-oxide-semiconductors are closed, even will comprise 1 road useful signal and 7 road invalid signals in the V1～V8 of each output, the method for designing of cell decode circuit is as follows for this reason:

If 1 road useful signal is defined as logical zero, invalid signals is defined as logical one, and the clock signal clk of input is carried out to 90 ° of phase shifts, is D, clk and clk_S90 thereby form three tunnel decoding input signals.

In the time that D, clk, clk_S90 are divided into 1,1,0, make V1 effective if select, V2～V8 is invalid, and according to the Karnaugh map shown in table 1, we select circle " 0 ", therefore

so

in the time that D, clk, clk_S90 are respectively 010,111,011,101,001,100,000, allow V2～V8 conducting successively, apply successively Kano primitive reason, release decoding circuit module.

Table 1

As shown in Figure 2, be a kind of way of realization of cell decode circuit, the decoding relation of realization is as follows:

(3) mode selecting method of mode selection circuit

Mode selection circuit is determined the output mode of switch arrays under the control of mode control signal E1～E3, and the decoding output signal V1～V8 of input is selected to the output of G1～G8.The present invention adopts three or eight decoders to receive the mode control signal E1～E3 of input, five output signal controls that utilize three or eight decoders are the PMOS pipe t1-t14 in mode selection circuit as shown in Figure 3, MUX in Fig. 3 is alternative data selector, and the annexation of V1～V8 and PMOS pipe t1-t14 is as Fig. 3.

In the time of E1E2E3=000, D1=0, other four output signals are 1.Therefore switch t1-t8 conducting, other switch cut-offs, are output as normal mode.

In the one-period of normal mode, switch selects signal only to make one group of switch all the time in conducting state.The switch function P of normal mode _zRH(t) as follows:

$P_{\mathrm{ZRH}}\left(t\right)=\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=\left\{\begin{array}{c}\mathrm{1,0}<t<T_R\\ 0,t<0\mathrm{ort}>T_R\end{array}\right.,$

$P_{\mathrm{ZRH}}\left(t\right)=\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=u\left(t\right)-u(t-T_R),$

Wherein, T _rfor the clock cycle,

P _zRH(t) Laplace transform is as follows:

$L\left\{\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)\right\}=L\{u\left(t\right)-u(t-T_R)\}=\frac{1}{s}-\frac{1}{s}{e}^{-{\mathrm{sT}}_R}=\frac{1-e^{{-\mathrm{sT}}_R}}{s},$

Fourier transform is as follows:

$\begin{array}{c}F\left\{\underset{(0,T_R)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)\right\}=T_R\frac{e^{\mathrm{jw}\frac{T_R}{2}}-e^{-\mathrm{jw}\frac{T_R}{2}}}{2\mathrm{jw}\frac{T_R}{2}}{e}^{-\mathrm{jw}\frac{T_R}{2}}=T_R\frac{\sin \left(w\frac{T_R}{2}\right)}{w\frac{T_R}{2}}{e}^{-\mathrm{jw}\frac{T_R}{2}}\\ =T_R\mathrm{Sa}\left(w\frac{T_R}{2}\right)e^{-\mathrm{jw}\frac{T_R}{2}}=P_{\mathrm{ZRH}}\left(w\right)\end{array}$

According to the character of sampling function, work as w=nw _r, (n ∈ z, n ≠ 0), sampling function has zero point, and the amplitude envelops of whole function with-20dB/Decade or-speed of 6dB/Octant successively decreases.Nyquist frequency is wR/2.

In the time of E1E2E3=001, D2=0, other four output signals are 1.Therefore switch t1-t4, t10 and t11 conducting, output BPBL pattern.

In the one-period of BPBL pattern, switch selects signal to make one group of switch in conducting state in front half period, makes another group switch in conducting state in rear half period

Switch function P _bPBL(t) as follows:

Its Fourier transform is

$\begin{array}{c}F\left\{P_{\mathrm{BPBL}}\left(t\right)\right\}=\frac{1-{2e}^{-{\mathrm{sT}}_R/2}+e^{-{\mathrm{sT}}_R}}{s}){|}_{s=\mathrm{jw}}=\frac{1-2e^{-\mathrm{jw}{T}_R/2}+e^{-\mathrm{jw}{T}_R}}{\mathrm{jw}}\\ =\frac{{(1-e^{-\mathrm{jw}{T}_R/2})}^2}{\mathrm{jw}}=T_R\frac{{\sin }^2(w{T}_R/4)}{w{T}_R/4}{e}^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}\end{array},$ ?

$F\left\{P_{\mathrm{BPBL}}\left(t\right)\right\}=P_{\mathrm{BPBL}}\left(w\right)=T_R\mathrm{Sa}\left(\mathrm{\&pi;}\frac{w}{2w_R}\right)\sin \left(\mathrm{\&pi;}\frac{w}{2w_R}\right)e^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}$

Under this pattern, the amplitude spectrum of switch function has suppressed direct current signal completely, larger inhibition the interval frequency spectrum of the first Nyquist, relatively high enhancing second and the spectral amplitude of the 3rd Nyquist, particularly the second Nyquist region has obtained comparatively smooth enhancing.

In the time of E1E2E3=010, D3=0, other four output signals are 1.Therefore switch t1, t2, t5, t6, t9 and t11 conducting, output QPBL pattern.

In the one-period of QPBL pattern, switch selects signal to make one group of switch in conducting state in the 1/4th cycle and the 3/4th cycle, makes another group switch in conducting state in the 2/4th cycle and the 4/4th cycle.

Switch function P _qPBL(t) r is as follows:

$P_{\mathrm{QPBL}}\left(t\right)=u\left(t\right)-2u(t-\frac{T_R}{4})+2u(t-\frac{T_R}{2})-2u(t-\frac{3T_R}{4})+u(t-T_R)$

Fourier transform is

$\begin{array}{c}F\left\{P_{\mathrm{QPBL}}\left(t\right)\right\}=\frac{1+{2e}^{-{\mathrm{sT}}_R/2}-{2e}^{-{\mathrm{sT}}_R/4}-{2e}^{-{3\mathrm{sT}}_R/4}+e^{-{\mathrm{sT}}_R}}{s}){|}_{s=\mathrm{jw}}\\ =\frac{{(e^{{\mathrm{sT}}_R/8}-e^{-{\mathrm{sT}}_R/8})}^2(e^{{\mathrm{sT}}_R/4}+e^{-{\mathrm{sT}}_R/4})}{s}{e}^{-{\mathrm{sT}}_R/2}{|}_{s=\mathrm{jw}}\end{array}$

$\begin{array}{c}F\left\{P_{\mathrm{QPBL}}\left(t\right)\right\}=T_R\frac{\sin ({\mathrm{wT}}_R/8)}{{\mathrm{wT}}_R/8}\sin ({\mathrm{wT}}_R/8)\cos ({\mathrm{wT}}_R/4)e^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}\\ =T_R\mathrm{Sa}\left(\mathrm{\&pi;}\frac{w}{{4w}_R}\right)\sin \left(\mathrm{\&pi;}\frac{w}{{4w}_R}\right)\cos \left(\mathrm{\&pi;}\frac{w}{2w_R}\right)e^{\mathrm{j\&pi;}/2-\mathrm{jw}{T}_R/2}\end{array}$

Under this pattern, mainly strengthened the 4th, the frequency spectrum in the 5th Nyquist region.

In the time of E1E2E3=011, D4=0, other four output signals are 1.Therefore switch t1-t8, t13, t14 conducting, output RZ pattern.

In the one-period of RZ pattern, switch select signal make one group of switch in front half period in conducting state, make two groups of switches in rear half period all in closed condition.

The switch function P of RZ pattern _rZ(t) as follows:

$P_{\mathrm{RZ}}\left(t\right)=\underset{(0,T_R/2)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=\left\{\begin{array}{c}\mathrm{1,0}<t<T_R/2\\ 0,t<0\mathrm{ort}>T_R/2\end{array}\right.,$ Therefore

$P_{\mathrm{RZ}}\left(t\right)=\underset{(0,T_R/2)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=u\left(t\right)-u(t-T_R/2),$ Fourier transform is

$\begin{array}{c}F\left\{\underset{(0,T_R/2)}{\overset{1}{\mathrm{\&Pi;}}}\right\}=\frac{T_R}{2}\frac{e^{\mathrm{jw}\frac{T_R}{4}}-e^{-\mathrm{jw}\frac{T_R}{4}}}{2\mathrm{jw}\frac{T_R}{4}}{e}^{-\mathrm{jw}\frac{T_R}{4}}\\ =\frac{T_R}{2}\mathrm{Sa}\left(w\frac{T_R}{4}\right)e^{-\mathrm{jw}\frac{T_R}{4}}=P_{\mathrm{RZ}}\left(w\right)\end{array}$

The spectral bandwidth of the Frequency spectrum ratio zeroth order Holdover mode of back to zero pattern has increased by 1 times, and amplitude is reduced to half simultaneously, and therefore the former has obtained inhibition with respect to the first Nyquist frequency spectrum of the latter, and the frequency spectrum of two or three Nyquists has obtained enhancing.

In the time of E1E2E3=100, D5=0, other four output signals are 1.Therefore switch t1-t4, t7, t8, t10, t12, t14 conducting, output QPTL pattern.

In the one-period of QPTL pattern, switch selects signal to make respectively two groups of switches successively in conducting state in the 1/4th cycle and the 3/4th cycle, makes two groups of switches all in closed condition in the 2/4th cycle and the 4/4th cycle.

The switch function P of QPTL pattern _qPTL(t) as follows:

$P_{\mathrm{QPTL}}\left(t\right)=\underset{(0,T_R/4)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)-\underset{(0,T_R/4)}{\overset{1}{\mathrm{\&Pi;}}}\left(t\right)=u\left(t\right)-u(t-\frac{T_R}{4})-u(t-\frac{T_R}{2})+u(t-\frac{{3T}_R}{4})$

Fourier transform is

$\begin{array}{c}F\left\{P_{\mathrm{QPTL}}\left(t\right)\right\}=\frac{1-e^{-{\mathrm{sT}}_R/2}-e^{-{\mathrm{sT}}_R/4}+e^{-{3\mathrm{sT}}_R/4}}{s}){|}_{s=\mathrm{jw}}\\ =\frac{{(e^{{\mathrm{sT}}_R/8}-e^{-{\mathrm{sT}}_R/8})}^{}(e^{{\mathrm{sT}}_R/4}-e^{-{\mathrm{sT}}_R/4})}{s}{e}^{-3{\mathrm{sT}}_R/8}{|}_{s=\mathrm{jw}}\end{array}$

$\begin{array}{c}F\left\{P_{\mathrm{QPTL}}\left(t\right)\right\}=\frac{T_R}{2}\frac{\sin ({\mathrm{wT}}_R/8)}{{\mathrm{wT}}_R/8}\sin ({\mathrm{wT}}_R/4)e^{\mathrm{j\&pi;}/2-\mathrm{<figure-callout\; id="3"\; label="j"\; filenames="DEST\_PATH\_HSB0000121995480000011.png,HSA00000529021000042.png"\; state="\{\{state\}\}">j</figure-callout>}3{\mathrm{wT}}_R/8}\\ =\frac{T_R}{2}\mathrm{Sa}\left(\mathrm{\&pi;}\frac{w}{4w_R}\right)\sin \left(\mathrm{\&pi;}\frac{w}{{4w}_R}\right)e^{\mathrm{j\&pi;}/2-\mathrm{<figure-callout\; id="3"\; label="j"\; filenames="DEST\_PATH\_HSB0000121995480000011.png,HSA00000529021000042.png"\; state="\{\{state\}\}">j</figure-callout>}3{\mathrm{wT}}_R/8}\end{array}$

The amplitude spectrum of this pattern has better strengthened second and the amplitude spectrum in the 3rd Nyquist district than two-way bipolar amplitude spectrum.

(4) switch arrays are selected the output control under signal at switch

As mentioned above, switch arrays are made up of 8 metal-oxide-semiconductor S1～S8.In S1～S8, the source electrode of S1～S8 is all connected with current source, the grid of S1～S8 selects signal G1～G8 to be connected by sequence number is corresponding with switch respectively, wherein, S1, S3, S5, S7 are one group, the drain electrode of S1, S3, S5, S7 is connected to form output Ip, and S2, S4, S6, S8 are another group, and the drain electrode of S2, S4, S6, S8 is connected to form output In.

Select the output rule under signal G1～G8 control to be at switch:

We are standardized as 1 by imitated output quantity, and no-output is 0

In the time that in G1, G3, G5, G7, any one is effective, in S1, S3, S5, S7, corresponding metal-oxide-semiconductor is by conducting, and S2, S4, S6, S8 all end, and Ip exports corresponding analog quantity, In no-output, difference be output as+1;

In the time that in G2, G4, G5, G8, any one is effective, in S2, S4, S6, S8, corresponding metal-oxide-semiconductor is by conducting, and S1, S3, S5, S7 all end, and In exports corresponding analog quantity, Ip no-output, and difference is output as-1.

In conjunction with foregoing circuit, following table 2 has provided D, clk, clk_90, the V1～V8 output relation under each pattern:

D?clk?clk_S90	110	111	101	100	010	011	001	000
									V1	0	1	1	1	1	1	1	1
V2	1	1	1	1	0	1	1	1
									V3	1	0	1	1	1	1	1	1
V4	1	1	1	1	1	0	1	1
									V5	1	1	0	1	1	1	1	1
V6	1	1	1	1	1	1	0	1
									V7	1	1	1	0	1	1	1	1
V8	1	1	1	1	1	1	1	0
									Normal?output	+1	+1	+1	+1	-1	-1	-1	-1
QPBL?output	+1	-1	+1	-1	-1	+1	-1	+1
									BPBL?output	+1	+1	-1	-1	-1	-1	+1	+1
QPTL?output	+1	0	-1	0	-1	0	+1	0
									RZ?output	+1	+1	0	0	-1	-1	0	0

Table 2

Fig. 4 has provided the oscillogram under each output mode under different D, clk, clk_90.Associative list 2 and Fig. 4 can find out that decoding circuit will be introduced the data that change on switch, but can't change output state when input data are not in the time that two continuous clock cycles change.When data are in the time that two continuous clock cycle change, the variation of switch upper domination number certificate has caused the variation of output state.Therefrom can find out, no matter whether input data variation, signal clock on switch is ceaselessly complementary to be changed and does not change with input data mode, burr associated with the data so is just converted into the burr of the clutter of a fixed frequency, he is 4 times of clock frequency, be a high frequency clutter, he is away from conventional available signal frequency band, thereby easily by filtering.

Fig. 5 has provided under all output modes, the spectrogram of switch function under frequency domain.As can be seen from the figure, full cycle zeroth order keeps rectangular pulse be the frequency spectrum exported under normal pattern+1Nyquist district is the strongest, Here it is base band Nyquist district that conventional DAC works.The spectral amplitude in other Nyquist districts is subject to compared with high attenuation.Under RZ pattern+spectral amplitude of 1 district Nyquist relatively with Normal pattern under+1Nyquist spectrum is inhibited, and+2, obtained enhancing under the relative and Normal pattern of the spectral amplitude in+3Nyquist district.The amplitude spectrum of BPBL has suppressed direct current signal completely, the spectrum amplitude in suppressed significantly+1Nyquist district and relatively highland strengthened+2, the spectral amplitude in+3Nyquist district, the spectrum in particularly+2nd district obtained comparatively evenly flatly strengthening.This realization just can be called Direct conversion for DAC.The spectrum of QPTL is than the spectrum of the BPBL spectral amplitude in (more evenly flatly) enhancing+2 ,+3Nyquist district better.Because of but one up-conversion characteristic better.QPBL mainly strengthened+and 4, the spectral amplitude in+5Nyquist district, thereby can realize the up-conversion characteristic of higher carrier wave.

The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.

Claims (1)

1. a control method for mixer/dac switching circuit, can realize the digital signal of input and export to the frequency conversion in analog signal transfer process, it is characterized in that controlling by following steps:

(1) build DAC switching circuit, described DAC switching circuit comprises: cell decode circuit, mode selection circuit and switch arrays, and the input of described cell decode circuit and the digital signal D of input, and the clock signal clk of input is connected; 8 tunnel output signal V1～V8 of the input of described mode selection circuit and cell decode circuit, and mode control signal E1～E3 is connected; Described switch arrays are made up of 8 metal-oxide-semiconductor S1～S8, the source electrode of S1～S8 is all connected with current source, the grid of S1～S8 selects signal G1～G8 to be connected by sequence number is corresponding with switch respectively, wherein, S1, S3, S5, S7 are one group, the drain electrode of S1, S3, S5, S7 is connected to form output Ip, and S2, S4, S6, S8 are another group, and the drain electrode of S2, S4, S6, S8 is connected to form output In;

(2) in the time that cell decode circuit has digital signal D input, D, clk and the clk_S90 of clk after 90 ° of phase shifts are carried out to decoding to be made within every 1/4 cycle of clock signal clk, produce 1 road useful signal output and 7 road invalid signals outputs, and the output signal V1～V8 of generation is outputed to mode selection circuit;

(3) mode selection circuit, in the time receiving the V1～V8 of input, selects the switch for determining switch arrays output mode to select signal according to the mode control signal E1 of input～E3 simultaneously; Described switch arrays output mode comprises: normal mode, back to zero pattern, two-phase bipolarity level mode, four phase bipolarity level modes and four, three polarity level modes mutually;

If output mode is normal mode,, in one-period, switch selects signal only to make one group of switch all the time in conducting state;

If output mode is back to zero pattern, in one-period, switch select signal make one group of switch in front half period in conducting state, make two groups of switches in rear half period all in closed condition;

If output mode is two-phase bipolarity level mode,, in one-period, switch selects signal to make one group of switch in conducting state in front half period, makes another group switch in conducting state in rear half period;

If output mode is four phase bipolarity level modes,, in one-period, switch selects signal to make one group of switch in conducting state in the 1/4th cycle and the 3/4th cycle, makes another group switch in conducting state in the 2/4th cycle and the 4/4th cycle;

If output mode is four phase three polarity level modes, in one-period, switch selects signal to make respectively two groups of switches successively in conducting state in the 1/4th cycle and the 3/4th cycle, makes two groups of switches all in closed condition in the 2/4th cycle and the 4/4th cycle;

(4) switch arrays receive the switch of being exported by mode selection circuit and select signal G1～G8, and select signal G1～G8 to produce the analog output signal corresponding with supplied with digital signal D according to switch; Switch arrays select the output rule of signal G1～G8 to be according to switch:

In the time that in G1, G3, G5, G7, any one is effective, in S1, S3, S5, S7, corresponding metal-oxide-semiconductor is by conducting, and S2, S4, S6, S8 all end, and Ip exports corresponding analog quantity, In no-output;

In the time that in G2, G4, G6, G8, any one is effective, in S2, S4, S6, S8, corresponding metal-oxide-semiconductor is by conducting, and S1, S3, S5, S7 all end, and In exports corresponding analog quantity, Ip no-output.

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